freedreno/a3xx/compiler: fix CMP

The 1st src to add.s needs (r) flag (repeat), otherwise it will end up:

  add.s dst.xyzw, tmp.xxxx -1

instead of:

  add.s dst.xyzw, tmp.xyzw, -1

Also, if we are using a temporary dst to avoid clobbering one of the src
registers, we actually need to use that as the dst for the sel
instruction.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_compiler.c b/src/gallium/drivers/freedreno/a3xx/fd3_compiler.c
index eabe21cb7e98cc56fb28291d1f29557999478d9a..07bede4a4c80ab8c717114523a44bca6dee3b7c4 100644 (file)
--- a/src/gallium/drivers/freedreno/a3xx/fd3_compiler.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_compiler.c
@@ -790,13 +790,13 @@ trans_cmp(const struct instr_translater *t,
        instr = ir3_instr_create(ctx->ir, 2, OPC_ADD_S);
        instr->repeat = 3;
        add_dst_reg(ctx, instr, &tmp_dst, 0);
-       add_src_reg(ctx, instr, &tmp_src, 0);
+       add_src_reg(ctx, instr, &tmp_src, 0)->flags |= IR3_REG_R;
        ir3_reg_create(instr, 0, IR3_REG_IMMED)->iim_val = -1;
 
        /* sel.{f32,f16} dst, src2, tmp, src1 */
        instr = ir3_instr_create(ctx->ir, 3, ctx->so->half_precision ?
                        OPC_SEL_F16 : OPC_SEL_F32);
-       vectorize(ctx, instr, &inst->Dst[0].Register, 3,
+       vectorize(ctx, instr, dst, 3,
                        &inst->Src[2].Register, 0,
                        &tmp_src, 0,
                        &inst->Src[1].Register, 0);