TLB: Make a TLB base class and put a virtual demapPage function in it.

--HG--
extra : convert_revision : cc0e62a5a337fd5bf332ad33bed61c0d505a936f

diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
index 2e974effe3f6afe2b1c1715cc7c990182b7430ff..77bf5e285310f43a7789debb206a7bc2d2c191f1 100644 (file)
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -58,7 +58,7 @@ bool uncacheBit40 = false;
 #define MODE2MASK(X)                   (1 << (X))
 
 TLB::TLB(const Params *p)
-    : SimObject(p), size(p->size), nlu(0)
+    : BaseTLB(p), size(p->size), nlu(0)
 {
     table = new TlbEntry[size];
     memset(table, 0, sizeof(TlbEntry[size]));

diff --git a/src/arch/alpha/tlb.hh b/src/arch/alpha/tlb.hh
index 69a33f32d86fbe4726083fdaf683acc58e49247a..e61ae5c6dbb0da4ddb029af886fd70f2cf15c912 100644 (file)
--- a/src/arch/alpha/tlb.hh
+++ b/src/arch/alpha/tlb.hh
@@ -44,7 +44,7 @@
 #include "params/AlphaDTB.hh"
 #include "params/AlphaITB.hh"
 #include "sim/faults.hh"
-#include "sim/sim_object.hh"
+#include "sim/tlb.hh"
 
 class ThreadContext;
 
@@ -52,7 +52,7 @@ namespace AlphaISA
 {
     class TlbEntry;
 
-    class TLB : public SimObject
+    class TLB : public BaseTLB
     {
       protected:
         typedef std::multimap<Addr, int> PageTable;
@@ -79,6 +79,12 @@ namespace AlphaISA
         void flushProcesses();
         void flushAddr(Addr addr, uint8_t asn);
 
+        void demapPage(Addr vaddr, uint64_t asn)
+        {
+            assert(asn < (1 << 8));
+            flushAddr(vaddr, asn);
+        }
+
         // static helper functions... really EV5 VM traits
         static bool validVirtualAddress(Addr vaddr) {
             // unimplemented bits must be all 0 or all 1

diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc
index 4923e3e3ac94553a65b9ae00c147dbb242151dd1..d78aefab4b2a71685408e23a9389dc7d90d33dfe 100644 (file)
--- a/src/arch/mips/tlb.cc
+++ b/src/arch/mips/tlb.cc
@@ -62,7 +62,7 @@ using namespace MipsISA;
 #define MODE2MASK(X)                   (1 << (X))
 
 TLB::TLB(const Params *p)
-    : SimObject(p), size(p->size), nlu(0)
+    : BaseTLB(p), size(p->size), nlu(0)
 {
     table = new MipsISA::PTE[size];
     memset(table, 0, sizeof(MipsISA::PTE[size]));

diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh
index d6f9ac101f8ad0d810844dc7258db0a4aa75537c..4333777ff05e562fd93e3bf0066d788402193e79 100644 (file)
--- a/src/arch/mips/tlb.hh
+++ b/src/arch/mips/tlb.hh
@@ -80,7 +80,7 @@ struct TlbEntry
 
 };
 
-class TLB : public SimObject
+class TLB : public BaseTLB
 {
   protected:
     typedef std::multimap<Addr, int> PageTable;
@@ -120,6 +120,10 @@ class TLB : public SimObject
     void insert(Addr vaddr, MipsISA::PTE &pte);
     void insertAt(MipsISA::PTE &pte, unsigned Index, int _smallPages);
     void flushAll();
+    void demapPage(Addr vaddr, uint64_t asn)
+    {
+        panic("demapPage unimplemented.\n");
+    }
 
     // static helper functions... really
     static bool validVirtualAddress(Addr vaddr);

diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 740da37ab14f9ce31118be2dc6b79c4e6e7ad079..22df4490872bdec9d1b2518a82b460fdbe73092e 100644 (file)
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -46,7 +46,7 @@
 namespace SparcISA {
 
 TLB::TLB(const Params *p)
-    : SimObject(p), size(p->size), usedEntries(0), lastReplaced(0),
+    : BaseTLB(p), size(p->size), usedEntries(0), lastReplaced(0),
       cacheValid(false)
 {
     // To make this work you'll have to change the hypervisor and OS

diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index b38ee15dc87c27c01ad4dd3e7f8c74256d3d4b55..2f7d08320fbeed72df29bf2b3a0501cd50b73ac0 100644 (file)
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -39,7 +39,7 @@
 #include "params/SparcDTB.hh"
 #include "params/SparcITB.hh"
 #include "sim/faults.hh"
-#include "sim/sim_object.hh"
+#include "sim/tlb.hh"
 
 class ThreadContext;
 class Packet;
@@ -47,7 +47,7 @@ class Packet;
 namespace SparcISA
 {
 
-class TLB : public SimObject
+class TLB : public BaseTLB
 {
 #if !FULL_SYSTEM
     //These faults need to be able to populate the tlb in SE mode.
@@ -152,6 +152,11 @@ class TLB : public SimObject
     typedef SparcTLBParams Params;
     TLB(const Params *p);
 
+    void demapPage(Addr vaddr, uint64_t asn)
+    {
+        panic("demapPage(Addr) is not implemented.\n");
+    }
+
     void dumpAll();
 
     // Checkpointing

diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index acac3081a7ebaeff85e05aab346b9bf6107a2a6c..208dec1777d5f5099f363f20b42fa2a75f8a98b5 100644 (file)
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -76,7 +76,7 @@
 
 namespace X86ISA {
 
-TLB::TLB(const Params *p) : SimObject(p), configAddress(0), size(p->size)
+TLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size)
 {
     tlb = new TlbEntry[size];
     std::memset(tlb, 0, sizeof(TlbEntry) * size);
@@ -169,7 +169,7 @@ TLB::invalidateNonGlobal()
 }
 
 void
-TLB::demapPage(Addr va)
+TLB::demapPage(Addr va, uint64_t asn)
 {
 }
 

diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index d08d6fa686944afcdb5172f1299e1e1334a5c686..f6ccd5731da1b880b6fa6f270602affd6a19a60b 100644 (file)
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -70,6 +70,7 @@
 #include "params/X86DTB.hh"
 #include "params/X86ITB.hh"
 #include "sim/faults.hh"
+#include "sim/tlb.hh"
 #include "sim/sim_object.hh"
 
 class ThreadContext;
@@ -83,7 +84,7 @@ namespace X86ISA
 
     class TLB;
 
-    class TLB : public SimObject
+    class TLB : public BaseTLB
     {
       protected:
         friend class FakeITLBFault;
@@ -120,7 +121,7 @@ namespace X86ISA
 
         void invalidateNonGlobal();
 
-        void demapPage(Addr va);
+        void demapPage(Addr va, uint64_t asn);
 
       protected:
         int size;

diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 74b250207c24d88d612d965a2c0658d56b83d5ed..bea680fac86b7887312bf6a3b8f5d4f63a125826 100644 (file)
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -92,6 +92,19 @@ class BaseDynInst : public FastAlloc, public RefCounted
     /** InstRecord that tracks this instructions. */
     Trace::InstRecord *traceData;
 
+    void demapPage(Addr vaddr, uint64_t asn)
+    {
+        cpu->demapPage(vaddr, asn);
+    }
+    void demapInstPage(Addr vaddr, uint64_t asn)
+    {
+        cpu->demapPage(vaddr, asn);
+    }
+    void demapDataPage(Addr vaddr, uint64_t asn)
+    {
+        cpu->demapPage(vaddr, asn);
+    }
+
     /**
      * Does a read to a given address.
      * @param addr The address to read.

diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 7b3628986b1402b83cd9e5553a74badb69a6d7a6..35dc59ff4badc04b7b1ce766ee30542486fdef4d 100644 (file)
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -324,6 +324,22 @@ class CheckerCPU : public BaseCPU
     void recordPCChange(uint64_t val) { changedPC = true; newPC = val; }
     void recordNextPCChange(uint64_t val) { changedNextPC = true; }
 
+    void demapPage(Addr vaddr, uint64_t asn)
+    {
+        this->itb->demapPage(vaddr, asn);
+        this->dtb->demapPage(vaddr, asn);
+    }
+
+    void demapInstPage(Addr vaddr, uint64_t asn)
+    {
+        this->itb->demapPage(vaddr, asn);
+    }
+
+    void demapDataPage(Addr vaddr, uint64_t asn)
+    {
+        this->dtb->demapPage(vaddr, asn);
+    }
+
     bool translateInstReq(Request *req);
     void translateDataWriteReq(Request *req);
     void translateDataReadReq(Request *req);

diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index e902968c1fc9598c259381f5e712bd6b45ef2fde..61d7dcf22f6b4aff7948c67ef5c5ee80a2cca221 100644 (file)
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -263,6 +263,22 @@ class FullO3CPU : public BaseO3CPU
     /** Registers statistics. */
     void fullCPURegStats();
 
+    void demapPage(Addr vaddr, uint64_t asn)
+    {
+        this->itb->demapPage(vaddr, asn);
+        this->dtb->demapPage(vaddr, asn);
+    }
+
+    void demapInstPage(Addr vaddr, uint64_t asn)
+    {
+        this->itb->demapPage(vaddr, asn);
+    }
+
+    void demapDataPage(Addr vaddr, uint64_t asn)
+    {
+        this->dtb->demapPage(vaddr, asn);
+    }
+
     /** Translates instruction requestion. */
     Fault translateInstReq(RequestPtr &req, Thread *thread)
     {

diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index 61abae807af739c3c841ffb0d0da2c80d3c86058..b0ea2cba95c7abf661fe97fa165264e02ab25d70 100644 (file)
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -423,6 +423,22 @@ class OzoneCPU : public BaseCPU
     virtual void serialize(std::ostream &os);
     virtual void unserialize(Checkpoint *cp, const std::string &section);
 
+    void demapPage(Addr vaddr, uint64_t asn)
+    {
+        itb->demap(vaddr, asn);
+        dtb->demap(vaddr, asn);
+    }
+
+    void demapInstPage(Addr vaddr, uint64_t asn)
+    {
+        itb->demap(vaddr, asn);
+    }
+
+    void demapDataPage(Addr vaddr, uint64_t asn)
+    {
+        dtb->demap(vaddr, asn);
+    }
+
 #if FULL_SYSTEM
     /** Translates instruction requestion. */
     Fault translateInstReq(RequestPtr &req, OzoneThreadState<Impl> *thread)

diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 8c162a8460b549d0cf3ea26f6e468ec9588a594b..918965fdba086f05fef5debc975a4532ee522792 100644 (file)
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -367,6 +367,21 @@ class BaseSimpleCPU : public BaseCPU
         return thread->setMiscReg(reg_idx, val);
     }
 
+    void demapPage(Addr vaddr, uint64_t asn)
+    {
+        thread->demapPage(vaddr, asn);
+    }
+
+    void demapInstPage(Addr vaddr, uint64_t asn)
+    {
+        thread->demapInstPage(vaddr, asn);
+    }
+
+    void demapDataPage(Addr vaddr, uint64_t asn)
+    {
+        thread->demapDataPage(vaddr, asn);
+    }
+
     unsigned readStCondFailures() {
         return thread->readStCondFailures();
     }

diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 2b79c97081c5b2d1d5c6f6234a2373eae51cf087..fa80a283a27d6ecd10edad40e551d2b84bc971f0 100644 (file)
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -163,6 +163,22 @@ class SimpleThread : public ThreadState
         return dtb->translate(req, tc, true);
     }
 
+    void demapPage(Addr vaddr, uint64_t asn)
+    {
+        itb->demapPage(vaddr, asn);
+        dtb->demapPage(vaddr, asn);
+    }
+
+    void demapInstPage(Addr vaddr, uint64_t asn)
+    {
+        itb->demapPage(vaddr, asn);
+    }
+
+    void demapDataPage(Addr vaddr, uint64_t asn)
+    {
+        dtb->demapPage(vaddr, asn);
+    }
+
 #if FULL_SYSTEM
     int getInstAsid() { return regs.instAsid(); }
     int getDataAsid() { return regs.dataAsid(); }

diff --git a/src/sim/tlb.cc b/src/sim/tlb.cc
index de677983960c5a9d662040bfedef8f61f7879b44..7292a69e0e9e5d64135df9d3c9e37f522fac8e3b 100644 (file)
--- a/src/sim/tlb.cc
+++ b/src/sim/tlb.cc
@@ -48,3 +48,9 @@ GenericTLB::translate(RequestPtr req, ThreadContext * tc, bool)
         return NoFault;
 #endif
 }
+
+void
+GenericTLB::demapPage(Addr vaddr, uint64_t asn)
+{
+    warn("Demapping pages in the generic TLB is unnecessary.\n");
+}

diff --git a/src/sim/tlb.hh b/src/sim/tlb.hh
index b5e341185436510b225d1cde9dd60fc02d507ea7..011cc114460fd280bb786c65b3d3ff12ea82e319 100644 (file)
--- a/src/sim/tlb.hh
+++ b/src/sim/tlb.hh
@@ -39,13 +39,25 @@
 class ThreadContext;
 class Packet;
 
-class GenericTLB : public SimObject
+class BaseTLB : public SimObject
 {
   protected:
-    GenericTLB(const Params *p) : SimObject(p)
+    BaseTLB(const Params *p) : SimObject(p)
     {}
 
   public:
+    virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
+};
+
+class GenericTLB : public BaseTLB
+{
+  protected:
+    GenericTLB(const Params *p) : BaseTLB(p)
+    {}
+
+  public:
+    void demapPage(Addr vaddr, uint64_t asn);
+
     Fault translate(RequestPtr req, ThreadContext *tc, bool=false);
 };