[AArch64] Add vcond(u?)didi pattern

	* config/aarch64/aarch64-simd.md (aarch64_vcond_internal<mode><mode>,
	vcond<mode><mode>, vcondu<mode><mode>): Add DImode variant.

From-SVN: r222908

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 1d3b0a976c5a5276f1d26b21616d63153425f32e..87a75d1398e31e69ef090de98b2734020adb5582 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2015-05-08  Alan Lawrence  <alan.lawrence@arm.com>
+
+       * config/aarch64/aarch64-simd.md (aarch64_vcond_internal<mode><mode>,
+       vcond<mode><mode>, vcondu<mode><mode>): Add DImode variant.
+
 2015-05-08  Alan Lawrence  <alan.lawrence@arm.com>
 
        * optabs.c (vector_compare_rtx): Handle RTL operands having VOIDmode.

diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 5342c3d20d2a702585cbcd44ee981fa82606d252..b90f93841f8ba505fb362a42646ef374ac18b2ec 100644 (file)
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -2057,13 +2057,13 @@
 })
 
 (define_expand "aarch64_vcond_internal<mode><mode>"
-  [(set (match_operand:VDQ_I 0 "register_operand")
-       (if_then_else:VDQ_I
+  [(set (match_operand:VSDQ_I_DI 0 "register_operand")
+       (if_then_else:VSDQ_I_DI
          (match_operator 3 "comparison_operator"
-           [(match_operand:VDQ_I 4 "register_operand")
-            (match_operand:VDQ_I 5 "nonmemory_operand")])
-         (match_operand:VDQ_I 1 "nonmemory_operand")
-         (match_operand:VDQ_I 2 "nonmemory_operand")))]
+           [(match_operand:VSDQ_I_DI 4 "register_operand")
+            (match_operand:VSDQ_I_DI 5 "nonmemory_operand")])
+         (match_operand:VSDQ_I_DI 1 "nonmemory_operand")
+         (match_operand:VSDQ_I_DI 2 "nonmemory_operand")))]
   "TARGET_SIMD"
 {
   rtx op1 = operands[1];
@@ -2365,13 +2365,13 @@
 })
 
 (define_expand "vcond<mode><mode>"
-  [(set (match_operand:VALL 0 "register_operand")
-       (if_then_else:VALL
+  [(set (match_operand:VALLDI 0 "register_operand")
+       (if_then_else:VALLDI
          (match_operator 3 "comparison_operator"
-           [(match_operand:VALL 4 "register_operand")
-            (match_operand:VALL 5 "nonmemory_operand")])
-         (match_operand:VALL 1 "nonmemory_operand")
-         (match_operand:VALL 2 "nonmemory_operand")))]
+           [(match_operand:VALLDI 4 "register_operand")
+            (match_operand:VALLDI 5 "nonmemory_operand")])
+         (match_operand:VALLDI 1 "nonmemory_operand")
+         (match_operand:VALLDI 2 "nonmemory_operand")))]
   "TARGET_SIMD"
 {
   emit_insn (gen_aarch64_vcond_internal<mode><mode> (operands[0], operands[1],
@@ -2398,13 +2398,13 @@
 })
 
 (define_expand "vcondu<mode><mode>"
-  [(set (match_operand:VDQ_I 0 "register_operand")
-       (if_then_else:VDQ_I
+  [(set (match_operand:VSDQ_I_DI 0 "register_operand")
+       (if_then_else:VSDQ_I_DI
          (match_operator 3 "comparison_operator"
-           [(match_operand:VDQ_I 4 "register_operand")
-            (match_operand:VDQ_I 5 "nonmemory_operand")])
-         (match_operand:VDQ_I 1 "nonmemory_operand")
-         (match_operand:VDQ_I 2 "nonmemory_operand")))]
+           [(match_operand:VSDQ_I_DI 4 "register_operand")
+            (match_operand:VSDQ_I_DI 5 "nonmemory_operand")])
+         (match_operand:VSDQ_I_DI 1 "nonmemory_operand")
+         (match_operand:VSDQ_I_DI 2 "nonmemory_operand")))]
   "TARGET_SIMD"
 {
   emit_insn (gen_aarch64_vcond_internal<mode><mode> (operands[0], operands[1],