targets/EthernetSoC: be sure memory region is added before adding Wishbone Slave...

diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py
index 8bbfa3cd26f2ccc88420a6ea9dd35a9c4658e45e..8b0840e4668d6c6ae97522738b834dfd924d1439 100755 (executable)
--- a/litex/boards/targets/arty.py
+++ b/litex/boards/targets/arty.py
@@ -95,7 +95,7 @@ class EthernetSoC(BaseSoC):
             interface  = "wishbone",
             endianness = self.cpu.endianness)
         self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
-        self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000)
+        self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
         self.add_csr("ethmac")
         self.add_interrupt("ethmac")
         # timing constraints

diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py
index 55cc272acbca25e058f6f285636b7d09f349cc63..583176cda7cbbaafb89d1811a1d151d2fbc48afd 100755 (executable)
--- a/litex/boards/targets/genesys2.py
+++ b/litex/boards/targets/genesys2.py
@@ -88,7 +88,7 @@ class EthernetSoC(BaseSoC):
             interface  = "wishbone",
             endianness = self.cpu.endianness)
         self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
-        self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000)
+        self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
         self.add_csr("ethmac")
         self.add_interrupt("ethmac")
         # timing constraints

diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py
index 70b2f9fb08d51b1d7dfb81b5a89b3fbb9d7f3620..67cdf274c1d335674648b287663b916905155eab 100755 (executable)
--- a/litex/boards/targets/kc705.py
+++ b/litex/boards/targets/kc705.py
@@ -89,7 +89,7 @@ class EthernetSoC(BaseSoC):
             interface  = "wishbone",
             endianness = self.cpu.endianness)
         self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
-        self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000)
+        self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
         self.add_csr("ethmac")
         self.add_interrupt("ethmac")
         # timing constraints

diff --git a/litex/boards/targets/netv2.py b/litex/boards/targets/netv2.py
index 40e20071efa7c411b5d311d58d60c639bd5a8c02..fb6e150fd76073883e2fc0ba35a1159acd3b0789 100755 (executable)
--- a/litex/boards/targets/netv2.py
+++ b/litex/boards/targets/netv2.py
@@ -91,7 +91,7 @@ class EthernetSoC(BaseSoC):
             interface  = "wishbone",
             endianness = self.cpu.endianness)
         self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
-        self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000)
+        self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
         self.add_csr("ethmac")
         self.add_interrupt("ethmac")
         # timing constraints

diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py
index fa78b9d5d951f4667e4fb775025106546456bd9b..79eaa6d0b789d0b3c05c77c47723842d75d6d20b 100755 (executable)
--- a/litex/boards/targets/nexys4ddr.py
+++ b/litex/boards/targets/nexys4ddr.py
@@ -90,7 +90,7 @@ class EthernetSoC(BaseSoC):
             interface  = "wishbone",
             endianness = self.cpu.endianness)
         self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
-        self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000)
+        self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
         self.add_csr("ethmac")
         self.add_interrupt("ethmac")
         # timing constraints

diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py
index 4d261d3c97b180dd9457822e9619afd8073135fa..19df6338bf925f2aac01bc303ed2ed3fb54c1b64 100755 (executable)
--- a/litex/boards/targets/nexys_video.py
+++ b/litex/boards/targets/nexys_video.py
@@ -90,7 +90,7 @@ class EthernetSoC(BaseSoC):
             interface  = "wishbone",
             endianness = self.cpu.endianness)
         self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
-        self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000)
+        self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
         self.add_csr("ethmac")
         self.add_interrupt("ethmac")
         # timing constraints

diff --git a/litex/boards/targets/simple.py b/litex/boards/targets/simple.py
index 904959ed08d8f2742e3e634a3369dab41f957a37..7250c98f2177e8759ae17a3eb29564f0629575df 100755 (executable)
--- a/litex/boards/targets/simple.py
+++ b/litex/boards/targets/simple.py
@@ -49,7 +49,7 @@ class EthernetSoC(BaseSoC):
         self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
             interface="wishbone", endianness=self.cpu.endianness, with_preamble_crc=False)
         self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
-        self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000)
+        self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
         self.add_csr("ethmac")
         self.add_interrupt("ethmac")
 

diff --git a/litex/boards/targets/versa_ecp5.py b/litex/boards/targets/versa_ecp5.py
index 9951b798d4dc6380e6aafe3bbe2468ec2c205d92..2ee57a207e1a55306adfd233b77d0b96baf686e1 100755 (executable)
--- a/litex/boards/targets/versa_ecp5.py
+++ b/litex/boards/targets/versa_ecp5.py
@@ -115,7 +115,7 @@ class EthernetSoC(BaseSoC):
         self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
             interface="wishbone", endianness=self.cpu.endianness)
         self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
-        self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000)
+        self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
         self.add_csr("ethmac")
         self.add_interrupt("ethmac")
         # timing constraints