cores/icap/ICAPBitstream: add source ready signal.

diff --git a/litex/soc/cores/icap.py b/litex/soc/cores/icap.py
index 73319925d18d73e6ea3cbb7a99a0b5137c2f8126..6c312dda4a8f11f2c9f626f565114f9d2ce1a3f4 100644 (file)
--- a/litex/soc/cores/icap.py
+++ b/litex/soc/cores/icap.py
@@ -114,6 +114,7 @@ class ICAPBitstream(Module, AutoCSR):
         self.comb += [
             If(fifo.source.valid,
                 _csib.eq(0),
+                fifo.source.ready.eq(1),
                 _i.eq(fifo.source.data)
             )
         ]