abc9_ops: Also derive blackboxes with timing info

Signed-off-by: gatecat <gatecat@ds0.me>

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 29fe74ec740e013f46e2ae048204df79f004948d..b8975f17835308ef5b577981067ba63f8a7243b9 100644 (file)
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -167,10 +167,6 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
                                derived_module = inst_module;
                        }
                        else {
-                               // Check potential for any one of those three
-                               //   (since its value may depend on a parameter, but not its existence)
-                               if (!inst_module->has_attribute(ID::abc9_flop) && !inst_module->has_attribute(ID::abc9_box) && !inst_module->get_bool_attribute(ID::abc9_bypass))
-                                       continue;
                                derived_type = inst_module->derive(design, cell->parameters);
                                derived_module = design->module(derived_type);
                        }
@@ -180,7 +176,16 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
                                        continue;
                        }
                        else {
-                               if (!derived_module->get_bool_attribute(ID::abc9_box) && !derived_module->get_bool_attribute(ID::abc9_bypass)) {
+                               bool has_timing = false;
+                               for (auto derived_cell : derived_module->cells()) {
+                                       if (derived_cell->type.in(ID($specify2), ID($specify3), ID($specrule))) {
+                                               // If the module contains timing; then we potentially care about deriving its content too,
+                                               // as timings (or associated port widths) could be dependent on parameters.
+                                               has_timing = true;
+                                               break;
+                                       }
+                               }
+                               if (!derived_module->get_bool_attribute(ID::abc9_box) && !derived_module->get_bool_attribute(ID::abc9_bypass) && !has_timing) {
                                        if (unmap_design->module(derived_type)) {
                                                // If derived_type is present in unmap_design, it means that it was processed previously, but found to be incompatible -- e.g. if
                                                // it contained a non-zero initial state. In this case, continue to replace the cell type/parameters so that it has the same properties