i965/hsw: Apply non-msrt fast color clear w/a to all HSW GTs

Pre-patch, the workaround was applied to only HSW GT3. However, the
workaround also fixes render corruption on the HSW GT1 Chromebook,
codenamed Falco.

Also, update the BSpec quote that discusses the workaround to reflect
the latest BSpec.

The BSpec states that the workaround is required for Ivybridge and
Baytrail as well as Haswell. But, we apply the workaround to only
Haswell because (a) we suspect that is the only hardware where it is
actually required and (b) we haven't yet validated the workaround for
the other hardware.

CC: "9.2, 10.0" <mesa-stable@lists.freedesktop.org>
CC: Anuj Phogat <anuj.phogat@gmail.com>
OTC-Tracker: CHRMOS-812
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>

diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
index 02ec2737ac38a12274794d7755682f8e5159f33e..3f096b513fa4af0dda493b6d125173e6cff9c5d5 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
@@ -265,13 +265,19 @@ brw_blorp_clear_params::brw_blorp_clear_params(struct brw_context *brw,
       x_align *= 16;
       y_align *= 32;
 
-      if (brw->is_haswell && brw->gt == 3) {
+      if (brw->is_haswell) {
          /* From BSpec: 3D-Media-GPGPU Engine > 3D Pipeline > Pixel > Pixel
-          * Backend > MCS Buffer for Render Target(s) [DevIVB+]:
-          * [DevHSW:GT3]: Clear rectangle must be aligned to two times the
-          * number of pixels in the table shown below...
-          * x_align, y_align values computed above are the relevant entries
-          * in the referred table.
+          * Backend > MCS Buffer for Render Target(s) [DevIVB+] > Table "Color
+          * Clear of Non-MultiSampled Render Target Restrictions":
+          *
+          *   [IVB, VLVT, HSW]: Clear rectangle must be aligned to two times
+          *   the number of pixels in the table shown below...  x_align,
+          *   y_align values computed above are the relevant entries in the
+          *   referred table.
+          *
+          * We apply the workaround to only Haswell because (a) we suspect that
+          * is the only hardware where it is actually required and (b) we
+          * haven't yet validated the workaround for the other hardware.
           */
          x0 = ROUND_DOWN_TO(x0, 2 * x_align);
          y0 = ROUND_DOWN_TO(y0, 2 * y_align);