Detect illegal port declaration, e.g input/output/inout keyword must be the first.

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index e803d8072e293082071913fafb42da190d570fd2..72a501d110699c234c4a258cbcc29e7320e5119b 100644 (file)
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -376,9 +376,10 @@ wire_type:
        };
 
 wire_type_token_list:
-       wire_type_token | wire_type_token_list wire_type_token;
+       wire_type_token | wire_type_token_list wire_type_token |
+       wire_type_token_io ;
 
-wire_type_token:
+wire_type_token_io:
        TOK_INPUT {
                astbuf3->is_input = true;
        } |
@@ -388,7 +389,9 @@ wire_type_token:
        TOK_INOUT {
                astbuf3->is_input = true;
                astbuf3->is_output = true;
-       } |
+       };
+
+wire_type_token:
        TOK_WIRE {
        } |
        TOK_REG {