arm: Don't speculatively access most miscregisters.

Speculative exeuction can cause panics in detailed execution mode that
shouldn't happen.

diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index 5403ddc8d64d9d082fd0b2b17cc67b8ec8d74b5b..6ecaa78de7f9a4d75bc2d4ea46c771a47a5db3f5 100644 (file)
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -219,7 +219,7 @@ let {{
     msrBankedRegIop = InstObjParams("msr", "MsrBankedReg", "MsrRegOp",
                                     { "code": msrBankedRegCode,
                                       "predicate_test": predicateTest },
-                                    ["IsSerializeAfter"])
+                                    ["IsSerializeAfter", "IsNonSpeculative"])
     header_output += MsrBankedRegDeclare.subst(msrBankedRegIop)
     decoder_output += MsrBankedRegConstructor.subst(msrBankedRegIop)
     exec_output += PredOpExecute.subst(msrBankedRegIop)

diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index d682dc45455f15ecd6910fd2cf515a21e429a993..c54e7d07b6759ae8f1be0cd165d1e84705a4846d 100644 (file)
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -758,7 +758,7 @@ bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS] = {
     // MISCREG_CNTP_CVAL
     bitset<NUM_MISCREG_INFOS>(string("0000000000000001001")),
     // MISCREG_CNTP_CVAL_NS
-    bitset<NUM_MISCREG_INFOS>(string("1100110011111110000")),
+    bitset<NUM_MISCREG_INFOS>(string("1100110011111110001")),
     // MISCREG_CNTP_CVAL_S
     bitset<NUM_MISCREG_INFOS>(string("0011001100111110000")),
     // MISCREG_CNTV_CVAL