Unpacked array declaration using size
authorTobias Wölfel <tobias.woelfel@mailbox.org>
Wed, 19 Jun 2019 10:47:48 +0000 (12:47 +0200)
committerTobias Wölfel <tobias.woelfel@mailbox.org>
Wed, 19 Jun 2019 10:47:48 +0000 (12:47 +0200)
Allows fixed-sized array dimension specified by a single number.

This commit is based on the work from PeterCrozier
https://github.com/YosysHQ/yosys/pull/560.
But is split out of the original work.

frontends/verilog/verilog_parser.y
tests/various/unpacked_arrays.sv [new file with mode: 0644]
tests/various/unpacked_arrays.ys [new file with mode: 0644]

index a034f960155ca59728729150c59dae164650584b..f77321f09e349f60ba95365ac962859d82b0b8c4 100644 (file)
@@ -1385,7 +1385,13 @@ wire_name:
                                node->children.push_back(rng);
                        }
                        node->type = AST_MEMORY;
-                       node->children.push_back($2);
+                       auto *rangeNode = $2;
+                       if (rangeNode->type == AST_RANGE && rangeNode->children.size() == 1) {
+                               // SV array size [n], rewrite as [n-1:0]
+                               rangeNode->children[0] = new AstNode(AST_SUB, rangeNode->children[0], AstNode::mkconst_int(1, true));
+                               rangeNode->children.push_back(AstNode::mkconst_int(0, false));
+                       }
+                       node->children.push_back(rangeNode);
                }
                if (current_function_or_task == NULL) {
                        if (do_not_require_port_stubs && (node->is_input || node->is_output) && port_stubs.count(*$1) == 0) {
diff --git a/tests/various/unpacked_arrays.sv b/tests/various/unpacked_arrays.sv
new file mode 100644 (file)
index 0000000..2f4ed0d
--- /dev/null
@@ -0,0 +1,4 @@
+module unpacked_arrays;
+  reg array_range [0:7];
+  reg array_size [8];
+endmodule
diff --git a/tests/various/unpacked_arrays.ys b/tests/various/unpacked_arrays.ys
new file mode 100644 (file)
index 0000000..419152d
--- /dev/null
@@ -0,0 +1,2 @@
+read_verilog -sv unpacked_arrays.sv
+stat