bool eventually_property(Net *&net, SigBit &trig)
{
+ Instance *inst = net_to_ast_driver(net);
+
+ if (inst == nullptr)
+ return false;
+
if (clocking.cond_net != nullptr)
trig = importer->net_map_at(clocking.cond_net);
else
trig = State::S1;
- Instance *inst = net_to_ast_driver(net);
-
if (inst->Type() == PRIM_SVA_S_EVENTUALLY || inst->Type() == PRIM_SVA_EVENTUALLY)
{
if (mode_cover || mode_trigger)
int node;
- log_dump(trig);
SvaFsm antecedent_fsm(clocking, trig);
node = parse_sequence(antecedent_fsm, antecedent_fsm.createStartNode(), antecedent_net);
if (inst->Type() == PRIM_SVA_NON_OVERLAPPED_IMPLICATION) {
if (verific_verbose) {
log(" Eventually Antecedent FSM:\n");
antecedent_fsm.dump();
- log_dump(trig);
}
return true;
SigBit sig_a, sig_en = trig;
parse_property(net, &sig_a, nullptr);
- log_dump(trig, sig_a, sig_en);
-
// add final FF stage
SigBit sig_a_q, sig_en_q;