radeonsi: fix DRM version checks for amdgpu DRM 3.0.0

diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c b/src/gallium/drivers/radeon/r600_buffer_common.c
index 0f788b7e23c912e6faa0706bc2ab8a801fdc589e..cb9809f2449ebc23d3a82ed2a9ab1c726278f40c 100644 (file)
--- a/src/gallium/drivers/radeon/r600_buffer_common.c
+++ b/src/gallium/drivers/radeon/r600_buffer_common.c
@@ -121,7 +121,8 @@ bool r600_init_resource(struct r600_common_screen *rscreen,
                /* Older kernels didn't always flush the HDP cache before
                 * CS execution
                 */
-               if (rscreen->info.drm_minor < 40) {
+               if (rscreen->info.drm_major == 2 &&
+                   rscreen->info.drm_minor < 40) {
                        res->domains = RADEON_DOMAIN_GTT;
                        flags |= RADEON_FLAG_GTT_WC;
                        break;
@@ -147,7 +148,8 @@ bool r600_init_resource(struct r600_common_screen *rscreen,
                 * Write-combined CPU mappings are fine, the kernel ensures all CPU
                 * writes finish before the GPU executes a command stream.
                 */
-               if (rscreen->info.drm_minor < 40)
+               if (rscreen->info.drm_major == 2 &&
+                   rscreen->info.drm_minor < 40)
                        res->domains = RADEON_DOMAIN_GTT;
                else if (res->domains & RADEON_DOMAIN_VRAM)
                        flags |= RADEON_FLAG_CPU_ACCESS;

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c b/src/gallium/drivers/radeon/r600_pipe_common.c
index 9e68e5f80ac3ec0812438e3a3459e73645f5a2c6..51c72cc882f60ef44d3f40472b3d8e0cadcb68d2 100644 (file)
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -928,7 +928,9 @@ bool r600_common_screen_init(struct r600_common_screen *rscreen,
        pipe_mutex_init(rscreen->aux_context_lock);
        pipe_mutex_init(rscreen->gpu_load_mutex);
 
-       if (rscreen->info.drm_minor >= 28 && (rscreen->debug_flags & DBG_TRACE_CS)) {
+       if (((rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 28) ||
+            rscreen->info.drm_major == 3) &&
+           (rscreen->debug_flags & DBG_TRACE_CS)) {
                rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->b,
                                                                                PIPE_BIND_CUSTOM,
                                                                                PIPE_USAGE_STAGING,

diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index a4c7034cb37c0e8410c9fe8043bc37d1a8e4a5ef..54696910e43bf676be68a0f2728963b807a3e592 100644 (file)
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -490,7 +490,7 @@ static unsigned r600_texture_get_htile_size(struct r600_common_screen *rscreen,
        unsigned num_pipes = rscreen->tiling_info.num_channels;
 
        if (rscreen->chip_class <= EVERGREEN &&
-           rscreen->info.drm_minor < 26)
+           rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 26)
                return 0;
 
        /* HW bug on R6xx. */
@@ -502,7 +502,7 @@ static unsigned r600_texture_get_htile_size(struct r600_common_screen *rscreen,
        /* HTILE is broken with 1D tiling on old kernels and CIK. */
        if (rscreen->chip_class >= CIK &&
            rtex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
-           rscreen->info.drm_minor < 38)
+           rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 38)
                return 0;
 
        switch (num_pipes) {
@@ -1261,7 +1261,9 @@ void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
 
                /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
                if (tex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
-                   rctx->chip_class >= CIK && rctx->screen->info.drm_minor < 38) {
+                   rctx->chip_class >= CIK &&
+                   rctx->screen->info.drm_major == 2 &&
+                   rctx->screen->info.drm_minor < 38) {
                        continue;
                }
 

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index 22efc6837eb4547867068f50551151d43458eadf..9b5cdd8dc12bf1d9205d4783889688f9b1c33d4d 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -271,7 +271,9 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
        case PIPE_CAP_TEXTURE_MULTISAMPLE:
                /* 2D tiling on CIK is supported since DRM 2.35.0 */
                return sscreen->b.chip_class < CIK ||
-                      sscreen->b.info.drm_minor >= 35;
+                      (sscreen->b.info.drm_major == 2 &&
+                       sscreen->b.info.drm_minor >= 35) ||
+                      sscreen->b.info.drm_major == 3;
 
         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
                 return R600_MAP_BUFFER_ALIGNMENT;

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index b9f512d17b60c591f2b0c04da0d38d1f549445d1..227d975e3805561d0e77eef9bd5d4e51c9486253 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1178,7 +1178,9 @@ static uint32_t si_translate_texformat(struct pipe_screen *screen,
                                       int first_non_void)
 {
        struct si_screen *sscreen = (struct si_screen*)screen;
-       bool enable_compressed_formats = sscreen->b.info.drm_minor >= 31;
+       bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
+                                         sscreen->b.info.drm_minor >= 31) ||
+                                        sscreen->b.info.drm_major == 3;
        boolean uniform = TRUE;
        int i;
 
@@ -1626,7 +1628,6 @@ boolean si_is_format_supported(struct pipe_screen *screen,
                                unsigned sample_count,
                                unsigned usage)
 {
-       struct si_screen *sscreen = (struct si_screen *)screen;
        unsigned retval = 0;
 
        if (target >= PIPE_MAX_TEXTURE_TYPES) {
@@ -1638,8 +1639,7 @@ boolean si_is_format_supported(struct pipe_screen *screen,
                return FALSE;
 
        if (sample_count > 1) {
-               /* 2D tiling on CIK is supported since DRM 2.35.0 */
-               if (sscreen->b.chip_class >= CIK && sscreen->b.info.drm_minor < 35)
+               if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
                        return FALSE;
 
                switch (sample_count) {