RISC-V: Support aliases for Zbs instructions

Add aliases for the non-immediate mnemonics of b{set,clr,inv,ext} to
yencode the respective immediate insn b{set,clr,inv,ext}i when the
second source operand is an immediate.

2021-01-11  Philipp Tomsich  <philipp.tomsich@vrull.eu>

    gas/
	* testsuite/gas/riscv/b-ext.d: Add tests.
	* testsuite/gas/riscv/b-ext.s: Likewise.
	* testsuite/gas/riscv/b-ext-64.d: Likewise.
	* testsuite/gas/riscv/b-ext-64.s: Likewise.
    opcodes/
        * riscv-opc.c (riscv_opcodes): Add aliases for Zbs.

Suggested-by: Jan Beulich <jbeulich@suse.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>

diff --git a/gas/testsuite/gas/riscv/b-ext-64.d b/gas/testsuite/gas/riscv/b-ext-64.d
index 339fa20a36757526339de62bcea4fe49c32bc276..9b6e6b7ab2a0585af6b038076398d726798cf6ec 100644 (file)
--- a/gas/testsuite/gas/riscv/b-ext-64.d
+++ b/gas/testsuite/gas/riscv/b-ext-64.d
@@ -62,3 +62,11 @@ Disassembly of section .text:
 [      ]+[0-9a-f]+:[   ]+28c59533[     ]+bset[         ]+a0,a1,a2
 [      ]+[0-9a-f]+:[   ]+68c59533[     ]+binv[         ]+a0,a1,a2
 [      ]+[0-9a-f]+:[   ]+48c5d533[     ]+bext[         ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+49f59513[     ]+bclri[        ]+a0,a1,0x1f
+[      ]+[0-9a-f]+:[   ]+29f59513[     ]+bseti[        ]+a0,a1,0x1f
+[      ]+[0-9a-f]+:[   ]+69f59513[     ]+binvi[        ]+a0,a1,0x1f
+[      ]+[0-9a-f]+:[   ]+49f5d513[     ]+bexti[        ]+a0,a1,0x1f
+[      ]+[0-9a-f]+:[   ]+4bf59513[     ]+bclri[        ]+a0,a1,0x3f
+[      ]+[0-9a-f]+:[   ]+2bf59513[     ]+bseti[        ]+a0,a1,0x3f
+[      ]+[0-9a-f]+:[   ]+6bf59513[     ]+binvi[        ]+a0,a1,0x3f
+[      ]+[0-9a-f]+:[   ]+4bf5d513[     ]+bexti[        ]+a0,a1,0x3f

diff --git a/gas/testsuite/gas/riscv/b-ext-64.s b/gas/testsuite/gas/riscv/b-ext-64.s
index 8ceb2b4fd1ccd5f0ec8e91781bd7c539d23f33e3..57e501e9a41ff95e85c1bf2c3527985007d7634f 100644 (file)
--- a/gas/testsuite/gas/riscv/b-ext-64.s
+++ b/gas/testsuite/gas/riscv/b-ext-64.s
@@ -53,3 +53,12 @@ target:
        bset    a0, a1, a2
        binv    a0, a1, a2
        bext    a0, a1, a2
+       #aliases
+       bclr    a0, a1, 31
+       bset    a0, a1, 31
+       binv    a0, a1, 31
+       bext    a0, a1, 31
+       bclr    a0, a1, 63
+       bset    a0, a1, 63
+       binv    a0, a1, 63
+       bext    a0, a1, 63

diff --git a/gas/testsuite/gas/riscv/b-ext.d b/gas/testsuite/gas/riscv/b-ext.d
index 748c218fdd055bbbedcdd38b902ecfd55ddfcb34..c1c5f918a841993292cdf9793025b1e0ff74dcf1 100644 (file)
--- a/gas/testsuite/gas/riscv/b-ext.d
+++ b/gas/testsuite/gas/riscv/b-ext.d
@@ -45,3 +45,7 @@ Disassembly of section .text:
 [      ]+[0-9a-f]+:[   ]+28c59533[     ]+bset[         ]+a0,a1,a2
 [      ]+[0-9a-f]+:[   ]+68c59533[     ]+binv[         ]+a0,a1,a2
 [      ]+[0-9a-f]+:[   ]+48c5d533[     ]+bext[         ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+49f59513[     ]+bclri[        ]+a0,a1,0x1f
+[      ]+[0-9a-f]+:[   ]+29f59513[     ]+bseti[        ]+a0,a1,0x1f
+[      ]+[0-9a-f]+:[   ]+69f59513[     ]+binvi[        ]+a0,a1,0x1f
+[      ]+[0-9a-f]+:[   ]+49f5d513[     ]+bexti[        ]+a0,a1,0x1f

diff --git a/gas/testsuite/gas/riscv/b-ext.s b/gas/testsuite/gas/riscv/b-ext.s
index a13a797f0dce9d1e10b82473ee12b14659414caf..9de3fc328064265e0435da17e5f27e0afb6b9b4a 100644 (file)
--- a/gas/testsuite/gas/riscv/b-ext.s
+++ b/gas/testsuite/gas/riscv/b-ext.s
@@ -36,3 +36,8 @@ target:
        bset    a0, a1, a2
        binv    a0, a1, a2
        bext    a0, a1, a2
+       #aliases
+       bclr    a0, a1, 31
+       bset    a0, a1, 31
+       binv    a0, a1, 31
+       bext    a0, a1, 31

diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 1a4c9f0e4fecfeeefd9dec95fca2b0e77a04b944..b756bae64ab8687467604287c2c7a41e8df39b2c 100644 (file)
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -839,9 +839,13 @@ const struct riscv_opcode riscv_opcodes[] =
 {"binvi",     0, INSN_CLASS_ZBS,   "d,s,>",  MATCH_BINVI, MASK_BINVI, match_opcode, 0 },
 {"bexti",     0, INSN_CLASS_ZBS,   "d,s,>",  MATCH_BEXTI, MASK_BEXTI, match_opcode, 0 },
 {"bclr",      0, INSN_CLASS_ZBS,   "d,s,t",  MATCH_BCLR, MASK_BCLR, match_opcode, 0 },
+{"bclr",      0, INSN_CLASS_ZBS,   "d,s,>",  MATCH_BCLRI, MASK_BCLRI, match_opcode, INSN_ALIAS },
 {"bset",      0, INSN_CLASS_ZBS,   "d,s,t",  MATCH_BSET, MASK_BSET, match_opcode, 0 },
+{"bset",      0, INSN_CLASS_ZBS,   "d,s,>",  MATCH_BSETI, MASK_BSETI, match_opcode, INSN_ALIAS },
 {"binv",      0, INSN_CLASS_ZBS,   "d,s,t",  MATCH_BINV, MASK_BINV, match_opcode, 0 },
+{"binv",      0, INSN_CLASS_ZBS,   "d,s,>",  MATCH_BINVI, MASK_BINVI, match_opcode, INSN_ALIAS },
 {"bext",      0, INSN_CLASS_ZBS,   "d,s,t",  MATCH_BEXT, MASK_BEXT, match_opcode, 0 },
+{"bext",      0, INSN_CLASS_ZBS,   "d,s,>",  MATCH_BEXTI, MASK_BEXTI, match_opcode, INSN_ALIAS },
 
 /* Terminate the list.  */
 {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}