* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-/* @file
- * System Console Definition
+/** @file
+ * Alpha Console Definition
*/
#include <cstddef>
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-/* @file
+/** @file
* System Console Interface
*/
class System;
class SimpleDisk;
-/*
+/**
* Memory mapped interface to the system console. This device
* represents a shared data region between the OS Kernel and the
* System Console.
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-/* @file
+/** @file
* BadDevice implemenation
*/
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-/* @file
+/** @file
* This devices just panics when touched. For example if you have a
* kernel that touches the frame buffer which isn't allowed.
*/
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-/* @file
+/** @file
* Disk Image Definitions
*/
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-/* @file
+/** @file
* Disk Image Interfaces
*/
#define SectorSize (512)
-/*
+/**
* Basic interface for accessing a disk image.
*/
class DiskImage : public SimObject
virtual off_t write(const uint8_t *data, off_t offset) = 0;
};
-/*
+/**
* Specialization for accessing a raw disk image
*/
class RawDiskImage : public DiskImage
virtual off_t write(const uint8_t *data, off_t offset);
};
-/*
+/**
* Specialization for accessing a copy-on-write disk image layer.
* A copy-on-write(COW) layer must be stacked on top of another disk
* image layer this layer can be another CowDiskImage, or a
--- /dev/null
+/* $OpenBSD: atareg.h,v 1.12 2004/09/24 07:15:22 grange Exp $ */
+/* $NetBSD: atareg.h,v 1.5 1999/01/18 20:06:24 bouyer Exp $ */
+
+/*
+ * Copyright (c) 1998, 2001 Manuel Bouyer.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Manuel Bouyer.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _DEV_ATA_ATAREG_H_
+#define _DEV_ATA_ATAREG_H_
+
+#define ATA_BYTE_ORDER LITTLE_ENDIAN
+/*
+ * Drive parameter structure for ATA/ATAPI.
+ * Bit fields: WDC_* : common to ATA/ATAPI
+ * ATA_* : ATA only
+ * ATAPI_* : ATAPI only.
+ */
+struct ataparams {
+ /* drive info */
+ uint16_t atap_config; /* 0: general configuration */
+#define WDC_CFG_ATAPI_MASK 0xc000
+#define WDC_CFG_ATAPI 0x8000
+#define ATA_CFG_REMOVABLE 0x0080
+#define ATA_CFG_FIXED 0x0040
+#define ATAPI_CFG_TYPE_MASK 0x1f00
+#define ATAPI_CFG_TYPE(x) (((x) & ATAPI_CFG_TYPE_MASK) >> 8)
+#define ATAPI_CFG_TYPE_DIRECT 0x00
+#define ATAPI_CFG_TYPE_SEQUENTIAL 0x01
+#define ATAPI_CFG_TYPE_CDROM 0x05
+#define ATAPI_CFG_TYPE_OPTICAL 0x07
+#define ATAPI_CFG_TYPE_NODEVICE 0x1F
+#define ATAPI_CFG_REMOV 0x0080
+#define ATAPI_CFG_DRQ_MASK 0x0060
+#define ATAPI_CFG_STD_DRQ 0x0000
+#define ATAPI_CFG_IRQ_DRQ 0x0020
+#define ATAPI_CFG_ACCEL_DRQ 0x0040
+#define ATAPI_CFG_CMD_MASK 0x0003
+#define ATAPI_CFG_CMD_12 0x0000
+#define ATAPI_CFG_CMD_16 0x0001
+/* words 1-9 are ATA only */
+ uint16_t atap_cylinders; /* 1: # of non-removable cylinders */
+ uint16_t __reserved1;
+ uint16_t atap_heads; /* 3: # of heads */
+ uint16_t __retired1[2]; /* 4-5: # of unform. bytes/track */
+ uint16_t atap_sectors; /* 6: # of sectors */
+ uint16_t __retired2[3];
+
+ uint8_t atap_serial[20]; /* 10-19: serial number */
+ uint16_t __retired3[2];
+ uint16_t __obsolete1;
+ uint8_t atap_revision[8]; /* 23-26: firmware revision */
+ uint8_t atap_model[40]; /* 27-46: model number */
+ uint16_t atap_multi; /* 47: maximum sectors per irq (ATA) */
+ uint16_t __reserved2;
+ uint8_t atap_vendor; /* 49: vendor */
+ uint8_t atap_capabilities1; /* 49: capability flags */
+#define WDC_CAP_IORDY 0x0800
+#define WDC_CAP_IORDY_DSBL 0x0400
+#define WDC_CAP_LBA 0x0200
+#define WDC_CAP_DMA 0x0100
+#define ATA_CAP_STBY 0x2000
+#define ATAPI_CAP_INTERL_DMA 0x8000
+#define ATAPI_CAP_CMD_QUEUE 0x4000
+#define ATAPI_CAP_OVERLP 0x2000
+#define ATAPI_CAP_ATA_RST 0x1000
+ uint16_t atap_capabilities2; /* 50: capability flags (ATA) */
+#if ATA_BYTE_ORDER == LITTLE_ENDIAN
+ uint8_t __junk2;
+ uint8_t atap_oldpiotiming; /* 51: old PIO timing mode */
+ uint8_t __junk3;
+ uint8_t atap_olddmatiming; /* 52: old DMA timing mode (ATA) */
+#else
+ uint8_t atap_oldpiotiming; /* 51: old PIO timing mode */
+ uint8_t __junk2;
+ uint8_t atap_olddmatiming; /* 52: old DMA timing mode (ATA) */
+ uint8_t __junk3;
+#endif
+ uint16_t atap_extensions; /* 53: extensions supported */
+#define WDC_EXT_UDMA_MODES 0x0004
+#define WDC_EXT_MODES 0x0002
+#define WDC_EXT_GEOM 0x0001
+/* words 54-62 are ATA only */
+ uint16_t atap_curcylinders; /* 54: current logical cylinders */
+ uint16_t atap_curheads; /* 55: current logical heads */
+ uint16_t atap_cursectors; /* 56: current logical sectors/tracks */
+ uint16_t atap_curcapacity[2]; /* 57-58: current capacity */
+ uint8_t atap_curmulti; /* 59: current multi-sector setting */
+ uint8_t atap_curmulti_valid; /* 59: current multi-sector setting */
+#define WDC_MULTI_VALID 0x0100
+#define WDC_MULTI_MASK 0x00ff
+ uint32_t atap_capacity; /* 60-61: total capacity (LBA only) */
+ uint16_t __retired4;
+#if ATA_BYTE_ORDER == LITTLE_ENDIAN
+ uint8_t atap_dmamode_supp; /* 63: multiword DMA mode supported */
+ uint8_t atap_dmamode_act; /* multiword DMA mode active */
+ uint8_t atap_piomode_supp; /* 64: PIO mode supported */
+ uint8_t __junk4;
+#else
+ uint8_t atap_dmamode_act; /* multiword DMA mode active */
+ uint8_t atap_dmamode_supp; /* 63: multiword DMA mode supported */
+ uint8_t __junk4;
+ uint8_t atap_piomode_supp; /* 64: PIO mode supported */
+#endif
+ uint16_t atap_dmatiming_mimi; /* 65: minimum DMA cycle time */
+ uint16_t atap_dmatiming_recom; /* 66: recommended DMA cycle time */
+ uint16_t atap_piotiming; /* 67: mini PIO cycle time without FC */
+ uint16_t atap_piotiming_iordy; /* 68: mini PIO cycle time with IORDY FC */
+ uint16_t __reserved3[2];
+/* words 71-72 are ATAPI only */
+ uint16_t atap_pkt_br; /* 71: time (ns) to bus release */
+ uint16_t atap_pkt_bsyclr; /* 72: tme to clear BSY after service */
+ uint16_t __reserved4[2];
+ uint16_t atap_queuedepth; /* 75: */
+#define WDC_QUEUE_DEPTH_MASK 0x1f
+ uint16_t atap_sata_caps; /* 76: SATA capabilities */
+#define SATA_SIGNAL_GEN1 0x0002 /* SATA Gen-1 signaling speed */
+#define SATA_SIGNAL_GEN2 0x0004 /* SATA Gen-2 signaling speed */
+#define SATA_NATIVE_CMDQ 0x0100 /* native command queuing */
+#define SATA_HOST_PWR_MGMT 0x0200 /* power management (host) */
+ uint16_t atap_sata_reserved; /* 77: reserved */
+ uint16_t atap_sata_features_supp;/* 78: SATA features supported */
+#define SATA_NONZERO_OFFSETS 0x0002 /* non-zero buffer offsets */
+#define SATA_DMA_SETUP_AUTO 0x0004 /* DMA setup auto-activate */
+#define SATA_DRIVE_PWR_MGMT 0x0008 /* power management (device) */
+ uint16_t atap_sata_features_en; /* 79: SATA features enabled */
+ uint16_t atap_ata_major; /* 80: Major version number */
+#define WDC_VER_ATA1 0x0002
+#define WDC_VER_ATA2 0x0004
+#define WDC_VER_ATA3 0x0008
+#define WDC_VER_ATA4 0x0010
+#define WDC_VER_ATA5 0x0020
+#define WDC_VER_ATA6 0x0040
+#define WDC_VER_ATA7 0x0080
+#define WDC_VER_ATA8 0x0100
+#define WDC_VER_ATA9 0x0200
+#define WDC_VER_ATA10 0x0400
+#define WDC_VER_ATA11 0x0800
+#define WDC_VER_ATA12 0x1000
+#define WDC_VER_ATA13 0x2000
+#define WDC_VER_ATA14 0x4000
+ uint16_t atap_ata_minor; /* 81: Minor version number */
+ uint16_t atap_cmd_set1; /* 82: command set supported */
+#define WDC_CMD1_NOP 0x4000
+#define WDC_CMD1_RB 0x2000
+#define WDC_CMD1_WB 0x1000
+#define WDC_CMD1_HPA 0x0400
+#define WDC_CMD1_DVRST 0x0200
+#define WDC_CMD1_SRV 0x0100
+#define WDC_CMD1_RLSE 0x0080
+#define WDC_CMD1_AHEAD 0x0040
+#define WDC_CMD1_CACHE 0x0020
+#define WDC_CMD1_PKT 0x0010
+#define WDC_CMD1_PM 0x0008
+#define WDC_CMD1_REMOV 0x0004
+#define WDC_CMD1_SEC 0x0002
+#define WDC_CMD1_SMART 0x0001
+ uint16_t atap_cmd_set2; /* 83: command set supported */
+#define ATAPI_CMD2_FCE 0x2000 /* Flush Cache Ext supported */
+#define ATAPI_CMD2_FC 0x1000 /* Flush Cache supported */
+#define ATAPI_CMD2_DCO 0x0800 /* Device Configuration Overlay supported */
+#define ATAPI_CMD2_48AD 0x0400 /* 48bit address supported */
+#define ATAPI_CMD2_AAM 0x0200 /* Automatic Acoustic Management supported */
+#define ATAPI_CMD2_SM 0x0100 /* Set Max security extension supported */
+#define ATAPI_CMD2_SF 0x0040 /* Set Features subcommand required */
+#define ATAPI_CMD2_PUIS 0x0020 /* Power up in standby supported */
+#define WDC_CMD2_RMSN 0x0010
+#define ATA_CMD2_APM 0x0008
+#define ATA_CMD2_CFA 0x0004
+#define ATA_CMD2_RWQ 0x0002
+#define WDC_CMD2_DM 0x0001 /* Download Microcode supported */
+ uint16_t atap_cmd_ext; /* 84: command/features supp. ext. */
+#define ATAPI_CMDE_MSER 0x0004 /* Media serial number supported */
+#define ATAPI_CMDE_TEST 0x0002 /* SMART self-test supported */
+#define ATAPI_CMDE_SLOG 0x0001 /* SMART error logging supported */
+ uint16_t atap_cmd1_en; /* 85: cmd/features enabled */
+/* bits are the same as atap_cmd_set1 */
+ uint16_t atap_cmd2_en; /* 86: cmd/features enabled */
+/* bits are the same as atap_cmd_set2 */
+ uint16_t atap_cmd_def; /* 87: cmd/features default */
+/* bits are NOT the same as atap_cmd_ext */
+#if ATA_BYTE_ORDER == LITTLE_ENDIAN
+ uint8_t atap_udmamode_supp; /* 88: Ultra-DMA mode supported */
+ uint8_t atap_udmamode_act; /* Ultra-DMA mode active */
+#else
+ uint8_t atap_udmamode_act; /* Ultra-DMA mode active */
+ uint8_t atap_udmamode_supp; /* 88: Ultra-DMA mode supported */
+#endif
+/* 89-92 are ATA-only */
+ uint16_t atap_seu_time; /* 89: Sec. Erase Unit compl. time */
+ uint16_t atap_eseu_time; /* 90: Enhanced SEU compl. time */
+ uint16_t atap_apm_val; /* 91: current APM value */
+ uint16_t atap_mpasswd_rev; /* 92: Master Password revision */
+ uint16_t atap_hwreset_res; /* 93: Hardware reset value */
+#define ATA_HWRES_CBLID 0x2000 /* CBLID above Vih */
+#define ATA_HWRES_D1_PDIAG 0x0800 /* Device 1 PDIAG detect OK */
+#define ATA_HWRES_D1_CSEL 0x0400 /* Device 1 used CSEL for address */
+#define ATA_HWRES_D1_JUMP 0x0200 /* Device 1 jumpered to address */
+#define ATA_HWRES_D0_SEL 0x0040 /* Device 0 responds when Dev 1 selected */
+#define ATA_HWRES_D0_DASP 0x0020 /* Device 0 DASP detect OK */
+#define ATA_HWRES_D0_PDIAG 0x0010 /* Device 0 PDIAG detect OK */
+#define ATA_HWRES_D0_DIAG 0x0008 /* Device 0 diag OK */
+#define ATA_HWRES_D0_CSEL 0x0004 /* Device 0 used CSEL for address */
+#define ATA_HWRES_D0_JUMP 0x0002 /* Device 0 jumpered to address */
+#if ATA_BYTE_ORDER == LITTLE_ENDIAN
+ uint8_t atap_acoustic_val; /* 94: Current acoustic level */
+ uint8_t atap_acoustic_def; /* recommended level */
+#else
+ uint8_t atap_acoustic_def; /* recommended level */
+ uint8_t atap_acoustic_val; /* 94: Current acoustic level */
+#endif
+ uint16_t __reserved6[5]; /* 95-99: reserved */
+ uint16_t atap_max_lba[4]; /* 100-103: Max. user LBA add */
+ uint16_t __reserved7[23]; /* 104-126: reserved */
+ uint16_t atap_rmsn_supp; /* 127: remov. media status notif. */
+#define WDC_RMSN_SUPP_MASK 0x0003
+#define WDC_RMSN_SUPP 0x0001
+ uint16_t atap_sec_st; /* 128: security status */
+#define WDC_SEC_LEV_MAX 0x0100
+#define WDC_SEC_ESE_SUPP 0x0020
+#define WDC_SEC_EXP 0x0010
+#define WDC_SEC_FROZEN 0x0008
+#define WDC_SEC_LOCKED 0x0004
+#define WDC_SEC_EN 0x0002
+#define WDC_SEC_SUPP 0x0001
+ uint16_t __reserved8[31]; /* 129-159: vendor specific */
+ uint16_t atap_cfa_power; /* 160: CFA powermode */
+#define ATAPI_CFA_MAX_MASK 0x0FFF
+#define ATAPI_CFA_MODE1_DIS 0x1000 /* CFA Mode 1 Disabled */
+#define ATAPI_CFA_MODE1_REQ 0x2000 /* CFA Mode 1 Required */
+#define ATAPI_CFA_WORD160 0x8000 /* Word 160 supported */
+ uint16_t __reserved9[15]; /* 161-175: reserved for CFA */
+ uint8_t atap_media_serial[60]; /* 176-205: media serial number */
+ uint16_t __reserved10[49]; /* 206-254: reserved */
+#if ATA_BYTE_ORDER == LITTLE_ENDIAN
+ uint8_t atap_signature; /* 255: Signature */
+ uint8_t atap_checksum; /* Checksum */
+#else
+ uint8_t atap_checksum; /* Checksum */
+ uint8_t atap_signature; /* 255: Signature */
+#endif
+};
+
+#undef ATA_BYTE_ORDER
+#endif /* !_DEV_ATA_ATAREG_H_ */
reset(id);
// fill out the drive ID structure
- memset(&driveID, 0, sizeof(struct hd_driveid));
+ memset(&driveID, 0, sizeof(struct ataparams));
// Calculate LBA and C/H/S values
uint16_t cylinders;
}
// Setup the model name
- sprintf((char *)driveID.model, "5MI EDD si k");
+ sprintf((char *)driveID.atap_model, "5MI EDD si k");
// Set the maximum multisector transfer size
- driveID.max_multsect = MAX_MULTSECT;
+ driveID.atap_multi = MAX_MULTSECT;
// IORDY supported, IORDY disabled, LBA enabled, DMA enabled
- driveID.capability = 0x7;
+ driveID.atap_capabilities1 = 0x7;
// UDMA support, EIDE support
- driveID.field_valid = 0x6;
+ driveID.atap_extensions = 0x6;
// Setup default C/H/S settings
- driveID.cyls = cylinders;
- driveID.sectors = sectors;
- driveID.heads = heads;
+ driveID.atap_cylinders = cylinders;
+ driveID.atap_sectors = sectors;
+ driveID.atap_heads = heads;
// Setup the current multisector transfer size
- driveID.multsect = MAX_MULTSECT;
- driveID.multsect_valid = 0x1;
+ driveID.atap_curmulti = MAX_MULTSECT;
+ driveID.atap_curmulti_valid = 0x1;
// Number of sectors on disk
- driveID.lba_capacity = lba_size;
+ driveID.atap_capacity = lba_size;
// Multiword DMA mode 2 and below supported
- driveID.dma_mword = 0x400;
+ driveID.atap_dmamode_supp = 0x400;
// Set PIO mode 4 and 3 supported
- driveID.eide_pio_modes = 0x3;
+ driveID.atap_piomode_supp = 0x3;
// Set DMA mode 4 and below supported
- driveID.dma_ultra = 0x10;
+ driveID.atap_udmamode_supp = 0x10;
// Statically set hardware config word
- driveID.hw_config = 0x4001;
+ driveID.atap_hwreset_res = 0x4001;
}
IdeDisk::~IdeDisk()
// Decode commands
switch (cmdReg.command) {
// Supported non-data commands
- case WIN_READ_NATIVE_MAX:
+ case WDSF_READ_NATIVE_MAX:
size = image->size() - 1;
cmdReg.sec_num = (size & 0xff);
cmdReg.cyl_low = ((size & 0xff00) >> 8);
action = ACT_CMD_COMPLETE;
break;
- case WIN_RECAL:
- case WIN_SPECIFY:
- case WIN_STANDBYNOW1:
- case WIN_FLUSH_CACHE:
- case WIN_VERIFY:
- case WIN_SEEK:
- case WIN_SETFEATURES:
- case WIN_SETMULT:
+ case WDCC_RECAL:
+ case WDCC_IDP:
+ case WDCC_STANDBY_IMMED:
+ case WDCC_FLUSHCACHE:
+ case WDSF_VERIFY:
+ case WDSF_SEEK:
+ case SET_FEATURES:
+ case WDCC_SETMULTI:
devState = Command_Execution;
action = ACT_CMD_COMPLETE;
break;
// Supported PIO data-in commands
- case WIN_IDENTIFY:
- cmdBytes = cmdBytesLeft = sizeof(struct hd_driveid);
+ case WDCC_IDENTIFY:
+ cmdBytes = cmdBytesLeft = sizeof(struct ataparams);
devState = Prepare_Data_In;
action = ACT_DATA_READY;
break;
- case WIN_MULTREAD:
- case WIN_READ:
+ case WDCC_READMULTI:
+ case WDCC_READ:
if (!(cmdReg.drive & DRIVE_LBA_BIT))
panic("Attempt to perform CHS access, only supports LBA\n");
break;
// Supported PIO data-out commands
- case WIN_MULTWRITE:
- case WIN_WRITE:
+ case WDCC_WRITEMULTI:
+ case WDCC_WRITE:
if (!(cmdReg.drive & DRIVE_LBA_BIT))
panic("Attempt to perform CHS access, only supports LBA\n");
break;
// Supported DMA commands
- case WIN_WRITEDMA:
+ case WDCC_WRITEDMA:
dmaRead = true; // a write to the disk is a DMA read from memory
- case WIN_READDMA:
+ case WDCC_READDMA:
if (!(cmdReg.drive & DRIVE_LBA_BIT))
panic("Attempt to perform CHS access, only supports LBA\n");
status |= STATUS_DRQ_BIT;
// copy the data into the data buffer
- if (cmdReg.command == WIN_IDENTIFY) {
+ if (cmdReg.command == WDCC_IDENTIFY) {
// Reset the drqBytes for this block
- drqBytesLeft = sizeof(struct hd_driveid);
+ drqBytesLeft = sizeof(struct ataparams);
memcpy((void *)dataBuffer, (void *)&driveID,
- sizeof(struct hd_driveid));
+ sizeof(struct ataparams));
} else {
// Reset the drqBytes for this block
drqBytesLeft = SectorSize;
#ifndef __IDE_DISK_HH__
#define __IDE_DISK_HH__
-#include "dev/ide.hh"
#include "dev/disk_image.hh"
+#include "dev/ide_atareg.h"
+#include "dev/ide_wdcreg.h"
#include "dev/io_device.hh"
#include "sim/eventq.hh"
private:
/** Drive identification structure for this disk */
- struct hd_driveid driveID;
+ struct ataparams driveID;
/** Data buffer for transfers */
uint8_t *dataBuffer;
/** Number of bytes in command data transfer */
--- /dev/null
+/* $OpenBSD: wdcreg.h,v 1.13 2004/09/24 07:05:44 grange Exp $ */
+/* $NetBSD: wdcreg.h,v 1.22 1999/03/07 14:02:54 bouyer Exp $ */
+
+/*-
+ * Copyright (c) 1991 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * William Jolitz.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * @(#)wdreg.h 7.1 (Berkeley) 5/9/91
+ */
+
+#ifndef _DEV_IC_WDCREG_H_
+#define _DEV_IC_WDCREG_H_
+
+/*
+ * Controller register (wdr_ctlr)
+ */
+#define WDCTL_4BIT 0x08 /* use four head bits (wd1003) */
+#define WDCTL_RST 0x04 /* reset the controller */
+#define WDCTL_IDS 0x02 /* disable controller interrupts */
+
+/*
+ * Status bits.
+ */
+#define WDCS_BSY 0x80 /* busy */
+#define WDCS_DRDY 0x40 /* drive ready */
+#define WDCS_DWF 0x20 /* drive write fault */
+#define WDCS_DSC 0x10 /* drive seek complete */
+#define WDCS_DRQ 0x08 /* data request */
+#define WDCS_CORR 0x04 /* corrected data */
+#define WDCS_IDX 0x02 /* index */
+#define WDCS_ERR 0x01 /* error */
+#define WDCS_BITS "\020\010BSY\007DRDY\006DWF\005DSC\004DRQ\003CORR\002IDX\001ERR"
+
+/*
+ * Error bits.
+ */
+#define WDCE_BBK 0x80 /* bad block detected */
+#define WDCE_CRC 0x80 /* CRC error (Ultra-DMA only) */
+#define WDCE_UNC 0x40 /* uncorrectable data error */
+#define WDCE_MC 0x20 /* media changed */
+#define WDCE_IDNF 0x10 /* id not found */
+#define WDCE_MCR 0x08 /* media change requested */
+#define WDCE_ABRT 0x04 /* aborted command */
+#define WDCE_TK0NF 0x02 /* track 0 not found */
+#define WDCE_AMNF 0x01 /* address mark not found */
+
+/*
+ * Commands for Disk Controller.
+ */
+#define WDCC_NOP 0x00 /* NOP - Always fail with "aborted command" */
+#define WDCC_RECAL 0x10 /* disk restore code -- resets cntlr */
+
+#define WDCC_READ 0x20 /* disk read code */
+#define WDCC_WRITE 0x30 /* disk write code */
+#define WDCC__LONG 0x02 /* modifier -- access ecc bytes */
+#define WDCC__NORETRY 0x01 /* modifier -- no retrys */
+
+#define WDCC_FORMAT 0x50 /* disk format code */
+#define WDCC_DIAGNOSE 0x90 /* controller diagnostic */
+#define WDCC_IDP 0x91 /* initialize drive parameters */
+
+#define WDCC_READMULTI 0xc4 /* read multiple */
+#define WDCC_WRITEMULTI 0xc5 /* write multiple */
+#define WDCC_SETMULTI 0xc6 /* set multiple mode */
+
+#define WDCC_READDMA 0xc8 /* read with DMA */
+#define WDCC_WRITEDMA 0xca /* write with DMA */
+
+#define WDCC_ACKMC 0xdb /* acknowledge media change */
+#define WDCC_LOCK 0xde /* lock drawer */
+#define WDCC_UNLOCK 0xdf /* unlock drawer */
+
+#define WDCC_FLUSHCACHE 0xe7 /* Flush cache */
+#define WDCC_IDENTIFY 0xec /* read parameters from controller */
+#define SET_FEATURES 0xef /* set features */
+
+#define WDCC_IDLE 0xe3 /* set idle timer & enter idle mode */
+#define WDCC_IDLE_IMMED 0xe1 /* enter idle mode */
+#define WDCC_SLEEP 0xe6 /* enter sleep mode */
+#define WDCC_STANDBY 0xe2 /* set standby timer & enter standby mode */
+#define WDCC_STANDBY_IMMED 0xe0 /* enter standby mode */
+#define WDCC_CHECK_PWR 0xe5 /* check power mode */
+
+#define WDCC_READ_EXT 0x24 /* read 48-bit addressing */
+#define WDCC_WRITE_EXT 0x34 /* write 48-bit addressing */
+
+#define WDCC_READMULTI_EXT 0x29 /* read multiple 48-bit addressing */
+#define WDCC_WRITEMULTI_EXT 0x39 /* write multiple 48-bit addressing */
+
+#define WDCC_READDMA_EXT 0x25 /* read 48-bit addressing with DMA */
+#define WDCC_WRITEDMA_EXT 0x35 /* write 48-bit addressing with DMA */
+
+#define WDCC_FLUSHCACHE_EXT 0xea /* 48-bit addressing flush cache */
+
+/* Subcommands for SET_FEATURES (features register ) */
+#define WDSF_8BIT_PIO_EN 0x01 /* Enable 8bit PIO (CFA featureset) */
+#define WDSF_EN_WR_CACHE 0x02
+#define WDSF_SET_MODE 0x03
+#define WDSF_REASSIGN_EN 0x04 /* Obsolete in ATA-6 */
+#define WDSF_APM_EN 0x05 /* Enable Adv. Power Management */
+#define WDSF_PUIS_EN 0x06 /* Enable Power-Up In Standby */
+#define WDSF_PUIS_SPINUP 0x07 /* Power-Up In Standby spin-up */
+#define WDSF_CFA_MODE1_EN 0x0A /* Enable CFA power mode 1 */
+#define WDSF_RMSN_DS 0x31 /* Disable Removable Media Status */
+#define WDSF_RETRY_DS 0x33 /* Obsolete in ATA-6 */
+#define WDSF_AAM_EN 0x42 /* Enable Autom. Acoustic Management */
+#define WDSF_SET_CACHE_SGMT 0x54 /* Obsolete in ATA-6 */
+#define WDSF_READAHEAD_DS 0x55 /* Disable read look-ahead */
+#define WDSF_RLSE_EN 0x5D /* Enable release interrupt */
+#define WDSF_SRV_EN 0x5E /* Enable SERVICE interrupt */
+#define WDSF_POD_DS 0x66
+#define WDSF_ECC_DS 0x77
+#define WDSF_8BIT_PIO_DS 0x81 /* Disable 8bit PIO (CFA featureset) */
+#define WDSF_WRITE_CACHE_DS 0x82
+#define WDSF_REASSIGN_DS 0x84
+#define WDSF_APM_DS 0x85 /* Disable Adv. Power Management */
+#define WDSF_PUIS_DS 0x86 /* Disable Power-Up In Standby */
+#define WDSF_ECC_EN 0x88
+#define WDSF_CFA_MODE1_DS 0x8A /* Disable CFA power mode 1 */
+#define WDSF_RMSN_EN 0x95 /* Enable Removable Media Status */
+#define WDSF_RETRY_EN 0x99 /* Obsolete in ATA-6 */
+#define WDSF_SET_CURRENT 0x9A /* Obsolete in ATA-6 */
+#define WDSF_READAHEAD_EN 0xAA
+#define WDSF_PREFETCH_SET 0xAB /* Obsolete in ATA-6 */
+#define WDSF_AAM_DS 0xC2 /* Disable Autom. Acoustic Management */
+#define WDSF_POD_EN 0xCC
+#define WDSF_RLSE_DS 0xDD /* Disable release interrupt */
+#define WDSF_SRV_DS 0xDE /* Disable SERVICE interrupt */
+#define WDSF_READ_NATIVE_MAX 0xF8
+#define WDSF_SEEK 0x70
+#define WDSF_VERIFY 0x40
+
+/* parameters uploaded to device/heads register */
+#define WDSD_IBM 0xa0 /* forced to 512 byte sector, ecc */
+#define WDSD_CHS 0x00 /* cylinder/head/sector addressing */
+#define WDSD_LBA 0x40 /* logical block addressing */
+
+/* Commands for ATAPI devices */
+#define ATAPI_CHECK_POWER_MODE 0xe5
+#define ATAPI_EXEC_DRIVE_DIAGS 0x90
+#define ATAPI_IDLE_IMMEDIATE 0xe1
+#define ATAPI_NOP 0x00
+#define ATAPI_PKT_CMD 0xa0
+#define ATAPI_IDENTIFY_DEVICE 0xa1
+#define ATAPI_SOFT_RESET 0x08
+#define ATAPI_DEVICE_RESET 0x08 /* ATA/ATAPI-5 name for soft reset */
+#define ATAPI_SLEEP 0xe6
+#define ATAPI_STANDBY_IMMEDIATE 0xe0
+#define ATAPI_SMART 0xB0 /* SMART operations */
+#define ATAPI_SETMAX 0xF9 /* Set Max Address */
+#define ATAPI_WRITEEXT 0x34 /* Write sectors Ext */
+#define ATAPI_SETMAXEXT 0x37 /* Set Max Address Ext */
+#define ATAPI_WRITEMULTIEXT 0x39 /* Write Multi Ext */
+
+/* Bytes used by ATAPI_PACKET_COMMAND ( feature register) */
+#define ATAPI_PKT_CMD_FTRE_DMA 0x01
+#define ATAPI_PKT_CMD_FTRE_OVL 0x02
+
+/* ireason */
+#define WDCI_CMD 0x01 /* command(1) or data(0) */
+#define WDCI_IN 0x02 /* transfer to(1) or from(0) the host */
+#define WDCI_RELEASE 0x04 /* bus released until completion */
+
+#define PHASE_CMDOUT (WDCS_DRQ | WDCI_CMD)
+#define PHASE_DATAIN (WDCS_DRQ | WDCI_IN)
+#define PHASE_DATAOUT WDCS_DRQ
+#define PHASE_COMPLETED (WDCI_IN | WDCI_CMD)
+#define PHASE_ABORTED 0
+
+#endif /* !_DEV_IC_WDCREG_H_ */
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-/* @file
+/** @file
* Emulation of the Tsunami CChip CSRs
*/
#include "base/range.hh"
#include "dev/io_device.hh"
-/*
- * Tsunami CChip
+/**
+ * Tsunami CChip CSR Emulation. This device includes all the interrupt
+ * handling code for the chipset.
*/
class TsunamiCChip : public PioDevice
{
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-/* @file
- * Tsunami Fake I/O Space mapping including RTC/timer interrupts
+/** @file
+ * Tsunami I/O Space mapping including RTC/timer interrupts
*/
#ifndef __DEV_TSUNAMI_IO_HH__
#include "dev/tsunami.hh"
#include "sim/eventq.hh"
-/*
+/**
* Tsunami I/O device is a catch all for all the south bridge stuff we care
* to implement.
*/
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-/* @file
- * Tsunami PChip
+/** @file
+ * Tsunami PCI interface CSRs
*/
#ifndef __TSUNAMI_PCHIP_HH__
#include "base/range.hh"
#include "dev/io_device.hh"
-/*
- * Tsunami PChip
+/**
+ * A very simple implementation of the Tsunami PCI interface chips.
*/
class TsunamiPChip : public PioDevice
{
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