x86: pc: Put a stub IO device at port 0xed which the kernel can use for delays.

There was already a stub device at 0x80, the port traditionally used for an IO
delay. 0x80 is also the port used for POST codes sent by firmware, and that
may have prompted adding this port as a second option.

diff --git a/src/dev/x86/Pc.py b/src/dev/x86/Pc.py
index 1f1f3ca89ba3a345f277583ed85d6800e4ecccc7..8740159c49a9c8b1526f35534a2d0af799da5ea8 100644 (file)
--- a/src/dev/x86/Pc.py
+++ b/src/dev/x86/Pc.py
@@ -49,8 +49,9 @@ class Pc(Platform):
 
     south_bridge = SouthBridge()
 
-    # "Non-existant" port used for timing purposes by the linux kernel
-    i_dont_exist = IsaFake(pio_addr=x86IOAddress(0x80), pio_size=1)
+    # "Non-existant" ports used for timing purposes by the linux kernel
+    i_dont_exist1 = IsaFake(pio_addr=x86IOAddress(0x80), pio_size=1)
+    i_dont_exist2 = IsaFake(pio_addr=x86IOAddress(0xed), pio_size=1)
 
     # Ports behind the pci config and data regsiters. These don't do anything,
     # but the linux kernel fiddles with them anway.
@@ -71,7 +72,8 @@ class Pc(Platform):
 
     def attachIO(self, bus, dma_ports = []):
         self.south_bridge.attachIO(bus, dma_ports)
-        self.i_dont_exist.pio = bus.master
+        self.i_dont_exist1.pio = bus.master
+        self.i_dont_exist2.pio = bus.master
         self.behind_pci.pio = bus.master
         self.com_1.pio = bus.master
         self.fake_com_2.pio = bus.master