i965/fs: Set compression only if writing two registers.

We don't want to set compression control on a SIMD16 instruction
operating on words or smaller.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index af08f9d6d071dd0079ed5ae673a6890ce5d2c281..397d8257a9188c25e47bf4de1ca7c1259862ba94 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -1631,7 +1631,10 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
          break;
       case 16:
       case 32:
-         brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
+         if (type_sz(inst->dst.type) < sizeof(float))
+            brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
+         else
+            brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
          break;
       default:
          unreachable("Invalid instruction width");