anv/cmd_buffer: Move vb_dirty bits into anv_cmd_graphics_state

Vertex buffers are entirely a graphics pipeline thing.

Tested-by: Józef Kucia <joseph.kucia@gmail.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Cc: "18.0" <mesa-stable@lists.freedesktop.org>

diff --git a/src/intel/vulkan/anv_cmd_buffer.c b/src/intel/vulkan/anv_cmd_buffer.c
index ad5baeea08b4d5327d05467f02007c2803e996cc..dd6fb9d23116680a6dab6c9c12e7282b8f05369f 100644 (file)
--- a/src/intel/vulkan/anv_cmd_buffer.c
+++ b/src/intel/vulkan/anv_cmd_buffer.c
@@ -352,7 +352,7 @@ void anv_CmdBindPipeline(
 
    case VK_PIPELINE_BIND_POINT_GRAPHICS:
       cmd_buffer->state.gfx.base.pipeline = pipeline;
-      cmd_buffer->state.vb_dirty |= pipeline->vb_used;
+      cmd_buffer->state.gfx.vb_dirty |= pipeline->vb_used;
       cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_PIPELINE;
       cmd_buffer->state.push_constants_dirty |= pipeline->active_stages;
       cmd_buffer->state.descriptors_dirty |= pipeline->active_stages;
@@ -590,7 +590,7 @@ void anv_CmdBindVertexBuffers(
    for (uint32_t i = 0; i < bindingCount; i++) {
       vb[firstBinding + i].buffer = anv_buffer_from_handle(pBuffers[i]);
       vb[firstBinding + i].offset = pOffsets[i];
-      cmd_buffer->state.vb_dirty |= 1 << (firstBinding + i);
+      cmd_buffer->state.gfx.vb_dirty |= 1 << (firstBinding + i);
    }
 }
 

diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index c10f65d4f06dfce4af0bd27d9439e416f6124278..29aac7cf2c16c085ad5bec535547ae86dcc546ef 100644 (file)
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -1693,6 +1693,7 @@ struct anv_cmd_graphics_state {
    struct anv_cmd_pipeline_state base;
 
    anv_cmd_dirty_mask_t dirty;
+   uint32_t vb_dirty;
 };
 
 /** State tracking for compute pipeline
@@ -1717,7 +1718,6 @@ struct anv_cmd_state {
    struct anv_cmd_graphics_state                gfx;
    struct anv_cmd_compute_state                 compute;
 
-   uint32_t                                     vb_dirty;
    enum anv_pipe_bits                           pending_pipe_bits;
    uint32_t                                     num_workgroups_offset;
    struct anv_bo                                *num_workgroups_bo;

diff --git a/src/intel/vulkan/genX_blorp_exec.c b/src/intel/vulkan/genX_blorp_exec.c
index 871ade82450c5a53dd25d11b8f0fc2ac1296506f..04f76755de529271eabbd1ec66e6fec9ee96eb14 100644 (file)
--- a/src/intel/vulkan/genX_blorp_exec.c
+++ b/src/intel/vulkan/genX_blorp_exec.c
@@ -218,7 +218,7 @@ genX(blorp_exec)(struct blorp_batch *batch,
 
    blorp_exec(batch, params);
 
-   cmd_buffer->state.vb_dirty = ~0;
+   cmd_buffer->state.gfx.vb_dirty = ~0;
    cmd_buffer->state.gfx.dirty = ~0;
    cmd_buffer->state.push_constants_dirty = ~0;
 }

diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index a1543969dd790320792eec1c1527f78856413f9f..f4b44111e3d20a40831f6d820a5c34b88dcf73c0 100644 (file)
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -2011,7 +2011,7 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
    struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline;
    uint32_t *p;
 
-   uint32_t vb_emit = cmd_buffer->state.vb_dirty & pipeline->vb_used;
+   uint32_t vb_emit = cmd_buffer->state.gfx.vb_dirty & pipeline->vb_used;
 
    assert((pipeline->active_stages & VK_SHADER_STAGE_COMPUTE_BIT) == 0);
 
@@ -2062,7 +2062,7 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
       }
    }
 
-   cmd_buffer->state.vb_dirty &= ~vb_emit;
+   cmd_buffer->state.gfx.vb_dirty &= ~vb_emit;
 
    if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_PIPELINE) {
       anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
@@ -3150,7 +3150,7 @@ genX(cmd_buffer_set_subpass)(struct anv_cmd_buffer *cmd_buffer,
     * of each subpass.
     */
    if (GEN_GEN == 7)
-      cmd_buffer->state.vb_dirty |= ~0;
+      cmd_buffer->state.gfx.vb_dirty |= ~0;
 
    /* Perform transitions to the subpass layout before any writes have
     * occurred.