Working on the hardware for loop

diff --git a/Cesar_Strauss.mdwn b/Cesar_Strauss.mdwn
index c88b2e0748c67c93a045dc92eeda149e5aa54432..492a8f24a5ffbb29b66abec333fab07b823b200b 100644 (file)
--- a/Cesar_Strauss.mdwn
+++ b/Cesar_Strauss.mdwn
@@ -62,6 +62,10 @@ unit tests.
         <https://bugs.libre-soc.org/show_bug.cgi?id=565>  
         Status: in progress  
 
+13. Implement simple VL for-loop in nMigen for TestIssuer  
+        <https://bugs.libre-soc.org/show_bug.cgi?id=583>  
+        Status: in progress  
+
 ## Completed but not yet submitted:
 
 1. FSM-based ALU example needed (compliant with ALU CompUnit)