tex_out/int_fp_mv.tex tex_out/av_opcodes.tex \
tex_out/big_integer.tex \
tex_out/pseudocode_fixedshift.tex \
+ tex_out/pseudocode_bcd.tex tex_out/pseudocode_branch.tex \
+ tex_out/pseudocode_comparefixed.tex \
+ tex_out/pseudocode_condition.tex \
tex_out/pseudocode_svfparith.tex \
tex_out/pseudocode_fixedarith.tex \
+ tex_out/pseudocode_fixedload.tex \
tex_out/pseudocode_fixedlogical.tex \
tex_out/pseudocode_svfixedarith.tex \
tex_out/big_integer_analysis.tex \
--filter pandoc_img.py \
-N -o tex_out/bitmanip.tex tex_out/bitmanip.mdwn
+tex_out/pseudocode_bcd.tex : $(ISA_DIR)/bcd.mdwn
+ mkdir -p tex_out
+ pandoc -f markdown -t latex --top-level-division=section \
+ --filter pandoc_img.py \
+ -N -o tex_out/pseudocode_bcd.tex \
+ $(ISA_DIR)/bcd.mdwn
+
+tex_out/pseudocode_branch.tex : $(ISA_DIR)/branch.mdwn
+ mkdir -p tex_out
+ pandoc -f markdown -t latex --top-level-division=section \
+ --filter pandoc_img.py \
+ -N -o tex_out/pseudocode_branch.tex \
+ $(ISA_DIR)/branch.mdwn
+
+tex_out/pseudocode_comparefixed.tex : $(ISA_DIR)/comparefixed.mdwn
+ mkdir -p tex_out
+ pandoc -f markdown -t latex --top-level-division=section \
+ --filter pandoc_img.py \
+ -N -o tex_out/pseudocode_comparefixed.tex \
+ $(ISA_DIR)/comparefixed.mdwn
+
+tex_out/pseudocode_condition.tex : $(ISA_DIR)/condition.mdwn
+ mkdir -p tex_out
+ pandoc -f markdown -t latex --top-level-division=section \
+ --filter pandoc_img.py \
+ -N -o tex_out/pseudocode_condition.tex \
+ $(ISA_DIR)/condition.mdwn
+
+tex_out/pseudocode_fixedload.tex : $(ISA_DIR)/fixedload.mdwn
+ mkdir -p tex_out
+ pandoc -f markdown -t latex --top-level-division=section \
+ --filter pandoc_img.py \
+ -N -o tex_out/pseudocode_fixedload.tex \
+ $(ISA_DIR)/fixedload.mdwn
+
+
+
simple_v_spec.pdf : tex simple_v_spec.tex
pdflatex -synctex=1 -interaction=nonstopmode simple_v_spec.tex
to extend to 128-bit in future (like RV128).
\begin{appendices}
+\chapter{Binary Coded Decimal pseudocode}
+\hypertarget{svux2fpseudocode_bcd}{}
+\input{tex_out/pseudocode_bcd.tex}
+\chapter{Branch pseudocode}
+\hypertarget{svux2fpseudocode_branch}{}
+\input{tex_out/pseudocode_branch.tex}
+\chapter{Fixed Point Compare pseudocode}
+\hypertarget{svux2fpseudocode_comparefixed}{}
+\input{tex_out/pseudocode_comparefixed.tex}
+\chapter{Condition Register pseudocode}
+\hypertarget{svux2fpseudocode_condition}{}
+\input{tex_out/pseudocode_condition.tex}
+
\chapter{Fixed Point Arithmetic pseudocode}
\hypertarget{svux2fpseudocode_fixedarith}{}
\input{tex_out/pseudocode_fixedarith.tex}
+\chapter{Fixed Point Load pseudocode}
+\hypertarget{svux2fpseudocode_fixedload}{}
+\input{tex_out/pseudocode_fixedload.tex}
\chapter{Fixed Point Logical pseudocode}
\hypertarget{svux2fpseudocode_fixedlogical}{}
\input{tex_out/pseudocode_fixedlogical.tex}
+
+\chapter{Fixed Point Rotate pseudocode}
+\hypertarget{svux2fpseudocode_fixedshift}{}
+\input{tex_out/pseudocode_fixedshift.tex}
\end{appendices}