x86: Support VEX base opcode length > 1

Intel AMX instructions with 8-bit immediate opcode extension without
operands:

tilerelease, 0, 0x49c0, None, 2, CpuAMX_TILE|Cpu64, Vex|VexOpcode=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }

Update build_vex_prefix to support VEX base opcode length > 1.

	* tc-i386.c (build_vex_prefix): Support VEX base opcode length > 1.
	(md_assemble): Don't process ImmExt without operands.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index fdec78bfa2200cf79b91f04f58c4a70f359eaeeb..e3e1c4749f905ae1ae630d9610af945aa83087f1 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2020-06-29  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * tc-i386.c (build_vex_prefix): Support VEX base opcode length > 1.
+       (md_assemble): Don't process ImmExt without operands.
+
 2020-06-29  Hans-Peter Nilsson  <hp@bitrange.com>
 
        PR gas/25331

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index ae2a2c1a5367aff595b94799077da3f63af0edfb..be894782a457a6e7902d86b5ed9142102c944e77 100644 (file)
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -3664,7 +3664,7 @@ build_vex_prefix (const insn_template *t)
          }
     }
 
-  switch ((i.tm.base_opcode >> 8) & 0xff)
+  switch ((i.tm.base_opcode >> (i.tm.opcode_length << 3)) & 0xff)
     {
     case 0:
       implied_prefix = 0;
@@ -4873,12 +4873,8 @@ md_assemble (char *line)
       if (!process_operands ())
        return;
     }
-  else
+  else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
     {
-      if (i.tm.opcode_modifier.immext)
-       process_immext ();
-
-      if (!quiet_warnings && i.tm.opcode_modifier.ugh)
       /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc.  */
       as_warn (_("translating to `%sp'"), i.tm.name);
     }