projects
/
yosys.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
| inline |
side by side
(parent:
c372e7b
)
Avoid work in replace() if rules empty.
author
Henner Zeller
<h.zeller@acm.org>
Sun, 29 Sep 2019 07:17:40 +0000
(
00:17
-0700)
committer
Henner Zeller
<h.zeller@acm.org>
Sun, 29 Sep 2019 07:17:40 +0000
(
00:17
-0700)
This speeds up processing when number of bits are large but there
is actually nothing to replace. Adresses part of #1382.
Signed-off-by: Henner Zeller <h.zeller@acm.org>
kernel/rtlil.cc
patch
|
blob
|
history
diff --git
a/kernel/rtlil.cc
b/kernel/rtlil.cc
index 1d380135b60af0307e0ecf08287595afeac05582..17be28f78277067d234eda60e3f243568bd4e760 100644
(file)
--- a/
kernel/rtlil.cc
+++ b/
kernel/rtlil.cc
@@
-3083,6
+3083,7
@@
void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RT
log_assert(other != NULL);
log_assert(width_ == other->width_);
+ if (rules.empty()) return;
unpack();
other->unpack();
@@
-3107,6
+3108,7
@@
void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules
log_assert(other != NULL);
log_assert(width_ == other->width_);
+ if (rules.empty()) return;
unpack();
other->unpack();