MSP430: Support a memory operand for op1 of andneghi3

This fixes an ICE caused by an unrecognizeable insn generated when
compiling gcc.c-torture/execute/pr97386-1.c at -O0.

gcc/ChangeLog:

	* config/msp430/msp430.md (andneghi3): Allow general operand for
	op1 and update output assembler template.

diff --git a/gcc/config/msp430/msp430.md b/gcc/config/msp430/msp430.md
index f70e61b97ddf8310dc67d8e3ae1c10fe0bb456b3..ad244bb0f3396724f3efbbd345c4e9f5f92ad3d9 100644 (file)
--- a/gcc/config/msp430/msp430.md
+++ b/gcc/config/msp430/msp430.md
@@ -1346,12 +1346,12 @@
 ;; instructions, so we provide a pattern to support it here.
 (define_insn "andneghi3"
   [(set (match_operand:HI                 0 "register_operand" "=r")
-       (and:HI (neg:HI (match_operand:HI 1 "register_operand"  "r"))
+       (and:HI (neg:HI (match_operand:HI 1 "general_operand"  "rm"))
                (match_operand            2 "immediate_operand" "n")))]
   ""
   "*
     if (REGNO (operands[0]) != REGNO (operands[1]))
-      return \"MOV.W\t%1, %0 { INV.W\t%0 { INC.W\t%0 { AND.W\t%2, %0\";
+      return \"MOV%X1.W\t%1, %0 { INV.W\t%0 { INC.W\t%0 { AND.W\t%2, %0\";
     else
       return \"INV.W\t%0 { INC.W\t%0 { AND.W\t%2, %0\";
   "