(no commit message)

diff --git a/openpower/sv/cr_int_predication.mdwn b/openpower/sv/cr_int_predication.mdwn
index 9da87f9a5833e5c7e865f687b0ace05d87c50dd8..c30776ef32544e534c19b2a63ecc04e52a6d7372 100644 (file)
--- a/openpower/sv/cr_int_predication.mdwn
+++ b/openpower/sv/cr_int_predication.mdwn
@@ -70,6 +70,8 @@ Useful side-effects:
   or destination GPR, in ways that are not possible with other
   SVP64 instructions because normal SVP64 is bit-per-element.
   On these weird instructions the element in effect *is* a bit.
+* `mfcrweird` mitigates a need to add `conflictd`, part of
+  [[sv/vector_ops]], as well as allowing more complex comparisons.
 
 # Bit ordering.