(no commit message)

diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index 8b68d7472b3bbbb505945aaac766b819bd63d110..53c4ce0ec6109a259e47897f54b1fc9d465c0b79 100644 (file)
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -393,7 +393,8 @@ and manual reordering of the Vector of RB offsets.
 ## LD/ST ffirst (Fault-First)
 
 LD/ST ffirst treats the first LD/ST in a vector (element 0 if REMAP
-is not active) as an ordinary one, with all behaviour with respect to
+is not active and predication is not applied)
+as an ordinary one, with all behaviour with respect to
 Interrupts Exceptions Page Faults Memory Management being identical
 in every regard to Scalar v3.0 Power ISA LD/ST. However for elements
 1 and above, if an exception would occur, then VL is **truncated**
@@ -407,7 +408,9 @@ considered a security risk due to the abuse of probing multiple
 pages in rapid succession and getting speculative feedback on which
 pages would fail.  Therefore Vector Indexed LD/ST is prohibited
 entirely, and the Mode bit instead used for element-strided LD/ST.
+<!-- hide -->
 See <https://bugs.libre-soc.org/show_bug.cgi?id=561>
+<!-- show -->
 
 ```
     for(i = 0; i < VL; i++)
@@ -437,6 +440,9 @@ operations on an aligned boundary such as the beginning of a cache line,
 or beginning of a Virtual Memory page. Likewise, to reduce workloads or
 balance resources.
 
+When Predication is used, the "first" element is considered to be the first
+non-predicated element rather than specifically `srcstep=0`.
+
 Vertical-First Mode is slightly strange in that only one element at a time
 is ever executed anyway.  Given that programmers may legitimately choose
 to alter srcstep and dststep in non-sequential order as part of explicit