freedreno: make gmem tile size alignment configurable
authorRob Clark <robdclark@gmail.com>
Wed, 23 Nov 2016 14:53:44 +0000 (09:53 -0500)
committerRob Clark <robdclark@gmail.com>
Wed, 30 Nov 2016 17:25:48 +0000 (12:25 -0500)
a5xx seems to prefer 64 pixel alignment, in at least some cases.  Make
this configurable per generation.

Signed-off-by: Rob Clark <robdclark@gmail.com>
src/gallium/drivers/freedreno/freedreno_gmem.c
src/gallium/drivers/freedreno/freedreno_screen.c
src/gallium/drivers/freedreno/freedreno_screen.h

index ed625e455af7b6039df7401ff4e95731350106f6..b94e33d285eb83b10d86e21b050fea9bd125e155 100644 (file)
@@ -109,7 +109,8 @@ calculate_tiles(struct fd_batch *batch)
        struct fd_gmem_stateobj *gmem = &ctx->gmem;
        struct pipe_scissor_state *scissor = &batch->max_scissor;
        struct pipe_framebuffer_state *pfb = &batch->framebuffer;
-       uint32_t gmem_size = ctx->screen->gmemsize_bytes;
+       const uint32_t gmem_alignment = ctx->screen->gmem_alignment;
+       const uint32_t gmem_size = ctx->screen->gmemsize_bytes;
        uint32_t minx, miny, width, height;
        uint32_t nbins_x = 1, nbins_y = 1;
        uint32_t bin_w, bin_h;
@@ -146,21 +147,22 @@ calculate_tiles(struct fd_batch *batch)
                width = pfb->width;
                height = pfb->height;
        } else {
-               minx = scissor->minx & ~31; /* round down to multiple of 32 */
-               miny = scissor->miny & ~31;
+               /* round down to multiple of alignment: */
+               minx = scissor->minx & ~(gmem_alignment - 1);
+               miny = scissor->miny & ~(gmem_alignment - 1);
                width = scissor->maxx - minx;
                height = scissor->maxy - miny;
        }
 
-       bin_w = align(width, 32);
-       bin_h = align(height, 32);
+       bin_w = align(width, gmem_alignment);
+       bin_h = align(height, gmem_alignment);
 
        /* first, find a bin width that satisfies the maximum width
         * restrictions:
         */
        while (bin_w > max_width) {
                nbins_x++;
-               bin_w = align(width / nbins_x, 32);
+               bin_w = align(width / nbins_x, gmem_alignment);
        }
 
        if (fd_mesa_debug & FD_DBG_MSGS) {
@@ -177,10 +179,10 @@ calculate_tiles(struct fd_batch *batch)
        while (total_size(cbuf_cpp, zsbuf_cpp, bin_w, bin_h, gmem) > gmem_size) {
                if (bin_w > bin_h) {
                        nbins_x++;
-                       bin_w = align(width / nbins_x, 32);
+                       bin_w = align(width / nbins_x, gmem_alignment);
                } else {
                        nbins_y++;
-                       bin_h = align(height / nbins_y, 32);
+                       bin_h = align(height / nbins_y, gmem_alignment);
                }
        }
 
index fb35742f2c04438a958d00099c98867df6e72c33..f6ec5763f76f8c915f520c8410e677225595a60b 100644 (file)
@@ -672,6 +672,12 @@ fd_screen_create(struct fd_device *dev)
                goto fail;
        }
 
+       if (screen->gpu_id >= 500) {
+               screen->gmem_alignment = 64;
+       } else {
+               screen->gmem_alignment = 32;
+       }
+
        /* NOTE: don't enable reordering on a2xx, since completely untested.
         * Also, don't enable if we have too old of a kernel to support
         * growable cmdstream buffers, since memory requirement for cmdstream
index db9050e71be96b6c5451be81952895e3be8add64..3fc66fb960759aff527a2614a76a2cefcffe4aac 100644 (file)
@@ -64,6 +64,7 @@ struct fd_screen {
        uint32_t chip_id;        /* coreid:8 majorrev:8 minorrev:8 patch:8 */
        uint32_t max_freq;
        uint32_t max_rts;        /* max # of render targets */
+       uint32_t gmem_alignment;
        bool has_timestamp;
 
        void *compiler;          /* currently unused for a2xx */