radeonsi: add drirc option "radeonsi_assume_no_z_fights"

This option enables a performance optimization where typical non-blending
draws with depth buffer may be rasterized out-of-order (on VI+, multi-SE
chips).

This optimization can lead to incorrect results when an applications
renders multiple objects with the same Z value at the same pixel, so we
will never enable it by default. But there may be applications that could
benefit from white-listing.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>

diff --git a/src/gallium/drivers/radeonsi/driinfo_radeonsi.h b/src/gallium/drivers/radeonsi/driinfo_radeonsi.h
index af6284a7787a08d59c2a37f14baeefbf3c5e31aa..8be85289a0c3f9366186eb0b5fe9432ddcb8f95e 100644 (file)
--- a/src/gallium/drivers/radeonsi/driinfo_radeonsi.h
+++ b/src/gallium/drivers/radeonsi/driinfo_radeonsi.h
@@ -1,4 +1,5 @@
 // DriConf options specific to radeonsi
 DRI_CONF_SECTION_PERFORMANCE
     DRI_CONF_RADEONSI_ENABLE_SISCHED("false")
+    DRI_CONF_RADEONSI_ASSUME_NO_Z_FIGHTS("false")
 DRI_CONF_SECTION_END

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index 68d63692e4f5ff3f2855ae71b2392653484b1f0c..d6de152571752e31ce1f9e3f2862765255453ba9 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -1048,6 +1048,8 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
        sscreen->has_out_of_order_rast = sscreen->b.chip_class >= VI &&
                                         sscreen->b.info.max_se >= 2 &&
                                         !(sscreen->b.debug_flags & DBG_NO_OUT_OF_ORDER);
+       sscreen->assume_no_z_fights =
+               driQueryOptionb(config->options, "radeonsi_assume_no_z_fights");
        sscreen->has_msaa_sample_loc_bug = (sscreen->b.family >= CHIP_POLARIS10 &&
                                            sscreen->b.family <= CHIP_POLARIS12) ||
                                           sscreen->b.family == CHIP_VEGA10 ||

diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 6d9d3def7b526a560c35a626860cb66649d80265..3d33e4f0ffa71aada78c810ba2fdce5a6b6f2852 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -95,6 +95,7 @@ struct si_screen {
        bool                            has_distributed_tess;
        bool                            has_draw_indirect_multi;
        bool                            has_out_of_order_rast;
+       bool                            assume_no_z_fights;
        bool                            has_msaa_sample_loc_bug;
        bool                            dpbb_allowed;
        bool                            dfsm_allowed;

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 9287086038d5552e9dfa52ec74d4f0243d8f4638..66228af1d238e2193159d8a49f35b94865956098 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1094,6 +1094,7 @@ static bool si_order_invariant_stencil_state(const struct pipe_stencil_state *st
 static void *si_create_dsa_state(struct pipe_context *ctx,
                                 const struct pipe_depth_stencil_alpha_state *state)
 {
+       struct si_context *sctx = (struct si_context *)ctx;
        struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
        struct si_pm4_state *pm4 = &dsa->pm4;
        unsigned db_depth_control;
@@ -1186,13 +1187,12 @@ static void *si_create_dsa_state(struct pipe_context *ctx,
                (state->depth.func == PIPE_FUNC_ALWAYS ||
                 state->depth.func == PIPE_FUNC_NEVER);
 
-       const bool assume_no_z_fights = false;
-
        dsa->order_invariance[1].pass_last =
-               assume_no_z_fights && !dsa->stencil_write_enabled &&
+               sctx->screen->assume_no_z_fights &&
+               !dsa->stencil_write_enabled &&
                dsa->depth_write_enabled && zfunc_is_ordered;
        dsa->order_invariance[0].pass_last =
-               assume_no_z_fights &&
+               sctx->screen->assume_no_z_fights &&
                dsa->depth_write_enabled && zfunc_is_ordered;
 
        return dsa;

diff --git a/src/util/xmlpool/t_options.h b/src/util/xmlpool/t_options.h
index d3f31fc94b12f9f6ae677e382970f839e442cc57..c92215183a595d6682a2d2aad2af311a72459aeb 100644 (file)
--- a/src/util/xmlpool/t_options.h
+++ b/src/util/xmlpool/t_options.h
@@ -438,3 +438,8 @@ DRI_CONF_OPT_END
 DRI_CONF_OPT_BEGIN_B(radeonsi_enable_sisched, def) \
         DRI_CONF_DESC(en,gettext("Use the LLVM sisched option for shader compiles")) \
 DRI_CONF_OPT_END
+
+#define DRI_CONF_RADEONSI_ASSUME_NO_Z_FIGHTS(def) \
+DRI_CONF_OPT_BEGIN_B(radeonsi_assume_no_z_fights, def) \
+        DRI_CONF_DESC(en,gettext("Assume no Z fights (enables aggressive out-of-order rasterization to improve performance; may cause rendering errors)")) \
+DRI_CONF_OPT_END