(no commit message)

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index bad606195af4b8d3cfba31a94e8e7d9aa398c053..fac669f0c0a706aff9b4ee339f70cbf7470f3008 100644 (file)
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -29,13 +29,16 @@ instructions should be used without an SV Prefix.
 An interesting side-effect of this decision is that the OE flag is now
 free for other uses when SV Prefixing is used.
 
-Regarding XER.CA: this does not fit either: it was designed for a scalar
-ISA. Instead, both carry-in and carry-out go into the CR.so bit of a given
-Vector element.  This provides a means to perform large parallel batches
-of Vectorised carry-capable additions.  crweird instructions can be used
-to transfer the CRs in and out of an integer, where bitmanipulation
-may be performed to analyse the carry bits (including carry lookahead
-propagation) before continuing with further parallel additions.
+XER.CA/CA32 on the other hand is expected and required to be implemented
+according to standard Power ISA Scalar behaviour.  Interestingly, due
+to SVP64 being in effect a hardware for-loop around Scalar instructions
+executing in precise Program Order, a little thought shows that a Vectorised
+Carry-In-Out add is in effect a Big Integer Add, taking a single bit CarryIn
+and producing, at the end, a single bit Carry out.  High performance
+implementations may exploit this observation to deploy efficient
+Parallel Carry Lookahead.
+
+    sv.
 
 # v3.0B/v3.1 relevant instructions