bring in edits from web on ls010

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index 829474e205cc1c091af38f7a0963784077b8265a..728e09c9a0211be644963dbfa698aca4c8d30dad 100644 (file)
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -31,6 +31,8 @@ Links:
 * <https://bugs.libre-soc.org/show_bug.cgi?id=574> Saturating description.
 * <https://bugs.libre-soc.org/show_bug.cgi?id=905> TODO [[sv/svp64-single]]
 * <https://bugs.libre-soc.org/show_bug.cgi?id=1045> External RFC ls010
+* [[sv/branches]] chapter
+* [[sv/ldst]] chapter
 
 
 Table of contents
@@ -236,14 +238,19 @@ MSB0 numbering in both bits and elements, adapting in full to LSB0 numbering,
 and obeying LE ordering*.
 
 **Crucial to understanding why the subtraction from 1,3,7,15 is present
-is because VSX Registers number elements also in MSB0 order**. SVP64
-very specifically numbers elements in **LSB0** order with the first
-element being at the **LSB** end of the register, where VSX places
-the numerically-lowest element at the **MSB** end of the register.
+is because the Power ISA numbers VSX Registers elements also in MSB0 order**.
+SVP64 very specifically numbers elements in **LSB0** order with the first
+element (numbered zero) being at the bitwise-numbered **LSB** end of the register, where VSX
+does the reverse: places the numerically-*highest* (last-numbered) element at
+the LSB end of the register.
+
 
 ```
     #pragma pack
     typedef union {
+        // these do NOT match their Power ISA VSX numbering directly, they are all reversed
+        // bytes[15] is actually VSR.byte[0] for example.  if this convention is not
+        // followed then everything ends up in the wrong place
         uint8_t  bytes[16]; // elwidth 8, QTY 16 FIXED total
         uint16_t hwords[8]; // elwidth 16, QTY 8 FIXED total
         uint32_t words[4]; // elwidth 32, QTY 8 FIXED total