update VL format

diff --git a/simple_v_extension/vblock_format_table.mdwn b/simple_v_extension/vblock_format_table.mdwn
index a0c258eb7eebffee1706358aee7a2a530ffc0ad0..2c274a727d9ecff1ef27289d5d165a38c5b51159 100644 (file)
--- a/simple_v_extension/vblock_format_table.mdwn
+++ b/simple_v_extension/vblock_format_table.mdwn
@@ -23,6 +23,9 @@ The VL/MAXVL/SubVL Block format, when 16xil != 0b111, is:
 
 Note (1) - Registers are in RVC format (x8-x15)
 
+Note (2) - [[specification/sv.setvl]] behaviour is expected, as if an sv.setvl
+instruction had actually been called.
+
 When 16xil is 0b111, this is the "Extended" Format, using the >= 192-bit
 RISC-V ISA format.  Note that the length is 96+16\*nnnnn, not 192+