Nothing in the tree generates it.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
case TGSI_OPCODE_UP2US:
case TGSI_OPCODE_UP4B:
case TGSI_OPCODE_UP4UB:
- case TGSI_OPCODE_X2D:
case TGSI_OPCODE_BRA:
case TGSI_OPCODE_PUSHA:
case TGSI_OPCODE_POPA:
return FALSE;
break;
- case TGSI_OPCODE_X2D:
- /* deprecated? */
- assert(0);
- return FALSE;
- break;
-
case TGSI_OPCODE_ARR:
src0 = lp_build_emit_fetch(&bld->bld_base, inst, 0, LP_CHAN_ALL);
dst0 = lp_build_round(&bld->bld_base.base, src0);
}
}
-static void
-exec_x2d(struct tgsi_exec_machine *mach,
- const struct tgsi_full_instruction *inst)
-{
- union tgsi_exec_channel r[4];
- union tgsi_exec_channel d[2];
-
- fetch_source(mach, &r[0], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
- fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
- if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XZ) {
- fetch_source(mach, &r[2], &inst->Src[2], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
- micro_mul(&r[2], &r[2], &r[0]);
- fetch_source(mach, &r[3], &inst->Src[2], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
- micro_mul(&r[3], &r[3], &r[1]);
- micro_add(&r[2], &r[2], &r[3]);
- fetch_source(mach, &r[3], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
- micro_add(&d[0], &r[2], &r[3]);
- }
- if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_YW) {
- fetch_source(mach, &r[2], &inst->Src[2], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
- micro_mul(&r[2], &r[2], &r[0]);
- fetch_source(mach, &r[3], &inst->Src[2], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
- micro_mul(&r[3], &r[3], &r[1]);
- micro_add(&r[2], &r[2], &r[3]);
- fetch_source(mach, &r[3], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
- micro_add(&d[1], &r[2], &r[3]);
- }
- if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
- store_dest(mach, &d[0], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
- }
- if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
- store_dest(mach, &d[1], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
- }
- if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
- store_dest(mach, &d[0], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
- }
- if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
- store_dest(mach, &d[1], &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
- }
-}
-
static void
exec_rfl(struct tgsi_exec_machine *mach,
const struct tgsi_full_instruction *inst)
assert (0);
break;
- case TGSI_OPCODE_X2D:
- exec_x2d(mach, inst);
- break;
-
case TGSI_OPCODE_ARR:
exec_vector_unary(mach, inst, micro_arr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
break;
{ 1, 1, 0, 0, 0, 0, COMP, "UP2US", TGSI_OPCODE_UP2US },
{ 1, 1, 0, 0, 0, 0, COMP, "UP4B", TGSI_OPCODE_UP4B },
{ 1, 1, 0, 0, 0, 0, COMP, "UP4UB", TGSI_OPCODE_UP4UB },
- { 1, 3, 0, 0, 0, 0, COMP, "X2D", TGSI_OPCODE_X2D },
+ { 0, 1, 0, 0, 0, 1, NONE, "", 59 }, /* removed */
{ 0, 1, 0, 0, 0, 1, NONE, "", 60 }, /* removed */
{ 1, 1, 0, 0, 0, 0, COMP, "ARR", TGSI_OPCODE_ARR },
{ 0, 1, 0, 0, 0, 0, NONE, "BRA", TGSI_OPCODE_BRA },
OP11(UP2US)
OP11(UP4B)
OP11(UP4UB)
-OP13(X2D)
OP11(ARR)
OP01(BRA)
OP00_LBL(CAL)
Considered for removal.
-.. opcode:: X2D - 2D Coordinate Transformation
-
-.. math::
-
- dst.x = src0.x + src1.x \times src2.x + src1.y \times src2.y
-
- dst.y = src0.y + src1.x \times src2.z + src1.y \times src2.w
-
- dst.z = src0.x + src1.x \times src2.x + src1.y \times src2.y
-
- dst.w = src0.y + src1.x \times src2.z + src1.y \times src2.w
-
-.. note::
-
- Considered for removal.
-
.. opcode:: ARR - Address Register Load With Round
[TGSI_OPCODE_UP2US] = aos_unsupported,
[TGSI_OPCODE_UP4B] = aos_unsupported,
[TGSI_OPCODE_UP4UB] = aos_unsupported,
- [TGSI_OPCODE_X2D] = aos_unsupported,
[TGSI_OPCODE_ARR] = aos_simple,
[TGSI_OPCODE_BRA] = aos_unsupported,
[TGSI_OPCODE_CAL] = aos_unsupported,
[TGSI_OPCODE_UP2US] = soa_unsupported,
[TGSI_OPCODE_UP4B] = soa_unsupported,
[TGSI_OPCODE_UP4UB] = soa_unsupported,
- [TGSI_OPCODE_X2D] = soa_unsupported,
[TGSI_OPCODE_ARR] = soa_per_channel,
[TGSI_OPCODE_BRA] = soa_unsupported,
[TGSI_OPCODE_CAL] = soa_unsupported,
/* case TGSI_OPCODE_UP2US: return RC_OPCODE_UP2US; */
/* case TGSI_OPCODE_UP4B: return RC_OPCODE_UP4B; */
/* case TGSI_OPCODE_UP4UB: return RC_OPCODE_UP4UB; */
- /* case TGSI_OPCODE_X2D: return RC_OPCODE_X2D; */
/* case TGSI_OPCODE_ARR: return RC_OPCODE_ARR; */
/* case TGSI_OPCODE_BRA: return RC_OPCODE_BRA; */
/* case TGSI_OPCODE_CAL: return RC_OPCODE_CAL; */
{TGSI_OPCODE_UP2US, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_UP4B, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_UP4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
- {TGSI_OPCODE_X2D, 0, ALU_OP0_NOP, tgsi_unsupported},
+ {59, 0, ALU_OP0_NOP, tgsi_unsupported},
{60, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_ARR, 0, ALU_OP0_NOP, tgsi_r600_arl},
{TGSI_OPCODE_BRA, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_UP2US, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_UP4B, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_UP4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
- {TGSI_OPCODE_X2D, 0, ALU_OP0_NOP, tgsi_unsupported},
+ {59, 0, ALU_OP0_NOP, tgsi_unsupported},
{60, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_ARR, 0, ALU_OP0_NOP, tgsi_eg_arl},
{TGSI_OPCODE_BRA, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_UP2US, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_UP4B, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_UP4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
- {TGSI_OPCODE_X2D, 0, ALU_OP0_NOP, tgsi_unsupported},
+ {59, 0, ALU_OP0_NOP, tgsi_unsupported},
{60, 0, ALU_OP0_NOP, tgsi_unsupported},
{TGSI_OPCODE_ARR, 0, ALU_OP0_NOP, tgsi_eg_arl},
{TGSI_OPCODE_BRA, 0, ALU_OP0_NOP, tgsi_unsupported},
#define TGSI_OPCODE_UP2US 56
#define TGSI_OPCODE_UP4B 57
#define TGSI_OPCODE_UP4UB 58
-#define TGSI_OPCODE_X2D 59
/* gap */
#define TGSI_OPCODE_ARR 61
#define TGSI_OPCODE_BRA 62