iyl.append((iy+i, i==4))
il.append(i)
- y = [0] * 8
- t = [0] * 8
+ y = [0] * 8 # result y and temp t of same size
+ t = [0] * 8 # no need after this to set t[4] to zero
for iy in range(4):
- for i in range(4):
+ for i in range(4): # use t[iy+4] as a 64-bit carry
t[iy+i], t[iy+4] = maddedu(a[iy], b[i], t[iy+4])
ca = 0
- for i in range(5):
- y[iy + i], ca = adde(y[iy + i], t[iy+i], ca)
+ for i in range(5): # add vec t to y with 1-bit carry
+ idx = iy + i
+ y[idx], ca = adde(y[idx], t[idx], ca)
return y