}
}
-void nir_dest_copy(nir_dest *dest, const nir_dest *src, void *mem_ctx)
+void nir_dest_copy(nir_dest *dest, const nir_dest *src, nir_instr *instr)
{
/* Copying an SSA definition makes no sense whatsoever. */
assert(!src->is_ssa);
dest->reg.base_offset = src->reg.base_offset;
dest->reg.reg = src->reg.reg;
if (src->reg.indirect) {
- dest->reg.indirect = ralloc(mem_ctx, nir_src);
- nir_src_copy(dest->reg.indirect, src->reg.indirect, mem_ctx);
+ dest->reg.indirect = ralloc(instr, nir_src);
+ nir_src_copy(dest->reg.indirect, src->reg.indirect, instr);
} else {
dest->reg.indirect = NULL;
}
}
void
-nir_alu_src_copy(nir_alu_src *dest, const nir_alu_src *src, void *mem_ctx)
+nir_alu_src_copy(nir_alu_src *dest, const nir_alu_src *src,
+ nir_alu_instr *instr)
{
- nir_src_copy(&dest->src, &src->src, mem_ctx);
+ nir_src_copy(&dest->src, &src->src, &instr->instr);
dest->abs = src->abs;
dest->negate = src->negate;
for (unsigned i = 0; i < 4; i++)
}
void
-nir_alu_dest_copy(nir_alu_dest *dest, const nir_alu_dest *src, void *mem_ctx)
+nir_alu_dest_copy(nir_alu_dest *dest, const nir_alu_dest *src,
+ nir_alu_instr *instr)
{
- nir_dest_copy(&dest->dest, &src->dest, mem_ctx);
+ nir_dest_copy(&dest->dest, &src->dest, &instr->instr);
dest->write_mask = src->write_mask;
dest->saturate = src->saturate;
}
nir_foreach_use_safe(def, use_src) {
nir_instr *src_parent_instr = use_src->parent_instr;
list_del(&use_src->use_link);
- nir_src_copy(use_src, &new_src, mem_ctx);
+ nir_src_copy(use_src, &new_src, src_parent_instr);
src_add_all_uses(use_src, src_parent_instr, NULL);
}
nir_foreach_if_use_safe(def, use_src) {
nir_if *src_parent_if = use_src->parent_if;
list_del(&use_src->use_link);
- nir_src_copy(use_src, &new_src, mem_ctx);
+ nir_src_copy(use_src, &new_src, src_parent_if);
src_add_all_uses(use_src, NULL, src_parent_if);
}
}
return dest;
}
-void nir_src_copy(nir_src *dest, const nir_src *src, void *mem_ctx);
-void nir_dest_copy(nir_dest *dest, const nir_dest *src, void *mem_ctx);
+void nir_src_copy(nir_src *dest, const nir_src *src, void *instr_or_if);
+void nir_dest_copy(nir_dest *dest, const nir_dest *src, nir_instr *instr);
typedef struct {
nir_src src;
unsigned write_mask : 4; /* ignored if dest.is_ssa is true */
} nir_alu_dest;
-void nir_alu_src_copy(nir_alu_src *dest, const nir_alu_src *src, void *mem_ctx);
-void nir_alu_dest_copy(nir_alu_dest *dest, const nir_alu_dest *src,
- void *mem_ctx);
-
typedef enum {
nir_type_invalid = 0, /* Not a valid type */
nir_type_float,
nir_alu_src src[];
} nir_alu_instr;
+void nir_alu_src_copy(nir_alu_src *dest, const nir_alu_src *src,
+ nir_alu_instr *instr);
+void nir_alu_dest_copy(nir_alu_dest *dest, const nir_alu_dest *src,
+ nir_alu_instr *instr);
+
/* is this source channel used? */
static inline bool
nir_alu_instr_channel_used(nir_alu_instr *instr, unsigned src, unsigned channel)
assert(src.reg.reg->num_components >= dest_src.reg.reg->num_components);
nir_alu_instr *mov = nir_alu_instr_create(mem_ctx, nir_op_imov);
- nir_src_copy(&mov->src[0].src, &src, mem_ctx);
+ nir_src_copy(&mov->src[0].src, &src, mov);
mov->dest.dest = nir_dest_for_reg(dest_src.reg.reg);
mov->dest.write_mask = (1 << dest_src.reg.reg->num_components) - 1;
for (unsigned i = 0; i < num_components; i++) {
nir_alu_instr *chan = nir_alu_instr_create(mem_ctx, chan_op);
nir_alu_ssa_dest_init(chan, 1);
- nir_alu_src_copy(&chan->src[0], &instr->src[0], mem_ctx);
+ nir_alu_src_copy(&chan->src[0], &instr->src[0], chan);
chan->src[0].swizzle[0] = chan->src[0].swizzle[i];
if (nir_op_infos[chan_op].num_inputs > 1) {
assert(nir_op_infos[chan_op].num_inputs == 2);
- nir_alu_src_copy(&chan->src[1], &instr->src[1], mem_ctx);
+ nir_alu_src_copy(&chan->src[1], &instr->src[1], chan);
chan->src[1].swizzle[0] = chan->src[1].swizzle[i];
}
unsigned src_chan = (nir_op_infos[instr->op].input_sizes[i] == 1 ?
0 : chan);
- nir_alu_src_copy(&lower->src[i], &instr->src[i], mem_ctx);
+ nir_alu_src_copy(&lower->src[i], &instr->src[i], lower);
for (int j = 0; j < 4; j++)
lower->src[i].swizzle[j] = instr->src[i].swizzle[src_chan];
}
nir_alu_instr *mul = nir_alu_instr_create(mem_ctx, nir_op_imul);
nir_ssa_dest_init(&mul->instr, &mul->dest.dest, 1, NULL);
mul->dest.write_mask = 0x1;
- nir_src_copy(&mul->src[0].src, &deref_array->indirect, mem_ctx);
+ nir_src_copy(&mul->src[0].src, &deref_array->indirect, mul);
mul->src[1].src.is_ssa = true;
mul->src[1].src.ssa = &atomic_counter_size->def;
nir_instr_insert_before(&instr->instr, &mul->instr);
store->const_index[0] = offset;
- nir_src_copy(&store->src[0], &intrin->src[0], state->mem_ctx);
+ nir_src_copy(&store->src[0], &intrin->src[0], store);
if (has_indirect)
store->src[1] = indirect;
nir_alu_instr *add = nir_alu_instr_create(state->shader,
nir_op_iadd);
add->src[0].src = *src.reg.indirect;
- nir_src_copy(&add->src[1].src, &deref_array->indirect,
- state->shader);
+ nir_src_copy(&add->src[1].src, &deref_array->indirect, add);
add->dest.write_mask = 1;
nir_ssa_dest_init(&add->instr, &add->dest.dest, 1, NULL);
nir_instr_insert_before(instr, &add->instr);
nir_src_for_ssa(&mov->dest.dest.ssa),
state->shader);
} else {
- nir_dest_copy(&mov->dest.dest, &intrin->dest, state->shader);
+ nir_dest_copy(&mov->dest.dest, &intrin->dest, &mov->instr);
}
nir_instr_insert_before(&intrin->instr, &mov->instr);
&intrin->instr, state);
nir_alu_instr *mov = nir_alu_instr_create(state->shader, nir_op_imov);
- nir_src_copy(&mov->src[0].src, &intrin->src[0], state->shader);
+ nir_src_copy(&mov->src[0].src, &intrin->src[0], mov);
mov->dest.write_mask = (1 << intrin->num_components) - 1;
mov->dest.dest.is_ssa = false;
mov->dest.dest.reg.reg = reg_src.reg.reg;
assert(src_idx < nir_op_infos[vec->op].num_inputs);
nir_alu_instr *mov = nir_alu_instr_create(mem_ctx, nir_op_imov);
- nir_alu_src_copy(&mov->src[0], &vec->src[src_idx], mem_ctx);
- nir_alu_dest_copy(&mov->dest, &vec->dest, mem_ctx);
+ nir_alu_src_copy(&mov->src[0], &vec->src[src_idx], mov);
+ nir_alu_dest_copy(&mov->dest, &vec->dest, mov);
mov->dest.write_mask = (1u << start_channel);
mov->src[0].swizzle[start_channel] = vec->src[src_idx].swizzle[0];
for (unsigned j = 0; j < add->dest.dest.ssa.num_components; j++)
ffma->src[i].swizzle[j] = mul->src[i].swizzle[swizzle[j]];
}
- nir_alu_src_copy(&ffma->src[2], &add->src[1 - add_mul_src],
- state->mem_ctx);
+ nir_alu_src_copy(&ffma->src[2], &add->src[1 - add_mul_src], ffma);
assert(add->dest.dest.is_ssa);
nir_phi_instr *phi = nir_instr_as_phi(instr);
nir_alu_instr *sel = nir_alu_instr_create(state->mem_ctx, nir_op_bcsel);
- nir_src_copy(&sel->src[0].src, &if_stmt->condition, state->mem_ctx);
+ nir_src_copy(&sel->src[0].src, &if_stmt->condition, sel);
/* Splat the condition to all channels */
memset(sel->src[0].swizzle, 0, sizeof sel->src[0].swizzle);
assert(src->src.is_ssa);
unsigned idx = src->pred == then_block ? 1 : 2;
- nir_src_copy(&sel->src[idx].src, &src->src, state->mem_ctx);
+ nir_src_copy(&sel->src[idx].src, &src->src, sel);
}
nir_ssa_dest_init(&sel->instr, &sel->dest.dest,