soc_sdram: change l2_size checks order

diff --git a/litex/soc/integration/soc_sdram.py b/litex/soc/integration/soc_sdram.py
index a28b9bc37968c280fe99fa670c222bc02b70cff5..ae4455af594c25e05121b19cd1eb1a0b4f3c75bb 100644 (file)
--- a/litex/soc/integration/soc_sdram.py
+++ b/litex/soc/integration/soc_sdram.py
@@ -82,8 +82,8 @@ class SoCSDRAM(SoCCore):
                             geom_settings.colbits)*phy.settings.databits//8
         main_ram_size = min(main_ram_size, 0x20000000) # FIXME: limit to 512MB for now
 
-        l2_size = 2**int(log2(self.l2_size))             # Round to nearest power of 2
-        l2_size = max(l2_size, int(2*port.data_width/8)) # L2 has a minimal size, use it if lower
+        l2_size = max(self.l2_size, int(2*port.data_width/8)) # L2 has a minimal size, use it if lower
+        l2_size = 2**int(log2(l2_size))                       # Round to nearest power of 2
 
         # SoC <--> L2 Cache Wishbone interface -----------------------------------------------------
         wb_sdram = wishbone.Interface()