FRT[5:64] = selectconcat(WORD[2:32], z29)
# Denormalized Operand
- if e.value == 0 and m.value != 0:
+ if e.value == 0 and m.value != 0:
log ("denormalised")
sign = WORD[0]
exp = -126
WORD = SelectableInt(0, 32)
e = FRS[1:12]
- m = FRS[9:32]
+ m = FRS[12:64]
s = FRS[0]
log ("SINGLE", FRS)
#No Denormalization Required (includes Zero / Infinity / NaN)
if e.value > 896 or FRS[1:64].value == 0:
+ log("nodenorm", FRS[0:2].value, hex(FRS[5:35].value))
WORD[0:2] = FRS[0:2]
WORD[2:32] = FRS[5:35]
#Denormalization Required
- if e.value >= 874 and e.value <= 896:
+ if e.value >= 874 and e.value <= 896:
sign = FRS[0]
- exp = e - 1023
+ exp = e.value - 1023
frac = selectconcat(SelectableInt(1, 1), FRS[12:64])
+ log("exp, fract", exp, hex(frac.value))
# denormalize operand
- while exp.value < -126:
+ while exp < -126:
frac[0:53] = selectconcat(SelectableInt(0, 1), frac[0:52])
exp = exp + 1
WORD[0] = sign
log("qemu program", generator.binfile.name)
qemu = run_program(generator, initial_mem=mem,
bigendian=False, start_addr=initial_pc,
- continuous_run=False, initial_sprs=initial_sprs)
- if initial_regs is not None:
- for reg, val in enumerate(initial_regs):
- qemu.set_gpr(reg, val)
- if initial_fprs is not None:
- for fpr, val in enumerate(initial_fprs):
- qemu.set_fpr(fpr, val)
+ continuous_run=False, initial_sprs=initial_sprs,
+ initial_regs=initial_regs, initial_fprs=initial_fprs)
for reg, val in qemu._get_registers().items():
- print (reg, hex(val))
+ log ("qemu reg", reg, hex(val))
m = Module()
comb = m.d.comb
qmem = qemu.get_mem(offs, length)
for i, mem in enumerate(qmem):
log(hex(offs+i*8), hex(mem))
+ for reg, val in qemu._get_registers().items():
+ log ("qemu reg", reg, hex(val))
# cleanup
if qemu:
return x
+def find_uint128(val):
+ print (val[1:])
+ assert val[1:].startswith('uint128 =')
+ val = val.split("=")[1]
+ val = val.split(',')[0].strip()
+ val = int(val, 0)
+ return swap_order(val, 16)
+
+
class QemuController:
def __init__(self, kernel, bigendian):
if bigendian:
for rdict in rlist:
regnum = int(rdict['number'])
regval = rdict['value']
+ print ("reg get", regnum, rdict)
if regval.startswith("{"): # TODO, VSX
- continue
- self._reg_cache["x %d" % regnum] = int(regval, 0)
+ regval = find_uint128(regval)
+ else:
+ regval = int(regval, 0)
+ self._reg_cache["x %d" % regnum] = regval
return self._reg_cache
def _get_register(self, fmt):
def set_fpr(self, reg, val):
self._rcache_trash('x %d' % (reg+32))
- self.gdb_eval('$fp%d=%d' % (reg, val))
+ self._rcache_trash('x %d' % (reg+471))
+ # grr, fp set cannot enter raw data
+ #val = swap_order(val, 8)
+ #val = 1<<31
+ valhi = (val >> 32) & 0xffffffff
+ vallo = val & 0xffffffff
+ res = self.gdb_eval('$vs%d.v4_int32={0,0,0x%x,0x%x}' % \
+ (reg, vallo, valhi))
+ #res = self.gdb_eval('$fp%d=1.0')
+ #res = self.gdb_eval('$vs%d.uint128=0x%x' % \
+ # (reg, val))
+ print ("set fpr", reg, hex(val), res)
+ print ("get fpr", hex(self.get_fpr(reg)))
def set_pc(self, pc):
self._rcache_trash('x 64')
def run_program(program, initial_mem=None, extra_break_addr=None,
bigendian=False, start_addr=0x20000000, init_endian=True,
- continuous_run=True, initial_sprs=None):
+ continuous_run=True, initial_sprs=None,
+ initial_regs=None, initial_fprs=None):
q = QemuController(program.binfile.name, bigendian)
q.connect()
q.set_endian(init_endian) # easier to set variables this way
msr = msr & ((1 << 53)-1)
else:
msr |= (1 << 13)
+ #msr = 0x4000000000009
+
q.set_msr(msr)
print("msr set to", hex(msr), bin(msr))
+ # upload regs
+ if initial_regs:
+ for i, reg in enumerate(initial_regs):
+ if reg != 0:
+ q.set_gpr(i, reg)
+ if initial_fprs:
+ if isinstance(initial_fprs, dict):
+ for i, reg in initial_fprs.items():
+ q.set_fpr(i, reg)
+ else:
+ for i, reg in enumerate(initial_fprs):
+ if reg != 0:
+ q.set_fpr(i, reg)
+
# can't do many of these - lr, ctr, etc. etc. later, just LR for now
if initial_sprs:
lr = initial_sprs.get('lr', None)
projects / openpower-isa.git / commitdiff