cpu: add `reserved_interrupts` property

diff --git a/litex/soc/cores/cpu/lm32/core.py b/litex/soc/cores/cpu/lm32/core.py
index 70d202ab6d662415d3122004b5f3078b247ef74e..7b5d92729ca2d12a85142d9242642724de2e942f 100644 (file)
--- a/litex/soc/cores/cpu/lm32/core.py
+++ b/litex/soc/cores/cpu/lm32/core.py
@@ -33,6 +33,10 @@ class LM32(Module):
     def linker_output_format(self):
         return "elf32-lm32"
 
+    @property
+    def reserved_interrupts(self):
+        return {}
+
     def __init__(self, platform, eba_reset, variant="standard"):
         assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
         self.platform = platform

diff --git a/litex/soc/cores/cpu/minerva/core.py b/litex/soc/cores/cpu/minerva/core.py
index 3c3c41d652adeefaecb24a594d0aa5d9a2ee21e0..73279abae786337fd9e23840528aa1b41fd42b72 100644 (file)
--- a/litex/soc/cores/cpu/minerva/core.py
+++ b/litex/soc/cores/cpu/minerva/core.py
@@ -31,6 +31,10 @@ class Minerva(Module):
     def linker_output_format(self):
         return "elf32-littleriscv"
 
+    @property
+    def reserved_interrupts(self):
+        return {}
+
     def __init__(self, platform, cpu_reset_address, variant="standard"):
         assert variant is "standard", "Unsupported variant %s" % variant
         self.platform = platform

diff --git a/litex/soc/cores/cpu/mor1kx/core.py b/litex/soc/cores/cpu/mor1kx/core.py
index bb46a6a6c7b59ef32c19f533ad9837b8e68f6019..82926e060bac8f202b7ef4a74b7c76303c55d26e 100644 (file)
--- a/litex/soc/cores/cpu/mor1kx/core.py
+++ b/litex/soc/cores/cpu/mor1kx/core.py
@@ -47,6 +47,10 @@ class MOR1KX(Module):
     def linker_output_format(self):
         return "elf32-or1k"
 
+    @property
+    def reserved_interrupts(self):
+        return { "nmi": 0 }
+
     def __init__(self, platform, reset_pc, variant="standard"):
         assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
         self.platform = platform

diff --git a/litex/soc/cores/cpu/picorv32/core.py b/litex/soc/cores/cpu/picorv32/core.py
index 846ab07d745ade5021a99c8563e528376e739152..332b768e12a44b93f3c996270061e0fb08e6eb43 100644 (file)
--- a/litex/soc/cores/cpu/picorv32/core.py
+++ b/litex/soc/cores/cpu/picorv32/core.py
@@ -45,6 +45,10 @@ class PicoRV32(Module):
     def linker_output_format(self):
         return "elf32-littleriscv"
 
+    @property
+    def reserved_interrupts(self):
+        return { "picorv32_timer": 0, "picorv32_ebreak_ecall_illegal": 1, "picorv32_bus_error": 2 }
+
     def __init__(self, platform, progaddr_reset, variant="standard"):
         assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
         self.platform = platform

diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py
index de30de8d5423c414740c86e5ac31727bfe9448e8..3d904f8687d8973218e83d9815bfa8583c663ad0 100644 (file)
--- a/litex/soc/cores/cpu/vexriscv/core.py
+++ b/litex/soc/cores/cpu/vexriscv/core.py
@@ -81,6 +81,10 @@ class VexRiscv(Module, AutoCSR):
     def linker_output_format(self):
         return "elf32-littleriscv"
 
+    @property
+    def reserved_interrupts(self):
+        return {}
+
     def __init__(self, platform, cpu_reset_address, variant="standard"):
         assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
         self.platform = platform