.*: +file format .*arm.*
Disassembly of section .text:
-0+ <.*> 824ff203 subhi pc, pc, #805306368 ; 0x30000000
+0+ <.*> 824ff203 subhi pc, pc, #805306368 @ 0x30000000
Disassembly of section .text:
...
0+2000 <.*> e24f0008 sub r0, pc, #8
-0+2004 <.*> e2400c20 sub r0, r0, #32, 24 ; 0x2000
+0+2004 <.*> e2400c20 sub r0, r0, #32, 24 @ 0x2000
0+2008 <.*> e28f0020 add r0, pc, #32
-0+200c <.*> e2800c20 add r0, r0, #32, 24 ; 0x2000
+0+200c <.*> e2800c20 add r0, r0, #32, 24 @ 0x2000
0+2010 <.*> e24f0018 sub r0, pc, #24
-0+2014 <.*> e1a00000 nop ; \(mov r0, r0\)
+0+2014 <.*> e1a00000 nop @ \(mov r0, r0\)
0+2018 <.*> e28f0008 add r0, pc, #8
-0+201c <.*> e1a00000 nop ; \(mov r0, r0\)
+0+201c <.*> e1a00000 nop @ \(mov r0, r0\)
0+2020 <.*> 028f0000 addeq r0, pc, #0
-0+2024 <.*> e1a00000 nop ; \(mov r0, r0\)
-0+2028 <.*> e24f0030 sub r0, pc, #48 ; 0x30
-0+202c <.*> e2400c20 sub r0, r0, #32, 24 ; 0x2000
-0+2030 <.*> e28f0c21 add r0, pc, #8448 ; 0x2100
-0+2034 <.*> e1a00000 nop ; \(mov r0, r0\)
+0+2024 <.*> e1a00000 nop @ \(mov r0, r0\)
+0+2028 <.*> e24f0030 sub r0, pc, #48 @ 0x30
+0+202c <.*> e2400c20 sub r0, r0, #32, 24 @ 0x2000
+0+2030 <.*> e28f0c21 add r0, pc, #8448 @ 0x2100
+0+2034 <.*> e1a00000 nop @ \(mov r0, r0\)
...
-0+4030 <.*> e28fec01 add lr, pc, #256 ; 0x100
+0+4030 <.*> e28fec01 add lr, pc, #256 @ 0x100
...
...
.*: R_ARM_V4BX.*
0+04 <[^>]+> 012fff11 ? bxeq r1
.*: R_ARM_V4BX.*
-0+08 <[^>]+> e15f30b8 ? ldrh r3, \[pc, #-8\] ; 0+08 <[^>]+>
+0+08 <[^>]+> e15f30b8 ? ldrh r3, \[pc, #-8\] @ 0+08 <[^>]+>
0+0c <[^>]+> e1d540f0 ? ldrsh r4, \[r5\]
0+10 <[^>]+> e19140d3 ? ldrsb r4, \[r1, r3\]
0+14 <[^>]+> e1b410f4 ? ldrsh r1, \[r4, r4\]!
0+24 <[^>]+> e1d32fdf ? ldrsb r2, \[r3, #255\].*
0+28 <[^>]+> e1541ffa ? ldrsh r1, \[r4, #-250\].*
0+2c <[^>]+> e1d51fd0 ? ldrsb r1, \[r5, #240\].*
-0+30 <[^>]+> e1cf23b0 ? strh r2, \[pc, #48\] ; 0+68 <[^>]+>
+0+30 <[^>]+> e1cf23b0 ? strh r2, \[pc, #48\] @ 0+68 <[^>]+>
0+34 <[^>]+> 11c330b0 ? strhne r3, \[r3\]
0+38 <[^>]+> e328f002 ? msr CPSR_f, #2
0+3c <[^>]+> e121f003 ? msr CPSR_c, r3
0+5c <[^>]+> e164f00a ? msr SPSR_s, sl
0+60 <[^>]+> e168f00b ? msr SPSR_f, fp
0+64 <[^>]+> e169f00c ? msr SPSR_fc, ip
-0+68 <[^>]+> e1a00000 ? nop ; \(mov r0, r0\)
-0+6c <[^>]+> e1a00000 ? nop ; \(mov r0, r0\)
+0+68 <[^>]+> e1a00000 ? nop @ \(mov r0, r0\)
+0+6c <[^>]+> e1a00000 ? nop @ \(mov r0, r0\)
Disassembly of section .text:
0+00 <[^>]+> e12fff10 ? bx r0
0+04 <[^>]+> 012fff11 ? bxeq r1
-0+08 <[^>]+> e15f30b8 ? ldrh r3, \[pc, #-8\] ; 0+08 <[^>]+>
+0+08 <[^>]+> e15f30b8 ? ldrh r3, \[pc, #-8\] @ 0+08 <[^>]+>
0+0c <[^>]+> e1d540f0 ? ldrsh r4, \[r5\]
0+10 <[^>]+> e19140d3 ? ldrsb r4, \[r1, r3\]
0+14 <[^>]+> e1b410f4 ? ldrsh r1, \[r4, r4\]!
0+24 <[^>]+> e1d32fdf ? ldrsb r2, \[r3, #255\].*
0+28 <[^>]+> e1541ffa ? ldrsh r1, \[r4, #-250\].*
0+2c <[^>]+> e1d51fd0 ? ldrsb r1, \[r5, #240\].*
-0+30 <[^>]+> e1cf23b0 ? strh r2, \[pc, #48\] ; 0+68 <[^>]+>
+0+30 <[^>]+> e1cf23b0 ? strh r2, \[pc, #48\] @ 0+68 <[^>]+>
0+34 <[^>]+> 11c330b0 ? strhne r3, \[r3\]
0+38 <[^>]+> e328f002 ? msr CPSR_f, #2
0+3c <[^>]+> e121f003 ? msr CPSR_c, r3
0+5c <[^>]+> e164f00a ? msr SPSR_s, sl
0+60 <[^>]+> e168f00b ? msr SPSR_f, fp
0+64 <[^>]+> e169f00c ? msr SPSR_fc, ip
-0+68 <[^>]+> e1a00000 ? nop ; \(mov r0, r0\)
-0+6c <[^>]+> e1a00000 ? nop ; \(mov r0, r0\)
+0+68 <[^>]+> e1a00000 ? nop @ \(mov r0, r0\)
+0+6c <[^>]+> e1a00000 ? nop @ \(mov r0, r0\)
0+050 <[^>]*> f995 f000 pli \[r5\]
0+054 <[^>]*> f995 ffff pli \[r5, #4095\].*
0+058 <[^>]*> f915 fcff pli \[r5, #-255\]
-0+05c <[^>]*> f99f ffff pli \[pc, #4095\] ; 0+0105f <[^>]*>
-0+060 <[^>]*> f91f ffff pli \[pc, #-4095\] ; f+ff065 <[^>]*>
+0+05c <[^>]*> f99f ffff pli \[pc, #4095\] @ 0+0105f <[^>]*>
+0+060 <[^>]*> f91f ffff pli \[pc, #-4095\] @ f+ff065 <[^>]*>
0+064 <[^>]*> f3af 80f0 dbg #0
0+068 <[^>]*> f3af 80ff dbg #15
0+06c <[^>]*> f3bf 8f5f dmb sy
0[0-9a-f]+ <[^>]+> f590f000 pldw \[r0\]
0[0-9a-f]+ <[^>]+> f59ef000 pldw \[lr\]
0[0-9a-f]+ <[^>]+> f591f000 pldw \[r1\]
-0[0-9a-f]+ <[^>]+> f590ffff pldw \[r0, #4095\] ; 0xfff
-0[0-9a-f]+ <[^>]+> f510ffff pldw \[r0, #-4095\] ; 0xfffff001
+0[0-9a-f]+ <[^>]+> f590ffff pldw \[r0, #4095\] @ 0xfff
+0[0-9a-f]+ <[^>]+> f510ffff pldw \[r0, #-4095\] @ 0xfffff001
0[0-9a-f]+ <[^>]+> f790f000 pldw \[r0, r0\]
0[0-9a-f]+ <[^>]+> f791f000 pldw \[r1, r0\]
0[0-9a-f]+ <[^>]+> f79ef000 pldw \[lr, r0\]
0[0-9a-f]+ <[^>]+> f8b0 f000 pldw \[r0\]
0[0-9a-f]+ <[^>]+> f8be f000 pldw \[lr\]
0[0-9a-f]+ <[^>]+> f8b1 f000 pldw \[r1\]
-0[0-9a-f]+ <[^>]+> f8b0 ffff pldw \[r0, #4095\] ; 0xfff
+0[0-9a-f]+ <[^>]+> f8b0 ffff pldw \[r0, #4095\] @ 0xfff
0[0-9a-f]+ <[^>]+> f830 fcff pldw \[r0, #-255\]
0[0-9a-f]+ <[^>]+> f830 f000 pldw \[r0, r0\]
0[0-9a-f]+ <[^>]+> f831 f000 pldw \[r1, r0\]
0[0-9a-f]+ <[^>]+> f590f000 pldw \[r0\]
0[0-9a-f]+ <[^>]+> f59ef000 pldw \[lr\]
0[0-9a-f]+ <[^>]+> f591f000 pldw \[r1\]
-0[0-9a-f]+ <[^>]+> f590ffff pldw \[r0, #4095\] ; 0xfff
-0[0-9a-f]+ <[^>]+> f510ffff pldw \[r0, #-4095\] ; 0xfffff001
+0[0-9a-f]+ <[^>]+> f590ffff pldw \[r0, #4095\] @ 0xfff
+0[0-9a-f]+ <[^>]+> f510ffff pldw \[r0, #-4095\] @ 0xfffff001
0[0-9a-f]+ <[^>]+> f790f000 pldw \[r0, r0\]
0[0-9a-f]+ <[^>]+> f791f000 pldw \[r1, r0\]
0[0-9a-f]+ <[^>]+> f79ef000 pldw \[lr, r0\]
0[0-9a-f]+ <[^>]+> f8b0 f000 pldw \[r0\]
0[0-9a-f]+ <[^>]+> f8be f000 pldw \[lr\]
0[0-9a-f]+ <[^>]+> f8b1 f000 pldw \[r1\]
-0[0-9a-f]+ <[^>]+> f8b0 ffff pldw \[r0, #4095\] ; 0xfff
+0[0-9a-f]+ <[^>]+> f8b0 ffff pldw \[r0, #4095\] @ 0xfff
0[0-9a-f]+ <[^>]+> f830 fcff pldw \[r0, #-255\]
0[0-9a-f]+ <[^>]+> f830 f000 pldw \[r0, r0\]
0[0-9a-f]+ <[^>]+> f831 f000 pldw \[r1, r0\]
0+78 <[^>]+> e3400000 movt r0, #0
0+7c <[^>]+> 13000000 movwne r0, #0
0+80 <[^>]+> e3009000 movw r9, #0
-0+84 <[^>]+> e3000999 movw r0, #2457 ; 0x999
-0+88 <[^>]+> e3090000 movw r0, #36864 ; 0x9000
+0+84 <[^>]+> e3000999 movw r0, #2457 @ 0x999
+0+88 <[^>]+> e3090000 movw r0, #36864 @ 0x9000
0+8c <[^>]+> e0f900b0 ldrht r0, \[r9\], #0
0+90 <[^>]+> e0f900f0 ldrsht r0, \[r9\], #0
0+94 <[^>]+> e0f900d0 ldrsbt r0, \[r9\], #0
0+ac <[^>]+> e07099b9 ldrht r9, \[r0\], #-153.*
0+b0 <[^>]+> 10b090b9 ldrhtne r9, \[r0\], r9
0+b4 <[^>]+> 103090b9 ldrhtne r9, \[r0\], -r9
-0+b8 <[^>]+> 10f099b9 ldrhtne r9, \[r0\], #153 ; 0x99
-0+bc <[^>]+> 107099b9 ldrhtne r9, \[r0\], #-153 ; 0xffffff67
+0+b8 <[^>]+> 10f099b9 ldrhtne r9, \[r0\], #153 @ 0x99
+0+bc <[^>]+> 107099b9 ldrhtne r9, \[r0\], #-153 @ 0xffffff67
0+c0 <[^>]+> e02100b2 strht r0, \[r1\], -r2
0+c4 <[^>]+> 102100b2 strhtne r0, \[r1\], -r2
0+c8 <[^>]+> e0a100b2 strht r0, \[r1\], r2
0+d4 <[^>]+> e06100b2 strht r0, \[r1\], #-2
0+d8 <[^>]+> 10e100b2 strhtne r0, \[r1\], #2
0+dc <[^>]+> 106100b2 strhtne r0, \[r1\], #-2
-0+e0 <[^>]+> e3009999 movw r9, #2457 ; 0x999
+0+e0 <[^>]+> e3009999 movw r9, #2457 @ 0x999
0+.* <[^>]*> e849 f800 tt r8, r9
0+.* <[^>]*> e841 f040 ttt r0, r1
0+.* <[^>]*> e849 f840 ttt r8, r9
-0+.* <[^>]*> f24f 1023 movw r0, #61731 ; 0xf123
-0+.* <[^>]*> f24f 1823 movw r8, #61731 ; 0xf123
-0+.* <[^>]*> f24f 1823 movw r8, #61731 ; 0xf123
-0+.* <[^>]*> f24f 1823 movw r8, #61731 ; 0xf123
-0+.* <[^>]*> f2cf 1023 movt r0, #61731 ; 0xf123
-0+.* <[^>]*> f2cf 1823 movt r8, #61731 ; 0xf123
+0+.* <[^>]*> f24f 1023 movw r0, #61731 @ 0xf123
+0+.* <[^>]*> f24f 1823 movw r8, #61731 @ 0xf123
+0+.* <[^>]*> f24f 1823 movw r8, #61731 @ 0xf123
+0+.* <[^>]*> f24f 1823 movw r8, #61731 @ 0xf123
+0+.* <[^>]*> f2cf 1023 movt r0, #61731 @ 0xf123
+0+.* <[^>]*> f2cf 1823 movt r8, #61731 @ 0xf123
0+.* <[^>]*> b154 cbz r4, 0+.* <[^>]*>
0+.* <[^>]*> b94c cbnz r4, 0+.* <[^>]*>
0+.* <[^>]*> f000 b808 b.w 0+.* <[^>]*>
0+.* <[^>]*> e849 f800 tt r8, r9
0+.* <[^>]*> e841 f040 ttt r0, r1
0+.* <[^>]*> e849 f840 ttt r8, r9
-0+.* <[^>]*> f24f 1023 movw r0, #61731 ; 0xf123
-0+.* <[^>]*> f24f 1823 movw r8, #61731 ; 0xf123
-0+.* <[^>]*> f24f 1823 movw r8, #61731 ; 0xf123
-0+.* <[^>]*> f24f 1823 movw r8, #61731 ; 0xf123
-0+.* <[^>]*> f2cf 1023 movt r0, #61731 ; 0xf123
-0+.* <[^>]*> f2cf 1823 movt r8, #61731 ; 0xf123
+0+.* <[^>]*> f24f 1023 movw r0, #61731 @ 0xf123
+0+.* <[^>]*> f24f 1823 movw r8, #61731 @ 0xf123
+0+.* <[^>]*> f24f 1823 movw r8, #61731 @ 0xf123
+0+.* <[^>]*> f24f 1823 movw r8, #61731 @ 0xf123
+0+.* <[^>]*> f2cf 1023 movt r0, #61731 @ 0xf123
+0+.* <[^>]*> f2cf 1823 movt r8, #61731 @ 0xf123
0+.* <[^>]*> b154 cbz r4, 0+.* <[^>]*>
0+.* <[^>]*> b94c cbnz r4, 0+.* <[^>]*>
0+.* <[^>]*> f000 b808 b.w 0+.* <[^>]*>
0+.* <[^>]*> e849 f800 tt r8, r9
0+.* <[^>]*> e841 f040 ttt r0, r1
0+.* <[^>]*> e849 f840 ttt r8, r9
-0+.* <[^>]*> f24f 1023 movw r0, #61731 ; 0xf123
-0+.* <[^>]*> f24f 1823 movw r8, #61731 ; 0xf123
-0+.* <[^>]*> f24f 1823 movw r8, #61731 ; 0xf123
-0+.* <[^>]*> f24f 1823 movw r8, #61731 ; 0xf123
-0+.* <[^>]*> f2cf 1023 movt r0, #61731 ; 0xf123
-0+.* <[^>]*> f2cf 1823 movt r8, #61731 ; 0xf123
+0+.* <[^>]*> f24f 1023 movw r0, #61731 @ 0xf123
+0+.* <[^>]*> f24f 1823 movw r8, #61731 @ 0xf123
+0+.* <[^>]*> f24f 1823 movw r8, #61731 @ 0xf123
+0+.* <[^>]*> f24f 1823 movw r8, #61731 @ 0xf123
+0+.* <[^>]*> f2cf 1023 movt r0, #61731 @ 0xf123
+0+.* <[^>]*> f2cf 1823 movt r8, #61731 @ 0xf123
0+.* <[^>]*> b154 cbz r4, 0+.* <[^>]*>
0+.* <[^>]*> b94c cbnz r4, 0+.* <[^>]*>
0+.* <[^>]*> f000 b808 b.w 0+.* <[^>]*>
0+0 <[^>]*> e1080091 ? swp r0, r1, \[r8\]
0+4 <[^>]*> e1423093 ? swpb r3, r3, \[r2\]
0+8 <[^>]*> a1454091 ? swpbge r4, r1, \[r5\]
-0+c <[^>]*> e1a00000 ? nop ; \(mov r0, r0\)
+0+c <[^>]*> e1a00000 ? nop @ \(mov r0, r0\)
0+00 <[^>]+> e10f8000 ? mrs r8, CPSR
0+04 <[^>]+> e14f2000 ? mrs r2, SPSR
0+08 <[^>]+> e129f001 ? msr CPSR_fc, r1
-0+0c <[^>]+> 1328f20f ? msrne CPSR_f, #-268435456 ; 0xf0000000
+0+0c <[^>]+> 1328f20f ? msrne CPSR_f, #-268435456 @ 0xf0000000
0+10 <[^>]+> e168f008 ? msr SPSR_f, r8
0+14 <[^>]+> e169f009 ? msr SPSR_fc, r9
0+18 <[^>]+> e10f8000 ? mrs r8, CPSR
0+1c <[^>]+> e14f2000 ? mrs r2, SPSR
0+20 <[^>]+> e129f001 ? msr CPSR_fc, r1
-0+24 <[^>]+> 1328f20f ? msrne CPSR_f, #-268435456 ; 0xf0000000
+0+24 <[^>]+> 1328f20f ? msrne CPSR_f, #-268435456 @ 0xf0000000
0+28 <[^>]+> e168f008 ? msr SPSR_f, r8
0+2c <[^>]+> e169f009 ? msr SPSR_fc, r9
0+18 <[^>]+> 00b92994 ? umlalseq r2, r9, r4, r9
0+1c <[^>]+> a0eaee98 ? smlalge lr, sl, r8, lr
0+20 <[^>]+> e322f000 ? msr CPSR_x, #0
-0+24 <[^>]+> e1a00000 ? nop ; \(mov r0, r0\)
-0+28 <[^>]+> e1a00000 ? nop ; \(mov r0, r0\)
-0+2c <[^>]+> e1a00000 ? nop ; \(mov r0, r0\)
+0+24 <[^>]+> e1a00000 ? nop @ \(mov r0, r0\)
+0+28 <[^>]+> e1a00000 ? nop @ \(mov r0, r0\)
+0+2c <[^>]+> e1a00000 ? nop @ \(mov r0, r0\)
0+14 <[^>]*> e1f100bc ? ldrh r0, \[r1, #12\]!
0+18 <[^>]*> e15100bc ? ldrh r0, \[r1, #-12\]
0+1c <[^>]*> e09100b2 ? ldrh r0, \[r1\], r2
-0+20 <[^>]*> e3a00cff ? mov r0, #65280 ; 0xff00
-0+24 <[^>]*> e1df0bb4 ? ldrh r0, \[pc, #180\] ; 0+e0 <[^>]*>
-0+28 <[^>]*> e1df0abc ? ldrh r0, \[pc, #172\] ; 0+dc <[^>]*>
+0+20 <[^>]*> e3a00cff ? mov r0, #65280 @ 0xff00
+0+24 <[^>]*> e1df0bb4 ? ldrh r0, \[pc, #180\] @ 0+e0 <[^>]*>
+0+28 <[^>]*> e1df0abc ? ldrh r0, \[pc, #172\] @ 0+dc <[^>]*>
0+2c <[^>]*> e1c100b0 ? strh r0, \[r1\]
0+30 <[^>]*> e1e100b0 ? strh r0, \[r1, #0\]!
0+34 <[^>]*> e18100b2 ? strh r0, \[r1, r2\]
0+40 <[^>]*> e1e100bc ? strh r0, \[r1, #12\]!
0+44 <[^>]*> e14100bc ? strh r0, \[r1, #-12\]
0+48 <[^>]*> e08100b2 ? strh r0, \[r1\], r2
-0+4c <[^>]*> e1cf08b8 ? strh r0, \[pc, #136\] ; 0+dc <[^>]*>
+0+4c <[^>]*> e1cf08b8 ? strh r0, \[pc, #136\] @ 0+dc <[^>]*>
0+50 <[^>]*> e1d100d0 ? ldrsb r0, \[r1\]
0+54 <[^>]*> e1f100d0 ? ldrsb r0, \[r1, #0\]!
0+58 <[^>]*> e19100d2 ? ldrsb r0, \[r1, r2\]
0+64 <[^>]*> e1f100dc ? ldrsb r0, \[r1, #12\]!
0+68 <[^>]*> e15100dc ? ldrsb r0, \[r1, #-12\]
0+6c <[^>]*> e09100d2 ? ldrsb r0, \[r1\], r2
-0+70 <[^>]*> e3a000de ? mov r0, #222 ; 0xde
-0+74 <[^>]*> e1df06d0 ? ldrsb r0, \[pc, #96\] ; 0+dc <[^>]*>
+0+70 <[^>]*> e3a000de ? mov r0, #222 @ 0xde
+0+74 <[^>]*> e1df06d0 ? ldrsb r0, \[pc, #96\] @ 0+dc <[^>]*>
0+78 <[^>]*> e1d100f0 ? ldrsh r0, \[r1\]
0+7c <[^>]*> e1f100f0 ? ldrsh r0, \[r1, #0\]!
0+80 <[^>]*> e19100f2 ? ldrsh r0, \[r1, r2\]
0+8c <[^>]*> e1f100fc ? ldrsh r0, \[r1, #12\]!
0+90 <[^>]*> e15100fc ? ldrsh r0, \[r1, #-12\]
0+94 <[^>]*> e09100f2 ? ldrsh r0, \[r1\], r2
-0+98 <[^>]*> e3a00cff ? mov r0, #65280 ; 0xff00
-0+9c <[^>]*> e1df03fc ? ldrsh r0, \[pc, #60\] ; 0+e0 <[^>]*>
-0+a0 <[^>]*> e1df03f4 ? ldrsh r0, \[pc, #52\] ; 0+dc <[^>]*>
+0+98 <[^>]*> e3a00cff ? mov r0, #65280 @ 0xff00
+0+9c <[^>]*> e1df03fc ? ldrsh r0, \[pc, #60\] @ 0+e0 <[^>]*>
+0+a0 <[^>]*> e1df03f4 ? ldrsh r0, \[pc, #52\] @ 0+dc <[^>]*>
0+a4 <[^>]*> e19100b2 ? ldrh r0, \[r1, r2\]
0+a8 <[^>]*> 119100b2 ? ldrhne r0, \[r1, r2\]
0+ac <[^>]*> 819100b2 ? ldrhhi r0, \[r1, r2\]
0+c8 <[^>]*> 119100d2 ? ldrsbne r0, \[r1, r2\]
0+cc <[^>]*> 819100d2 ? ldrsbhi r0, \[r1, r2\]
0+d0 <[^>]*> b19100d2 ? ldrsblt r0, \[r1, r2\]
-0+d4 <[^>]*> e1df00f4 ? ldrsh r0, \[pc, #4\] ; 0+e0 <[^>]*>
-0+d8 <[^>]*> e1df00f4 ? ldrsh r0, \[pc, #4\] ; 0+e4 <[^>]*>
+0+d4 <[^>]*> e1df00f4 ? ldrsh r0, \[pc, #4\] @ 0+e0 <[^>]*>
+0+d8 <[^>]*> e1df00f4 ? ldrsh r0, \[pc, #4\] @ 0+e4 <[^>]*>
0+dc <[^>]*> 00000000 ? .*
[ ]*dc:.*fred
0+e0 <[^>]*> 0000c0de ? .*
0+e4 <[^>]*> 0000dead ? .*
-0+e8 <[^>]*> e1a00000 ? nop[ ]+; \(mov r0, r0\)
-0+ec <[^>]*> e1a00000 ? nop[ ]+; \(mov r0, r0\)
+0+e8 <[^>]*> e1a00000 ? nop[ ]+@ \(mov r0, r0\)
+0+ec <[^>]*> e1a00000 ? nop[ ]+@ \(mov r0, r0\)
0+74 <[^>]*> e1700000 ? cmn r0, r0
0+78 <[^>]*> e1700000 ? cmn r0, r0
0+7c <[^>]*> e170f000 ? cmnp r0, r0
-0+80 <[^>]*> e1a00000 ? nop[\s]+; \(mov r0, r0\)
+0+80 <[^>]*> e1a00000 ? nop[\s]+@ \(mov r0, r0\)
0+84 <[^>]*> e1b00000 ? movs r0, r0
0+88 <[^>]*> e1e00000 ? mvn r0, r0
0+8c <[^>]*> e1f00000 ? mvns r0, r0
0+e8 <[^>]*> e8100001 ? ldmda r0, {r0}
0+ec <[^>]*> e9100001 ? ldmdb r0, {r0}
0+f0 <[^>]*> e9900001 ? ldmib r0, {r0}
-0+f4 <[^>]*> e1a00000 ? nop[\s]+; \(mov r0, r0\)
-0+f8 <[^>]*> e1a00000 ? nop[\s]+; \(mov r0, r0\)
-0+fc <[^>]*> e1a00000 ? nop[\s]+; \(mov r0, r0\)
+0+f4 <[^>]*> e1a00000 ? nop[\s]+@ \(mov r0, r0\)
+0+f8 <[^>]*> e1a00000 ? nop[\s]+@ \(mov r0, r0\)
+0+fc <[^>]*> e1a00000 ? nop[\s]+@ \(mov r0, r0\)
Disassembly of section .text:
0[0-9a-f]+ <[^>]+> e1400070 hvc 0
-0[0-9a-f]+ <[^>]+> e14fff7f hvc 65535 ; 0xffff
+0[0-9a-f]+ <[^>]+> e14fff7f hvc 65535 @ 0xffff
0[0-9a-f]+ <[^>]+> e160006e eret
0[0-9a-f]+ <[^>]+> e1001200 mrs r1, R8_usr
0[0-9a-f]+ <[^>]+> e1011200 mrs r1, R9_usr
0[0-9a-f]+ <[^>]+> e12ef301 msr ELR_hyp, r1
0[0-9a-f]+ <[^>]+> e16ef301 msr SPSR_hyp, r1
0[0-9a-f]+ <[^>]+> f7e0 8000 hvc #0
-0[0-9a-f]+ <[^>]+> f7ef 8fff hvc #65535 ; 0xffff
+0[0-9a-f]+ <[^>]+> f7ef 8fff hvc #65535 @ 0xffff
0[0-9a-f]+ <[^>]+> f3de 8f00 subs pc, lr, #0
0[0-9a-f]+ <[^>]+> f3e0 8120 mrs r1, R8_usr
0[0-9a-f]+ <[^>]+> f3e1 8120 mrs r1, R9_usr
00000000 <label-0xc>:
0: ee001910 vmov.f16 s0, r1
4: ee100990 vmov.f16 r0, s1
- 8: eeb00900 vmov.f16 s0, #0 ; 0x40000000 2.0
+ 8: eeb00900 vmov.f16 s0, #0 @ 0x40000000 2.0
0000000c <label>:
c: 00000ffe .word 0x00000ffe
- 10: ed5f1906 vldr.16 s3, \[pc, #-12\] ; c <label>
- 14: ed1f3902 vldr.16 s6, \[pc, #-4\] ; 18 <label\+0xc>
- 18: eddf1902 vldr.16 s3, \[pc, #4\] ; 24 <label\+0x18>
+ 10: ed5f1906 vldr.16 s3, \[pc, #-12\] @ c <label>
+ 14: ed1f3902 vldr.16 s6, \[pc, #-4\] @ 18 <label\+0xc>
+ 18: eddf1902 vldr.16 s3, \[pc, #4\] @ 24 <label\+0x18>
1c: edd00902 vldr.16 s1, \[r0, #4\]
20: ed101902 vldr.16 s2, \[r0, #-4\]
24: ed803902 vstr.16 s6, \[r0, #4\]
00000000 <label-0xc>:
0: ee00 1910 vmov.f16 s0, r1
4: ee10 0990 vmov.f16 r0, s1
- 8: eeb0 0900 vmov.f16 s0, #0 ; 0x40000000 2.0
+ 8: eeb0 0900 vmov.f16 s0, #0 @ 0x40000000 2.0
0000000c <label>:
c: 00000ffe .word 0x00000ffe
- 10: ed5f 1904 vldr.16 s3, \[pc, #-8\] ; c <label>
- 14: ed1f 3902 vldr.16 s6, \[pc, #-4\] ; 14 <label\+0x8>
- 18: eddf 1902 vldr.16 s3, \[pc, #4\] ; 20 <label\+0x14>
+ 10: ed5f 1904 vldr.16 s3, \[pc, #-8\] @ c <label>
+ 14: ed1f 3902 vldr.16 s6, \[pc, #-4\] @ 14 <label\+0x8>
+ 18: eddf 1902 vldr.16 s3, \[pc, #4\] @ 20 <label\+0x14>
1c: edd0 0902 vldr.16 s1, \[r0, #4\]
20: ed10 1902 vldr.16 s2, \[r0, #-4\]
24: ed80 3902 vstr.16 s6, \[r0, #4\]
00000000 <label-0xc>:
0: ee00 1910 vmov.f16 s0, r1
4: ee10 0990 vmov.f16 r0, s1
- 8: eeb0 0900 vmov.f16 s0, #0 ; 0x40000000 2.0
+ 8: eeb0 0900 vmov.f16 s0, #0 @ 0x40000000 2.0
0000000c <label>:
c: 00000ffe .word 0x00000ffe
- 10: ed5f 1904 vldr.16 s3, \[pc, #-8\] ; c <label>
- 14: ed1f 3902 vldr.16 s6, \[pc, #-4\] ; 14 <label\+0x8>
- 18: eddf 1902 vldr.16 s3, \[pc, #4\] ; 20 <label\+0x14>
+ 10: ed5f 1904 vldr.16 s3, \[pc, #-8\] @ c <label>
+ 14: ed1f 3902 vldr.16 s6, \[pc, #-4\] @ 14 <label\+0x8>
+ 18: eddf 1902 vldr.16 s3, \[pc, #4\] @ 20 <label\+0x14>
1c: edd0 0902 vldr.16 s1, \[r0, #4\]
20: ed10 1902 vldr.16 s2, \[r0, #-4\]
24: ed80 3902 vstr.16 s6, \[r0, #4\]
00000000 <label-0xc>:
0: ee001910 vmov.f16 s0, r1
4: ee100990 vmov.f16 r0, s1
- 8: eeb00900 vmov.f16 s0, #0 ; 0x40000000 2.0
+ 8: eeb00900 vmov.f16 s0, #0 @ 0x40000000 2.0
0000000c <label>:
c: 00000ffe .word 0x00000ffe
- 10: ed5f1906 vldr.16 s3, \[pc, #-12\] ; c <label>
- 14: ed1f3902 vldr.16 s6, \[pc, #-4\] ; 18 <label\+0xc>
- 18: eddf1902 vldr.16 s3, \[pc, #4\] ; 24 <label\+0x18>
+ 10: ed5f1906 vldr.16 s3, \[pc, #-12\] @ c <label>
+ 14: ed1f3902 vldr.16 s6, \[pc, #-4\] @ 18 <label\+0xc>
+ 18: eddf1902 vldr.16 s3, \[pc, #4\] @ 24 <label\+0x18>
1c: edd00902 vldr.16 s1, \[r0, #4\]
20: ed101902 vldr.16 s2, \[r0, #-4\]
24: ed803902 vstr.16 s6, \[r0, #4\]
0+05c <[^>]*> ecb0 0a01 (vldmia|fldmias) r0!, {s0}
0+060 <[^>]*> ed30 0a01 (vldmdb|fldmdbs) r0!, {s0}
0+064 <[^>]*> ed30 0a01 (vldmdb|fldmdbs) r0!, {s0}
-0+068 <[^>]*> ec90 0b03 fldmiax r0, {d0}( ;@ Deprecated|)
-0+06c <[^>]*> ec90 0b03 fldmiax r0, {d0}( ;@ Deprecated|)
-0+070 <[^>]*> ecb0 0b03 fldmiax r0!, {d0}( ;@ Deprecated|)
-0+074 <[^>]*> ecb0 0b03 fldmiax r0!, {d0}( ;@ Deprecated|)
-0+078 <[^>]*> ed30 0b03 fldmdbx r0!, {d0}( ;@ Deprecated|)
-0+07c <[^>]*> ed30 0b03 fldmdbx r0!, {d0}( ;@ Deprecated|)
+0+068 <[^>]*> ec90 0b03 fldmiax r0, {d0}( @ Deprecated|)
+0+06c <[^>]*> ec90 0b03 fldmiax r0, {d0}( @ Deprecated|)
+0+070 <[^>]*> ecb0 0b03 fldmiax r0!, {d0}( @ Deprecated|)
+0+074 <[^>]*> ecb0 0b03 fldmiax r0!, {d0}( @ Deprecated|)
+0+078 <[^>]*> ed30 0b03 fldmdbx r0!, {d0}( @ Deprecated|)
+0+07c <[^>]*> ed30 0b03 fldmdbx r0!, {d0}( @ Deprecated|)
0+080 <[^>]*> ec80 0a01 (vstmia|fstmias) r0, {s0}
0+084 <[^>]*> ec80 0a01 (vstmia|fstmias) r0, {s0}
0+088 <[^>]*> eca0 0a01 (vstmia|fstmias) r0!, {s0}
0+08c <[^>]*> eca0 0a01 (vstmia|fstmias) r0!, {s0}
0+090 <[^>]*> ed20 0a01 (vstmdb|fstmdbs) r0!, {s0}
0+094 <[^>]*> ed20 0a01 (vstmdb|fstmdbs) r0!, {s0}
-0+098 <[^>]*> ec80 0b03 fstmiax r0, {d0}( ;@ Deprecated|)
-0+09c <[^>]*> ec80 0b03 fstmiax r0, {d0}( ;@ Deprecated|)
-0+0a0 <[^>]*> eca0 0b03 fstmiax r0!, {d0}( ;@ Deprecated|)
-0+0a4 <[^>]*> eca0 0b03 fstmiax r0!, {d0}( ;@ Deprecated|)
-0+0a8 <[^>]*> ed20 0b03 fstmdbx r0!, {d0}( ;@ Deprecated|)
-0+0ac <[^>]*> ed20 0b03 fstmdbx r0!, {d0}( ;@ Deprecated|)
+0+098 <[^>]*> ec80 0b03 fstmiax r0, {d0}( @ Deprecated|)
+0+09c <[^>]*> ec80 0b03 fstmiax r0, {d0}( @ Deprecated|)
+0+0a0 <[^>]*> eca0 0b03 fstmiax r0!, {d0}( @ Deprecated|)
+0+0a4 <[^>]*> eca0 0b03 fstmiax r0!, {d0}( @ Deprecated|)
+0+0a8 <[^>]*> ed20 0b03 fstmdbx r0!, {d0}( @ Deprecated|)
+0+0ac <[^>]*> ed20 0b03 fstmdbx r0!, {d0}( @ Deprecated|)
0+0b0 <[^>]*> eeb8 0ac0 (vcvt\.f32\.s32|fsitos) s0, s0
0+0b4 <[^>]*> eeb8 0a40 (vcvt\.f32\.u32|fuitos) s0, s0
0+0b8 <[^>]*> eebd 0a40 (vcvtr\.s32\.f32|ftosis) s0, s0
0+210 <[^>]*> ec90 fa02 (vldmia|fldmias) r0, {s30-s31}
0+214 <[^>]*> ec91 0a01 (vldmia|fldmias) r1, {s0}
0+218 <[^>]*> ec9e 0a01 (vldmia|fldmias) lr, {s0}
-0+21c <[^>]*> ec80 1b03 fstmiax r0, {d1}( ;@ Deprecated|)
-0+220 <[^>]*> ec80 2b03 fstmiax r0, {d2}( ;@ Deprecated|)
-0+224 <[^>]*> ec80 fb03 fstmiax r0, {d15}( ;@ Deprecated|)
-0+228 <[^>]*> ec80 0b05 fstmiax r0, {d0-d1}( ;@ Deprecated|)
-0+22c <[^>]*> ec80 0b07 fstmiax r0, {d0-d2}( ;@ Deprecated|)
-0+230 <[^>]*> ec80 0b21 fstmiax r0, {d0-d15}( ;@ Deprecated|)
-0+234 <[^>]*> ec80 1b1f fstmiax r0, {d1-d15}( ;@ Deprecated|)
-0+238 <[^>]*> ec80 2b1d fstmiax r0, {d2-d15}( ;@ Deprecated|)
-0+23c <[^>]*> ec80 eb05 fstmiax r0, {d14-d15}( ;@ Deprecated|)
-0+240 <[^>]*> ec81 0b03 fstmiax r1, {d0}( ;@ Deprecated|)
-0+244 <[^>]*> ec8e 0b03 fstmiax lr, {d0}( ;@ Deprecated|)
+0+21c <[^>]*> ec80 1b03 fstmiax r0, {d1}( @ Deprecated|)
+0+220 <[^>]*> ec80 2b03 fstmiax r0, {d2}( @ Deprecated|)
+0+224 <[^>]*> ec80 fb03 fstmiax r0, {d15}( @ Deprecated|)
+0+228 <[^>]*> ec80 0b05 fstmiax r0, {d0-d1}( @ Deprecated|)
+0+22c <[^>]*> ec80 0b07 fstmiax r0, {d0-d2}( @ Deprecated|)
+0+230 <[^>]*> ec80 0b21 fstmiax r0, {d0-d15}( @ Deprecated|)
+0+234 <[^>]*> ec80 1b1f fstmiax r0, {d1-d15}( @ Deprecated|)
+0+238 <[^>]*> ec80 2b1d fstmiax r0, {d2-d15}( @ Deprecated|)
+0+23c <[^>]*> ec80 eb05 fstmiax r0, {d14-d15}( @ Deprecated|)
+0+240 <[^>]*> ec81 0b03 fstmiax r1, {d0}( @ Deprecated|)
+0+244 <[^>]*> ec8e 0b03 fstmiax lr, {d0}( @ Deprecated|)
0+248 <[^>]*> eeb5 0a40 (vcmp\.f32 s0, #0.0|fcmpzs s0)
0+24c <[^>]*> eef5 0a40 (vcmp\.f32 s1, #0.0|fcmpzs s1)
0+250 <[^>]*> eeb5 1a40 (vcmp\.f32 s2, #0.0|fcmpzs s2)
0+334 <[^>]*> bf01 itttt eq
0+336 <[^>]*> ed35 2a01 (vldmdbeq|fldmdbseq) r5!, {s4}
0+33a <[^>]*> ed76 1a01 (vldmdbeq|fldmdbseq) r6!, {s3}
-0+33e <[^>]*> ec97 1b03 fldmiaxeq r7, {d1}( ;@ Deprecated|)
-0+342 <[^>]*> ec98 2b03 fldmiaxeq r8, {d2}( ;@ Deprecated|)
+0+33e <[^>]*> ec97 1b03 fldmiaxeq r7, {d1}( @ Deprecated|)
+0+342 <[^>]*> ec98 2b03 fldmiaxeq r8, {d2}( @ Deprecated|)
0+346 <[^>]*> bf01 itttt eq
-0+348 <[^>]*> ecb9 3b03 fldmiaxeq r9!, {d3}( ;@ Deprecated|)
-0+34c <[^>]*> ecba 4b03 fldmiaxeq sl!, {d4}( ;@ Deprecated|)
-0+350 <[^>]*> ed3b 5b03 fldmdbxeq fp!, {d5}( ;@ Deprecated|)
-0+354 <[^>]*> ed3c 6b03 fldmdbxeq ip!, {d6}( ;@ Deprecated|)
+0+348 <[^>]*> ecb9 3b03 fldmiaxeq r9!, {d3}( @ Deprecated|)
+0+34c <[^>]*> ecba 4b03 fldmiaxeq sl!, {d4}( @ Deprecated|)
+0+350 <[^>]*> ed3b 5b03 fldmdbxeq fp!, {d5}( @ Deprecated|)
+0+354 <[^>]*> ed3c 6b03 fldmdbxeq ip!, {d6}( @ Deprecated|)
0+358 <[^>]*> bf01 itttt eq
0+35a <[^>]*> ec8d 1a01 (vstmiaeq|fstmiaseq) sp, {s2}
0+35e <[^>]*> ecce 0a01 (vstmiaeq|fstmiaseq) lr, {s1}
0+36a <[^>]*> bf01 itttt eq
0+36c <[^>]*> ed63 ea01 (vstmdbeq|fstmdbseq) r3!, {s29}
0+370 <[^>]*> ed24 ea01 (vstmdbeq|fstmdbseq) r4!, {s28}
-0+374 <[^>]*> ec85 7b03 fstmiaxeq r5, {d7}( ;@ Deprecated|)
-0+378 <[^>]*> ec86 8b03 fstmiaxeq r6, {d8}( ;@ Deprecated|)
+0+374 <[^>]*> ec85 7b03 fstmiaxeq r5, {d7}( @ Deprecated|)
+0+378 <[^>]*> ec86 8b03 fstmiaxeq r6, {d8}( @ Deprecated|)
0+37c <[^>]*> bf01 itttt eq
-0+37e <[^>]*> eca7 9b03 fstmiaxeq r7!, {d9}( ;@ Deprecated|)
-0+382 <[^>]*> eca8 ab03 fstmiaxeq r8!, {d10}( ;@ Deprecated|)
-0+386 <[^>]*> ed29 bb03 fstmdbxeq r9!, {d11}( ;@ Deprecated|)
-0+38a <[^>]*> ed2a cb03 fstmdbxeq sl!, {d12}( ;@ Deprecated|)
+0+37e <[^>]*> eca7 9b03 fstmiaxeq r7!, {d9}( @ Deprecated|)
+0+382 <[^>]*> eca8 ab03 fstmiaxeq r8!, {d10}( @ Deprecated|)
+0+386 <[^>]*> ed29 bb03 fstmdbxeq r9!, {d11}( @ Deprecated|)
+0+38a <[^>]*> ed2a cb03 fstmdbxeq sl!, {d12}( @ Deprecated|)
0+38e <[^>]*> bf01 itttt eq
0+390 <[^>]*> eef8 dac3 (vcvteq\.f32\.s32|fsitoseq) s27, s6
0+394 <[^>]*> eefd ca62 (vcvtreq\.s32\.f32|ftosiseq) s25, s5
00000000 <label-0xc>:
0: ee00 1910 vmov.f16 s0, r1
4: ee10 0990 vmov.f16 r0, s1
- 8: eeb0 0900 vmov.f16 s0, #0 ; 0x40000000 2.0
+ 8: eeb0 0900 vmov.f16 s0, #0 @ 0x40000000 2.0
0000000c <label>:
c: 00000ffe .word 0x00000ffe
- 10: ed5f 1904 vldr.16 s3, \[pc, #-8\] ; c <label>
- 14: ed1f 3902 vldr.16 s6, \[pc, #-4\] ; 14 <label\+0x8>
- 18: eddf 1902 vldr.16 s3, \[pc, #4\] ; 20 <label\+0x14>
+ 10: ed5f 1904 vldr.16 s3, \[pc, #-8\] @ c <label>
+ 14: ed1f 3902 vldr.16 s6, \[pc, #-4\] @ 14 <label\+0x8>
+ 18: eddf 1902 vldr.16 s3, \[pc, #4\] @ 20 <label\+0x14>
1c: edd0 0902 vldr.16 s1, \[r0, #4\]
20: ed10 1902 vldr.16 s2, \[r0, #-4\]
24: ed80 3902 vstr.16 s6, \[r0, #4\]
Disassembly of section \.text:
0+00 <[^>]+> e12fff1e bx lr
-0+04 <[^>]+> 46c0 nop ; \(mov r8, r8\)
+0+04 <[^>]+> 46c0 nop @ \(mov r8, r8\)
0+06 <[^>]+> f7ff effc blx 0+ <myfunction>
-0+0a <[^>]+> 46c0 nop ; \(mov r8, r8\)
+0+0a <[^>]+> 46c0 nop @ \(mov r8, r8\)
0+0c <[^>]+> f7ff eff8 blx 0+ <myfunction>
-0+10 <[^>]+> 46c0 nop ; \(mov r8, r8\)
+0+10 <[^>]+> 46c0 nop @ \(mov r8, r8\)
0+12 <[^>]+> f7ff eff6 blx 0+ <myfunction>
-0+16 <[^>]+> 46c0 nop ; \(mov r8, r8\)
+0+16 <[^>]+> 46c0 nop @ \(mov r8, r8\)
0+18 <[^>]+> f7ff eff2 blx 0+ <myfunction>
0+1c <[^>]+> 4770 bx lr
-0+1e <[^>]+> 46c0 nop ; \(mov r8, r8\)
+0+1e <[^>]+> 46c0 nop @ \(mov r8, r8\)
0+20 <[^>]+> fafffffd blx 0000001c <mythumbfunction>
0+06 <[^>]*> e003 b.n 00+10 <[^>]*>
0+08 <[^>]*> f000 f808 bl 00+1c <[^>]*>
0+0c <[^>]*> f000 f802 bl 00+14 <[^>]*>
-0+10 <[^>]*> 46c0 nop ; \(mov r8, r8\)
-0+12 <[^>]*> 46c0 nop ; \(mov r8, r8\)
-0+14 <[^>]*> 46c0 nop ; \(mov r8, r8\)
+0+10 <[^>]*> 46c0 nop @ \(mov r8, r8\)
+0+12 <[^>]*> 46c0 nop @ \(mov r8, r8\)
+0+14 <[^>]*> 46c0 nop @ \(mov r8, r8\)
...
-0+18 <[^>]*> e1a00000 nop ; \(mov r0, r0\)
-0+1c <[^>]*> e1a00000 nop ; \(mov r0, r0\)
+0+18 <[^>]*> e1a00000 nop @ \(mov r0, r0\)
+0+1c <[^>]*> e1a00000 nop @ \(mov r0, r0\)
Disassembly of section .text:
00000000 <ARM>:
- 0: e1a00000 nop ; \(mov r0, r0\)
+ 0: e1a00000 nop @ \(mov r0, r0\)
00000004 <THUMB>:
4: f7ff effc blx 0 <ARM>
- 8: 46c0 nop ; \(mov r8, r8\)
+ 8: 46c0 nop @ \(mov r8, r8\)
a: f7ff effa blx 0 <ARM>
- e: 46c0 nop ; \(mov r8, r8\)
+ e: 46c0 nop @ \(mov r8, r8\)
10: f7ff eff6 blx 0 <ARM>
- 14: f7ff eff5 ; <UNDEFINED> instruction: 0xf7ffeff5
- 18: 46c0 nop ; \(mov r8, r8\)
- 1a: f7ff eff1 ; <UNDEFINED> instruction: 0xf7ffeff1
+ 14: f7ff eff5 @ <UNDEFINED> instruction: 0xf7ffeff5
+ 18: 46c0 nop @ \(mov r8, r8\)
+ 1a: f7ff eff1 @ <UNDEFINED> instruction: 0xf7ffeff1
1e: f7ff eff0 blx 0 <ARM>
- 22: 46c0 nop ; \(mov r8, r8\)
+ 22: 46c0 nop @ \(mov r8, r8\)
[^<]*<one\+0x1c> f000 f804 bl 00000028 <fooundefthumb>
[^<]*<foo> e7ee b.n 00000000 <one>
[^<]*<foo\+0x2> e003 b.n 0000002c <foo2>
-[^<]*<foo\+0x4> 46c0 nop ; \(mov r8, r8\)
-[^<]*<foo\+0x6> 46c0 nop ; \(mov r8, r8\)
-[^<]*<fooundefthumb> 46c0 nop ; \(mov r8, r8\)
+[^<]*<foo\+0x4> 46c0 nop @ \(mov r8, r8\)
+[^<]*<foo\+0x6> 46c0 nop @ \(mov r8, r8\)
+[^<]*<fooundefthumb> 46c0 nop @ \(mov r8, r8\)
...
-[^<]*<foo2> e1a00000 nop ; \(mov r0, r0\)
-[^<]*<fooundefarm> e1a00000 nop ; \(mov r0, r0\)
+[^<]*<foo2> e1a00000 nop @ \(mov r0, r0\)
+[^<]*<fooundefarm> e1a00000 nop @ \(mov r0, r0\)
0+14 <[^>]*> eb00000a bl 00000044 <fooundefarm>
0+18 <[^>]*> fa000001 blx 00000024 <fooundefthumb>
0+1c <[^>]*> eb000000 bl 00000024 <fooundefthumb>
-0+20 <[^>]*> 46c0 nop ; \(mov r8, r8\)
-0+22 <[^>]*> 46c0 nop ; \(mov r8, r8\)
-0+24 <[^>]*> 46c0 nop ; \(mov r8, r8\)
-0+26 <[^>]*> 46c0 nop ; \(mov r8, r8\)
+0+20 <[^>]*> 46c0 nop @ \(mov r8, r8\)
+0+22 <[^>]*> 46c0 nop @ \(mov r8, r8\)
+0+24 <[^>]*> 46c0 nop @ \(mov r8, r8\)
+0+26 <[^>]*> 46c0 nop @ \(mov r8, r8\)
0+28 <[^>]*> 0bfffffd bleq 00000024 <fooundefthumb>
0+2c <[^>]*> 0afffffc beq 00000024 <fooundefthumb>
0+30 <[^>]*> eafffffb b 00000024 <fooundefthumb>
0+34 <[^>]*> 0bfffffe bleq 00000020 <foo> 34: R_ARM_JUMP24 foo
0+38 <[^>]*> 0afffffe beq 00000020 <foo> 38: R_ARM_JUMP24 foo
0+3c <[^>]*> eafffffe b 00000020 <foo> 3c: R_ARM_JUMP24 foo
-0+40 <[^>]*> e1a00000 nop ; \(mov r0, r0\)
-0+44 <[^>]*> e1a00000 nop ; \(mov r0, r0\)
+0+40 <[^>]*> e1a00000 nop @ \(mov r0, r0\)
+0+44 <[^>]*> e1a00000 nop @ \(mov r0, r0\)
Disassembly of section .text:
00000000 <arm_glob_sym1-0x4>:
- 0: e1a00000 nop ; \(mov r0, r0\)
+ 0: e1a00000 nop @ \(mov r0, r0\)
00000004 <arm_glob_sym1>:
4: ebfffffe bl 46 <thumb_glob_sym1>
2c: fafffffe blx 13c <arm_glob_sym2>
2c: R_ARM_CALL arm_glob_sym2
30: eb000001 bl 3c <arm_sym1>
- 34: e1a00000 nop ; \(mov r0, r0\)
+ 34: e1a00000 nop @ \(mov r0, r0\)
38: e12fff1e bx lr
0000003c <arm_sym1>:
- 3c: e1a00000 nop ; \(mov r0, r0\)
+ 3c: e1a00000 nop @ \(mov r0, r0\)
40: e12fff1e bx lr
00000044 <thumb_sym1>:
128: f7ff effe blx 100 <thumb_glob_sym2>
128: R_ARM_THM_CALL thumb_glob_sym2
12c: f000 f802 bl 134 <thumb_sym2>
- 130: 46c0 nop ; \(mov r8, r8\)
+ 130: 46c0 nop @ \(mov r8, r8\)
132: 4770 bx lr
00000134 <thumb_sym2>:
- 134: 46c0 nop ; \(mov r8, r8\)
+ 134: 46c0 nop @ \(mov r8, r8\)
136: 4770 bx lr
00000138 <arm_sym2>:
00000000 <_test_func>:
0: e92d5fff push {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
- 4: e59fc018 ldr ip, \[pc, #24\] ; 24 <sym1>
+ 4: e59fc018 ldr ip, \[pc, #24\] @ 24 <sym1>
8: e59c0000 ldr r0, \[ip\]
c: e3100008 tst r0, #8
10: 1a000000 bne 18 <aLabel>
0+00c <[^>]*> edd1e108 ldfp f6, \[r1, #32\]
0+010 <[^>]*> 4db200ff ldcmi 0, cr0, \[r2, #1020\]!.*
0+014 <[^>]*> 5cf31710 ldclpl 7, cr1, \[r3\], #64.*
-0+018 <[^>]*> ed1f8001 ldc 0, cr8, \[pc, #-4\] ; .* <foo>
+0+018 <[^>]*> ed1f8001 ldc 0, cr8, \[pc, #-4\] @ .* <foo>
0+01c <[^>]*> ed830500 cfstr32 mvfx0, \[r3\]
0+020 <[^>]*> edc0f302 stcl 3, cr15, \[r0, #8\]
0+024 <[^>]*> 0da2c419 cfstrseq mvf12, \[r2, #100\]!.*
0+028 <[^>]*> 3ca4860c stccc 6, cr8, \[r4\], #48.*
-0+02c <[^>]*> ed0f7101 stfs f7, \[pc, #-4\] ; .* <bar>
+0+02c <[^>]*> ed0f7101 stfs f7, \[pc, #-4\] @ .* <bar>
0+030 <[^>]*> ee715212 mrc 2, 3, r5, cr1, cr2, \{0\}
0+034 <[^>]*> aeb1f4f2 mrcge 4, 5, APSR_nzcv, cr1, cr2, \{7\}
0+038 <[^>]*> ee215711 mcr 7, 1, r5, cr1, cr1, \{0\}
0+04c <[^>]*> ecc52805 stcl 8, cr2, \[r5\], \{5\}
0+050 <[^>]*> ecd88cff ldcl 12, cr8, \[r8\], \{255\}.*
0+054 <[^>]*> ecc99cfe stcl 12, cr9, \[r9\], \{254\}.*
-0+058 <[^>]*> e1a00000 nop ; \(mov r0, r0\)
-0+05c <[^>]*> e1a00000 nop ; \(mov r0, r0\)
+0+058 <[^>]*> e1a00000 nop @ \(mov r0, r0\)
+0+05c <[^>]*> e1a00000 nop @ \(mov r0, r0\)
0+060 <[^>]*> aeb1f4f2 mrcge 4, 5, APSR_nzcv, cr1, cr2, \{7\}
0+000 <[^>]*> fe421103 cdp2 1, 4, cr1, cr2, cr3, \{0\}
0+004 <[^>]*> fd939500 ldc2 5, cr9, \[r3\]
0+008 <[^>]*> fdd1e108 ldc2l 1, cr14, \[r1, #32\]
-0+00c <[^>]*> fd1f8001 ldc2 0, cr8, \[pc, #-4\] ; .* <foo>
+0+00c <[^>]*> fd1f8001 ldc2 0, cr8, \[pc, #-4\] @ .* <foo>
0+010 <[^>]*> fd830500 stc2 5, cr0, \[r3\]
0+014 <[^>]*> fdc0f302 stc2l 3, cr15, \[r0, #8\]
-0+018 <[^>]*> fd0f7101 stc2 1, cr7, \[pc, #-4\] ; .* <bar>
+0+018 <[^>]*> fd0f7101 stc2 1, cr7, \[pc, #-4\] @ .* <bar>
0+01c <[^>]*> fe715212 mrc2 2, 3, r5, cr1, cr2, \{0\}
0+020 <[^>]*> fe215711 mcr2 7, 1, r5, cr1, cr1, \{0\}
0+024 <[^>]*> fc925502 ldc2 5, cr5, \[r2\], \{2\}
0+012 <[^>]*> [^ ]* ite mi
0+014 <[^>]*> edb2 00ff ldcmi 0, cr0, \[r2, #1020\]!.*
0+018 <[^>]*> ecf3 1710 ldclpl 7, cr1, \[r3\], #64.*
-0+01c <[^>]*> ed9f 8000 ldc 0, cr8, \[pc] ; .* <foo>
+0+01c <[^>]*> ed9f 8000 ldc 0, cr8, \[pc] @ .* <foo>
0+020 <[^>]*> ed83 0500 cfstr32 mvfx0, \[r3\]
0+024 <[^>]*> edc0 f302 stcl 3, cr15, \[r0, #8\]
0+028 <[^>]*> [^ ]* it eq
0+02a <[^>]*> eda2 c419 cfstrseq mvf12, \[r2, #100\]!.*
0+02e <[^>]*> [^ ]* it cc
0+030 <[^>]*> eca4 860c stccc 6, cr8, \[r4\], #48.*
-0+034 <[^>]*> ed8f 7100 stfs f7, \[pc\] ; .* <bar>
+0+034 <[^>]*> ed8f 7100 stfs f7, \[pc\] @ .* <bar>
0+038 <[^>]*> ee71 5212 mrc 2, 3, r5, cr1, cr2, \{0\}
0+03c <[^>]*> [^ ]* it ge
0+03e <[^>]*> eeb1 f4f2 mrcge 4, 5, APSR_nzcv, cr1, cr2, \{7\}
0+000 <[^>]*> fe42 1103 cdp2 1, 4, cr1, cr2, cr3, \{0\}
0+004 <[^>]*> fd93 9500 ldc2 5, cr9, \[r3\]
0+008 <[^>]*> fdd1 e108 ldc2l 1, cr14, \[r1, #32\]
-0+00c <[^>]*> fd9f 8000 ldc2 0, cr8, \[pc\] ; .* <foo>
+0+00c <[^>]*> fd9f 8000 ldc2 0, cr8, \[pc\] @ .* <foo>
0+010 <[^>]*> fd83 0500 stc2 5, cr0, \[r3\]
0+014 <[^>]*> fdc0 f302 stc2l 3, cr15, \[r0, #8\]
-0+018 <[^>]*> fd8f 7100 stc2 1, cr7, \[pc\] ; .* <bar>
+0+018 <[^>]*> fd8f 7100 stc2 1, cr7, \[pc\] @ .* <bar>
0+01c <[^>]*> fe71 5212 mrc2 2, 3, r5, cr1, cr2, \{0\}
0+020 <[^>]*> fe21 5711 mcr2 7, 1, r5, cr1, cr1, \{0\}
0+024 <[^>]*> fc92 5502 ldc2 5, cr5, \[r2\], \{2\}
Disassembly of section .text:
-0+0 <[^>]*> e101f042 crc32b pc, r1, r2 ; <UNPREDICTABLE>
-0+4 <[^>]*> e12f0042 crc32h r0, pc, r2 ; <UNPREDICTABLE>
-0+8 <[^>]*> e141004f crc32w r0, r1, pc ; <UNPREDICTABLE>
-0+c <[^>]*> e10f0242 crc32cb r0, pc, r2 ; <UNPREDICTABLE>
-0+10 <[^>]*> e121f242 crc32ch pc, r1, r2 ; <UNPREDICTABLE>
-0+14 <[^>]*> e14f0242 crc32cw r0, pc, r2 ; <UNPREDICTABLE>
-0+18 <[^>]*> fac1 ff82 crc32b pc, r1, r2 ; <UNPREDICTABLE>
-0+1c <[^>]*> facf f092 crc32h r0, pc, r2 ; <UNPREDICTABLE>
-0+20 <[^>]*> fac1 f0af crc32w r0, r1, pc ; <UNPREDICTABLE>
-0+24 <[^>]*> fadf f082 crc32cb r0, pc, r2 ; <UNPREDICTABLE>
-0+28 <[^>]*> fad1 ff92 crc32ch pc, r1, r2 ; <UNPREDICTABLE>
-0+2c <[^>]*> fadf f0a2 crc32cw r0, pc, r2 ; <UNPREDICTABLE>
+0+0 <[^>]*> e101f042 crc32b pc, r1, r2 @ <UNPREDICTABLE>
+0+4 <[^>]*> e12f0042 crc32h r0, pc, r2 @ <UNPREDICTABLE>
+0+8 <[^>]*> e141004f crc32w r0, r1, pc @ <UNPREDICTABLE>
+0+c <[^>]*> e10f0242 crc32cb r0, pc, r2 @ <UNPREDICTABLE>
+0+10 <[^>]*> e121f242 crc32ch pc, r1, r2 @ <UNPREDICTABLE>
+0+14 <[^>]*> e14f0242 crc32cw r0, pc, r2 @ <UNPREDICTABLE>
+0+18 <[^>]*> fac1 ff82 crc32b pc, r1, r2 @ <UNPREDICTABLE>
+0+1c <[^>]*> facf f092 crc32h r0, pc, r2 @ <UNPREDICTABLE>
+0+20 <[^>]*> fac1 f0af crc32w r0, r1, pc @ <UNPREDICTABLE>
+0+24 <[^>]*> fadf f082 crc32cb r0, pc, r2 @ <UNPREDICTABLE>
+0+28 <[^>]*> fad1 ff92 crc32ch pc, r1, r2 @ <UNPREDICTABLE>
+0+2c <[^>]*> fadf f0a2 crc32cw r0, pc, r2 @ <UNPREDICTABLE>
Disassembly of section .text:
-0+0 <[^>]*> e101f042 crc32b pc, r1, r2 ; <UNPREDICTABLE>
-0+4 <[^>]*> e12f0042 crc32h r0, pc, r2 ; <UNPREDICTABLE>
-0+8 <[^>]*> e141004f crc32w r0, r1, pc ; <UNPREDICTABLE>
-0+c <[^>]*> e10f0242 crc32cb r0, pc, r2 ; <UNPREDICTABLE>
-0+10 <[^>]*> e121f242 crc32ch pc, r1, r2 ; <UNPREDICTABLE>
-0+14 <[^>]*> e14f0242 crc32cw r0, pc, r2 ; <UNPREDICTABLE>
-0+18 <[^>]*> fac1 ff82 crc32b pc, r1, r2 ; <UNPREDICTABLE>
-0+1c <[^>]*> facf f092 crc32h r0, pc, r2 ; <UNPREDICTABLE>
-0+20 <[^>]*> fac1 f0af crc32w r0, r1, pc ; <UNPREDICTABLE>
-0+24 <[^>]*> fadf f082 crc32cb r0, pc, r2 ; <UNPREDICTABLE>
-0+28 <[^>]*> fad1 ff92 crc32ch pc, r1, r2 ; <UNPREDICTABLE>
-0+2c <[^>]*> fadf f0a2 crc32cw r0, pc, r2 ; <UNPREDICTABLE>
+0+0 <[^>]*> e101f042 crc32b pc, r1, r2 @ <UNPREDICTABLE>
+0+4 <[^>]*> e12f0042 crc32h r0, pc, r2 @ <UNPREDICTABLE>
+0+8 <[^>]*> e141004f crc32w r0, r1, pc @ <UNPREDICTABLE>
+0+c <[^>]*> e10f0242 crc32cb r0, pc, r2 @ <UNPREDICTABLE>
+0+10 <[^>]*> e121f242 crc32ch pc, r1, r2 @ <UNPREDICTABLE>
+0+14 <[^>]*> e14f0242 crc32cw r0, pc, r2 @ <UNPREDICTABLE>
+0+18 <[^>]*> fac1 ff82 crc32b pc, r1, r2 @ <UNPREDICTABLE>
+0+1c <[^>]*> facf f092 crc32h r0, pc, r2 @ <UNPREDICTABLE>
+0+20 <[^>]*> fac1 f0af crc32w r0, r1, pc @ <UNPREDICTABLE>
+0+24 <[^>]*> fadf f082 crc32cb r0, pc, r2 @ <UNPREDICTABLE>
+0+28 <[^>]*> fad1 ff92 crc32ch pc, r1, r2 @ <UNPREDICTABLE>
+0+2c <[^>]*> fadf f0a2 crc32cw r0, pc, r2 @ <UNPREDICTABLE>
00000000 <main> 20010000 .word 0x20010000
00000004 <main\+0x4> 000000f9 .word 0x000000f9
00000008 <main\+0x8> 00004cd5 .word 0x00004cd5
-0000000c <main\+0xc> e1a00000 nop ; \(mov r0, r0\)
+0000000c <main\+0xc> e1a00000 nop @ \(mov r0, r0\)
0+60 <[^>]+> e1220051 qsub r0, r1, r2
0+64 <[^>]+> e1620051 qdsub r0, r1, r2
0+68 <[^>]+> e1220051 qsub r0, r1, r2
-0+6c <[^>]+> e1a00000 nop ; \(mov r0, r0\)
+0+6c <[^>]+> e1a00000 nop @ \(mov r0, r0\)
0+1d0 <[^>]+> ed911210 ? lfm f1, 4, \[r1, #64\].*
0+1d4 <[^>]+> edae22ff ? sfm f2, 4, \[lr, #1020\]!.*
0+1d8 <[^>]+> 0c68f2ff ? sfmeq f7, 3, \[r8\], #-1020.*
-0+1dc <[^>]+> eddf6200 ? lfm f6, 2, \[pc\] ; .* <l\+.*>
+0+1dc <[^>]+> eddf6200 ? lfm f6, 2, \[pc\] @ .* <l\+.*>
0+1e0 <[^>]+> eca8f203 ? sfm f7, 1, \[r8\], #12
0+1e4 <[^>]+> 0d16520c ? lfmeq f5, 4, \[r6, #-48\].*
0+1e8 <[^>]+> 1d42c209 ? sfmne f4, 3, \[r2, #-36\].*
.*: +file format .*arm.*
Disassembly of section .text:
-0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 @ 0x100
0: R_ARM_ALU_PC_G0 f
-0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 @ 0x100
4: R_ARM_ALU_PC_G1 f
-0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 @ 0x100
8: R_ARM_ALU_PC_G2 f
-0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 @ 0x100
c: R_ARM_ALU_PC_G0_NC f
-0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 @ 0x100
10: R_ARM_ALU_PC_G1_NC f
-0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 @ 0x100
14: R_ARM_ALU_SB_G0 f
-0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 @ 0x100
18: R_ARM_ALU_SB_G1 f
-0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 @ 0x100
1c: R_ARM_ALU_SB_G2 f
-0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 @ 0x100
20: R_ARM_ALU_SB_G0_NC f
-0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 @ 0x100
24: R_ARM_ALU_SB_G1_NC f
-0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 @ 0x100
28: R_ARM_ALU_PC_G0 localsym
-0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 @ 0x100
2c: R_ARM_ALU_PC_G1 localsym
-0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 @ 0x100
30: R_ARM_ALU_PC_G2 localsym
-0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 @ 0x100
34: R_ARM_ALU_PC_G0_NC localsym
-0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 @ 0x100
38: R_ARM_ALU_PC_G1_NC localsym
-0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 @ 0x100
3c: R_ARM_ALU_SB_G0 localsym
-0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 @ 0x100
40: R_ARM_ALU_SB_G1 localsym
-0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 @ 0x100
44: R_ARM_ALU_SB_G2 localsym
-0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 @ 0x100
48: R_ARM_ALU_SB_G0_NC localsym
-0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 @ 0x100
4c: R_ARM_ALU_SB_G1_NC localsym
-0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 @ 0x100
50: R_ARM_ALU_PC_G0 f
-0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 @ 0x100
54: R_ARM_ALU_PC_G1 f
-0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 @ 0x100
58: R_ARM_ALU_PC_G2 f
-0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 @ 0x100
5c: R_ARM_ALU_PC_G0_NC f
-0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 @ 0x100
60: R_ARM_ALU_PC_G1_NC f
-0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 @ 0x100
64: R_ARM_ALU_SB_G0 f
-0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 @ 0x100
68: R_ARM_ALU_SB_G1 f
-0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 @ 0x100
6c: R_ARM_ALU_SB_G2 f
-0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 @ 0x100
70: R_ARM_ALU_SB_G0_NC f
-0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 @ 0x100
74: R_ARM_ALU_SB_G1_NC f
-0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 @ 0x100
78: R_ARM_ALU_PC_G0 localsym
-0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 @ 0x100
7c: R_ARM_ALU_PC_G1 localsym
-0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 @ 0x100
80: R_ARM_ALU_PC_G2 localsym
-0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 @ 0x100
84: R_ARM_ALU_PC_G0_NC localsym
-0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 @ 0x100
88: R_ARM_ALU_PC_G1_NC localsym
-0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 @ 0x100
8c: R_ARM_ALU_SB_G0 localsym
-0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 @ 0x100
90: R_ARM_ALU_SB_G1 localsym
-0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 @ 0x100
94: R_ARM_ALU_SB_G2 localsym
-0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 @ 0x100
98: R_ARM_ALU_SB_G0_NC localsym
-0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 @ 0x100
9c: R_ARM_ALU_SB_G1_NC localsym
-0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 @ 0x100
a0: R_ARM_ALU_PC_G0 f
-0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 @ 0x100
a4: R_ARM_ALU_PC_G1 f
-0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 @ 0x100
a8: R_ARM_ALU_PC_G2 f
-0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 @ 0x100
ac: R_ARM_ALU_PC_G0_NC f
-0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 @ 0x100
b0: R_ARM_ALU_PC_G1_NC f
-0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 @ 0x100
b4: R_ARM_ALU_SB_G0 f
-0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 @ 0x100
b8: R_ARM_ALU_SB_G1 f
-0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 @ 0x100
bc: R_ARM_ALU_SB_G2 f
-0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 @ 0x100
c0: R_ARM_ALU_SB_G0_NC f
-0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 @ 0x100
c4: R_ARM_ALU_SB_G1_NC f
-0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 @ 0x100
c8: R_ARM_ALU_PC_G0 localsym
-0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 @ 0x100
cc: R_ARM_ALU_PC_G1 localsym
-0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 @ 0x100
d0: R_ARM_ALU_PC_G2 localsym
-0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 @ 0x100
d4: R_ARM_ALU_PC_G0_NC localsym
-0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 @ 0x100
d8: R_ARM_ALU_PC_G1_NC localsym
-0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 @ 0x100
dc: R_ARM_ALU_SB_G0 localsym
-0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 @ 0x100
e0: R_ARM_ALU_SB_G1 localsym
-0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 @ 0x100
e4: R_ARM_ALU_SB_G2 localsym
-0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 @ 0x100
e8: R_ARM_ALU_SB_G0_NC localsym
-0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 @ 0x100
ec: R_ARM_ALU_SB_G1_NC localsym
-0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 @ 0x100
f0: R_ARM_ALU_PC_G0 f
-0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 @ 0x100
f4: R_ARM_ALU_PC_G1 f
-0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 @ 0x100
f8: R_ARM_ALU_PC_G2 f
-0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 @ 0x100
fc: R_ARM_ALU_PC_G0_NC f
-0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 @ 0x100
100: R_ARM_ALU_PC_G1_NC f
-0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 @ 0x100
104: R_ARM_ALU_SB_G0 f
-0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 @ 0x100
108: R_ARM_ALU_SB_G1 f
-0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 @ 0x100
10c: R_ARM_ALU_SB_G2 f
-0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 @ 0x100
110: R_ARM_ALU_SB_G0_NC f
-0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 @ 0x100
114: R_ARM_ALU_SB_G1_NC f
-0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 @ 0x100
118: R_ARM_ALU_PC_G0 localsym
-0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 @ 0x100
11c: R_ARM_ALU_PC_G1 localsym
-0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 @ 0x100
120: R_ARM_ALU_PC_G2 localsym
-0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 @ 0x100
124: R_ARM_ALU_PC_G0_NC localsym
-0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 @ 0x100
128: R_ARM_ALU_PC_G1_NC localsym
-0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 @ 0x100
12c: R_ARM_ALU_SB_G0 localsym
-0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 @ 0x100
130: R_ARM_ALU_SB_G1 localsym
-0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 @ 0x100
134: R_ARM_ALU_SB_G2 localsym
-0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 @ 0x100
138: R_ARM_ALU_SB_G0_NC localsym
-0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
+0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 @ 0x100
13c: R_ARM_ALU_SB_G1_NC localsym
0[0-9a-f]+ <[^>]+> e3a00000 mov r0, #0
.*: +file format .*arm.*
Disassembly of section .text:
-0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] @ 0xff
0: R_ARM_LDRS_PC_G1 f
-0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] @ 0xff
4: R_ARM_LDRS_PC_G2 f
-0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] @ 0xff
8: R_ARM_LDRS_SB_G0 f
-0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] @ 0xff
c: R_ARM_LDRS_SB_G1 f
-0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] @ 0xff
10: R_ARM_LDRS_SB_G2 f
-0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] @ 0xff
14: R_ARM_LDRS_PC_G1 f
-0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] @ 0xff
18: R_ARM_LDRS_PC_G2 f
-0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] @ 0xff
1c: R_ARM_LDRS_SB_G0 f
-0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] @ 0xff
20: R_ARM_LDRS_SB_G1 f
-0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] @ 0xff
24: R_ARM_LDRS_SB_G2 f
-0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] @ 0xff
28: R_ARM_LDRS_PC_G1 f
-0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] @ 0xff
2c: R_ARM_LDRS_PC_G2 f
-0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] @ 0xff
30: R_ARM_LDRS_SB_G0 f
-0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] @ 0xff
34: R_ARM_LDRS_SB_G1 f
-0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] @ 0xff
38: R_ARM_LDRS_SB_G2 f
-0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] @ 0xff
3c: R_ARM_LDRS_PC_G1 f
-0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] @ 0xff
40: R_ARM_LDRS_PC_G2 f
-0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] @ 0xff
44: R_ARM_LDRS_SB_G0 f
-0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] @ 0xff
48: R_ARM_LDRS_SB_G1 f
-0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] @ 0xff
4c: R_ARM_LDRS_SB_G2 f
-0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] @ 0xff
50: R_ARM_LDRS_PC_G1 f
-0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] @ 0xff
54: R_ARM_LDRS_PC_G2 f
-0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] @ 0xff
58: R_ARM_LDRS_SB_G0 f
-0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] @ 0xff
5c: R_ARM_LDRS_SB_G1 f
-0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] @ 0xff
60: R_ARM_LDRS_SB_G2 f
-0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] @ 0xff
64: R_ARM_LDRS_PC_G1 f
-0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] @ 0xff
68: R_ARM_LDRS_PC_G2 f
-0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] @ 0xff
6c: R_ARM_LDRS_SB_G0 f
-0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] @ 0xff
70: R_ARM_LDRS_SB_G1 f
-0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] @ 0xff
74: R_ARM_LDRS_SB_G2 f
-0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] @ 0xffffff01
78: R_ARM_LDRS_PC_G1 f
-0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] @ 0xffffff01
7c: R_ARM_LDRS_PC_G2 f
-0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] @ 0xffffff01
80: R_ARM_LDRS_SB_G0 f
-0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] @ 0xffffff01
84: R_ARM_LDRS_SB_G1 f
-0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] @ 0xffffff01
88: R_ARM_LDRS_SB_G2 f
-0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] @ 0xffffff01
8c: R_ARM_LDRS_PC_G1 f
-0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] @ 0xffffff01
90: R_ARM_LDRS_PC_G2 f
-0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] @ 0xffffff01
94: R_ARM_LDRS_SB_G0 f
-0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] @ 0xffffff01
98: R_ARM_LDRS_SB_G1 f
-0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] @ 0xffffff01
9c: R_ARM_LDRS_SB_G2 f
-0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] @ 0xffffff01
a0: R_ARM_LDRS_PC_G1 f
-0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] @ 0xffffff01
a4: R_ARM_LDRS_PC_G2 f
-0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] @ 0xffffff01
a8: R_ARM_LDRS_SB_G0 f
-0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] @ 0xffffff01
ac: R_ARM_LDRS_SB_G1 f
-0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] @ 0xffffff01
b0: R_ARM_LDRS_SB_G2 f
-0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] @ 0xffffff01
b4: R_ARM_LDRS_PC_G1 f
-0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] @ 0xffffff01
b8: R_ARM_LDRS_PC_G2 f
-0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] @ 0xffffff01
bc: R_ARM_LDRS_SB_G0 f
-0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] @ 0xffffff01
c0: R_ARM_LDRS_SB_G1 f
-0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] @ 0xffffff01
c4: R_ARM_LDRS_SB_G2 f
-0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] @ 0xffffff01
c8: R_ARM_LDRS_PC_G1 f
-0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] @ 0xffffff01
cc: R_ARM_LDRS_PC_G2 f
-0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] @ 0xffffff01
d0: R_ARM_LDRS_SB_G0 f
-0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] @ 0xffffff01
d4: R_ARM_LDRS_SB_G1 f
-0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] @ 0xffffff01
d8: R_ARM_LDRS_SB_G2 f
-0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] @ 0xffffff01
dc: R_ARM_LDRS_PC_G1 f
-0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] @ 0xffffff01
e0: R_ARM_LDRS_PC_G2 f
-0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] @ 0xffffff01
e4: R_ARM_LDRS_SB_G0 f
-0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] @ 0xffffff01
e8: R_ARM_LDRS_SB_G1 f
-0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] @ 0xffffff01
ec: R_ARM_LDRS_SB_G2 f
-0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] @ 0xff
f0: R_ARM_LDRS_PC_G1 localsym
-0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] @ 0xff
f4: R_ARM_LDRS_PC_G2 localsym
-0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] @ 0xff
f8: R_ARM_LDRS_SB_G0 localsym
-0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] @ 0xff
fc: R_ARM_LDRS_SB_G1 localsym
-0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] @ 0xff
100: R_ARM_LDRS_SB_G2 localsym
-0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] @ 0xff
104: R_ARM_LDRS_PC_G1 localsym
-0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] @ 0xff
108: R_ARM_LDRS_PC_G2 localsym
-0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] @ 0xff
10c: R_ARM_LDRS_SB_G0 localsym
-0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] @ 0xff
110: R_ARM_LDRS_SB_G1 localsym
-0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] @ 0xff
114: R_ARM_LDRS_SB_G2 localsym
-0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] @ 0xff
118: R_ARM_LDRS_PC_G1 localsym
-0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] @ 0xff
11c: R_ARM_LDRS_PC_G2 localsym
-0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] @ 0xff
120: R_ARM_LDRS_SB_G0 localsym
-0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] @ 0xff
124: R_ARM_LDRS_SB_G1 localsym
-0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] @ 0xff
128: R_ARM_LDRS_SB_G2 localsym
-0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] @ 0xff
12c: R_ARM_LDRS_PC_G1 localsym
-0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] @ 0xff
130: R_ARM_LDRS_PC_G2 localsym
-0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] @ 0xff
134: R_ARM_LDRS_SB_G0 localsym
-0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] @ 0xff
138: R_ARM_LDRS_SB_G1 localsym
-0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] @ 0xff
13c: R_ARM_LDRS_SB_G2 localsym
-0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] @ 0xff
140: R_ARM_LDRS_PC_G1 localsym
-0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] @ 0xff
144: R_ARM_LDRS_PC_G2 localsym
-0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] @ 0xff
148: R_ARM_LDRS_SB_G0 localsym
-0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] @ 0xff
14c: R_ARM_LDRS_SB_G1 localsym
-0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] @ 0xff
150: R_ARM_LDRS_SB_G2 localsym
-0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] @ 0xff
154: R_ARM_LDRS_PC_G1 localsym
-0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] @ 0xff
158: R_ARM_LDRS_PC_G2 localsym
-0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] @ 0xff
15c: R_ARM_LDRS_SB_G0 localsym
-0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] @ 0xff
160: R_ARM_LDRS_SB_G1 localsym
-0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] ; 0xff
+0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] @ 0xff
164: R_ARM_LDRS_SB_G2 localsym
-0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] @ 0xffffff01
168: R_ARM_LDRS_PC_G1 localsym
-0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] @ 0xffffff01
16c: R_ARM_LDRS_PC_G2 localsym
-0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] @ 0xffffff01
170: R_ARM_LDRS_SB_G0 localsym
-0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] @ 0xffffff01
174: R_ARM_LDRS_SB_G1 localsym
-0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] @ 0xffffff01
178: R_ARM_LDRS_SB_G2 localsym
-0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] @ 0xffffff01
17c: R_ARM_LDRS_PC_G1 localsym
-0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] @ 0xffffff01
180: R_ARM_LDRS_PC_G2 localsym
-0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] @ 0xffffff01
184: R_ARM_LDRS_SB_G0 localsym
-0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] @ 0xffffff01
188: R_ARM_LDRS_SB_G1 localsym
-0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] @ 0xffffff01
18c: R_ARM_LDRS_SB_G2 localsym
-0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] @ 0xffffff01
190: R_ARM_LDRS_PC_G1 localsym
-0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] @ 0xffffff01
194: R_ARM_LDRS_PC_G2 localsym
-0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] @ 0xffffff01
198: R_ARM_LDRS_SB_G0 localsym
-0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] @ 0xffffff01
19c: R_ARM_LDRS_SB_G1 localsym
-0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] @ 0xffffff01
1a0: R_ARM_LDRS_SB_G2 localsym
-0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] @ 0xffffff01
1a4: R_ARM_LDRS_PC_G1 localsym
-0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] @ 0xffffff01
1a8: R_ARM_LDRS_PC_G2 localsym
-0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] @ 0xffffff01
1ac: R_ARM_LDRS_SB_G0 localsym
-0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] @ 0xffffff01
1b0: R_ARM_LDRS_SB_G1 localsym
-0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] @ 0xffffff01
1b4: R_ARM_LDRS_SB_G2 localsym
-0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] @ 0xffffff01
1b8: R_ARM_LDRS_PC_G1 localsym
-0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] @ 0xffffff01
1bc: R_ARM_LDRS_PC_G2 localsym
-0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] @ 0xffffff01
1c0: R_ARM_LDRS_SB_G0 localsym
-0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] @ 0xffffff01
1c4: R_ARM_LDRS_SB_G1 localsym
-0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] @ 0xffffff01
1c8: R_ARM_LDRS_SB_G2 localsym
-0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] @ 0xffffff01
1cc: R_ARM_LDRS_PC_G1 localsym
-0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] @ 0xffffff01
1d0: R_ARM_LDRS_PC_G2 localsym
-0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] @ 0xffffff01
1d4: R_ARM_LDRS_SB_G0 localsym
-0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] @ 0xffffff01
1d8: R_ARM_LDRS_SB_G1 localsym
-0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] ; 0xffffff01
+0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] @ 0xffffff01
1dc: R_ARM_LDRS_SB_G2 localsym
0[0-9a-f]+ <[^>]+> e3a00000 mov r0, #0
Disassembly of section .text:
0+0000 <[^>]+> e3a00000 ? mov r0, #0
0+0004 <[^>]+> e3e00003 ? mvn r0, #3
-0+0008 <[^>]+> e51f0010 ? ldr r0, \[pc, #-16\] ; 0+0 <[^>]+>
-0+000c <[^>]+> e51f0014 ? ldr r0, \[pc, #-20\] ; 0+0 <[^>]+>
+0+0008 <[^>]+> e51f0010 ? ldr r0, \[pc, #-16\] @ 0+0 <[^>]+>
+0+000c <[^>]+> e51f0014 ? ldr r0, \[pc, #-20\] @ 0+0 <[^>]+>
\.\.\.
0+1010 <[^>]+> e3a00008 ? mov r0, #8
-0+1014 <[^>]+> e59f00e4 ? ldr r0, \[pc, #228\] ; 0+1100 <[^>]+>
-0+1018 <[^>]+> e1a00000 ? nop ; \(mov r0, r0\)
-0+101c <[^>]+> e1a00000 ? nop ; \(mov r0, r0\)
+0+1014 <[^>]+> e59f00e4 ? ldr r0, \[pc, #228\] @ 0+1100 <[^>]+>
+0+1018 <[^>]+> e1a00000 ? nop @ \(mov r0, r0\)
+0+101c <[^>]+> e1a00000 ? nop @ \(mov r0, r0\)
.*: +file format .*arm.*
Disassembly of section .text:
-0+0000 <[^>]+> b351029c ? cmplt r1, #156, 4 ; 0xc0000009
+0+0000 <[^>]+> b351029c ? cmplt r1, #156, 4 @ 0xc0000009
0+14c <[^>]*> e1720004 ? cmn r2, r4
0+150 <[^>]*> e1750287 ? cmn r5, r7, lsl #5
0+154 <[^>]*> e1710113 ? cmn r1, r3, lsl r1
-0+158 <[^>]*> e330f00a ? teq r0, #10 ; <UNPREDICTABLE>
-0+15c <[^>]*> e132f004 ? teq r2, r4 ; <UNPREDICTABLE>
-0+160 <[^>]*> e135f287 ? teq r5, r7, lsl #5 ; <UNPREDICTABLE>
-0+164 <[^>]*> e131f113 ? teq r1, r3, lsl r1 ; <UNPREDICTABLE>
-0+168 <[^>]*> e370f00a ? cmn r0, #10 ; <UNPREDICTABLE>
-0+16c <[^>]*> e172f004 ? cmn r2, r4 ; <UNPREDICTABLE>
-0+170 <[^>]*> e175f287 ? cmn r5, r7, lsl #5 ; <UNPREDICTABLE>
-0+174 <[^>]*> e171f113 ? cmn r1, r3, lsl r1 ; <UNPREDICTABLE>
-0+178 <[^>]*> e350f00a ? cmp r0, #10 ; <UNPREDICTABLE>
-0+17c <[^>]*> e152f004 ? cmp r2, r4 ; <UNPREDICTABLE>
-0+180 <[^>]*> e155f287 ? cmp r5, r7, lsl #5 ; <UNPREDICTABLE>
-0+184 <[^>]*> e151f113 ? cmp r1, r3, lsl r1 ; <UNPREDICTABLE>
-0+188 <[^>]*> e310f00a ? tst r0, #10 ; <UNPREDICTABLE>
-0+18c <[^>]*> e112f004 ? tst r2, r4 ; <UNPREDICTABLE>
-0+190 <[^>]*> e115f287 ? tst r5, r7, lsl #5 ; <UNPREDICTABLE>
-0+194 <[^>]*> e111f113 ? tst r1, r3, lsl r1 ; <UNPREDICTABLE>
+0+158 <[^>]*> e330f00a ? teq r0, #10 @ <UNPREDICTABLE>
+0+15c <[^>]*> e132f004 ? teq r2, r4 @ <UNPREDICTABLE>
+0+160 <[^>]*> e135f287 ? teq r5, r7, lsl #5 @ <UNPREDICTABLE>
+0+164 <[^>]*> e131f113 ? teq r1, r3, lsl r1 @ <UNPREDICTABLE>
+0+168 <[^>]*> e370f00a ? cmn r0, #10 @ <UNPREDICTABLE>
+0+16c <[^>]*> e172f004 ? cmn r2, r4 @ <UNPREDICTABLE>
+0+170 <[^>]*> e175f287 ? cmn r5, r7, lsl #5 @ <UNPREDICTABLE>
+0+174 <[^>]*> e171f113 ? cmn r1, r3, lsl r1 @ <UNPREDICTABLE>
+0+178 <[^>]*> e350f00a ? cmp r0, #10 @ <UNPREDICTABLE>
+0+17c <[^>]*> e152f004 ? cmp r2, r4 @ <UNPREDICTABLE>
+0+180 <[^>]*> e155f287 ? cmp r5, r7, lsl #5 @ <UNPREDICTABLE>
+0+184 <[^>]*> e151f113 ? cmp r1, r3, lsl r1 @ <UNPREDICTABLE>
+0+188 <[^>]*> e310f00a ? tst r0, #10 @ <UNPREDICTABLE>
+0+18c <[^>]*> e112f004 ? tst r2, r4 @ <UNPREDICTABLE>
+0+190 <[^>]*> e115f287 ? tst r5, r7, lsl #5 @ <UNPREDICTABLE>
+0+194 <[^>]*> e111f113 ? tst r1, r3, lsl r1 @ <UNPREDICTABLE>
0+198 <[^>]*> e0000291 ? mul r0, r1, r2
0+19c <[^>]*> e0110392 ? muls r1, r2, r3
0+1a0 <[^>]*> 10000091 ? mulne r0, r1, r0
0+1d0 <[^>]*> 14954006 ? ldrne r4, \[r5\], #6
0+1d4 <[^>]*> e6b21003 ? ldrt r1, \[r2\], r3
0+1d8 <[^>]*> e6942425 ? ldr r2, \[r4\], r5, lsr #8
-0+1dc <[^>]*> e51f0008 ? ldr r0, \[pc, #-8\] ; 0+1dc <[^>]*>
+0+1dc <[^>]*> e51f0008 ? ldr r0, \[pc, #-8\] @ 0+1dc <[^>]*>
0+1e0 <[^>]*> e5d43000 ? ldrb r3, \[r4\]
0+1e4 <[^>]*> 14f85000 ? ldrbtne r5, \[r8\], #0
0+1e8 <[^>]*> e5810000 ? str r0, \[r1\]
0+200 <[^>]*> 14854006 ? strne r4, \[r5\], #6
0+204 <[^>]*> e6821003 ? str r1, \[r2\], r3
0+208 <[^>]*> e6a42425 ? strt r2, \[r4\], r5, lsr #8
-0+20c <[^>]*> e50f1004 ? str r1, \[pc, #-4\] ; 0+210 <[^>]*>
+0+20c <[^>]*> e50f1004 ? str r1, \[pc, #-4\] @ 0+210 <[^>]*>
0+210 <[^>]*> e5c71000 ? strb r1, \[r7\]
0+214 <[^>]*> e4e02000 ? strbt r2, \[r0\], #0
0+218 <[^>]*> e8900002 ? ldm r0, {r1}
0+280 <[^>]*> ae377007[ ]+wandnge[ ]+wr7, wr7, wr7
0+284 <[^>]*> ee080110[ ]+tmcr[ ]+wcgr0, r0
0+288 <[^>]*> ee1a1110[ ]+tmrc[ ]+r1, wcgr2
-0+28c <[^>]*> e1a00000[ ]+nop[ ]+; \(mov r0, r0\)
+0+28c <[^>]*> e1a00000[ ]+nop[ ]+@ \(mov r0, r0\)
Disassembly of section .text:
0+00 <[^>]*> e3a00000 ? mov r0, #0
-0+04 <[^>]*> e3a004ff ? mov r0, #-16777216 ; 0xff000000
+0+04 <[^>]*> e3a004ff ? mov r0, #-16777216 @ 0xff000000
0+08 <[^>]*> e3e00000 ? mvn r0, #0
-0+0c <[^>]*> e51f0004 ? ldr r0, \[pc, #-4\] ; 0+10 <[^>]*>
+0+0c <[^>]*> e51f0004 ? ldr r0, \[pc, #-4\] @ 0+10 <[^>]*>
0+10 <[^>]*> 0fff0000 ? .*
0+14 <[^>]*> e3a0e000 ? mov lr, #0
-0+18 <[^>]*> e3a0e8ff ? mov lr, #16711680 ; 0xff0000
-0+1c <[^>]*> e3e0e8ff ? mvn lr, #16711680 ; 0xff0000
-0+20 <[^>]*> e51fe004 ? ldr lr, \[pc, #-4\] ; 0+24 <[^>]*>
+0+18 <[^>]*> e3a0e8ff ? mov lr, #16711680 @ 0xff0000
+0+1c <[^>]*> e3e0e8ff ? mvn lr, #16711680 @ 0xff0000
+0+20 <[^>]*> e51fe004 ? ldr lr, \[pc, #-4\] @ 0+24 <[^>]*>
0+24 <[^>]*> 00fff000 ? .*
0+28 <[^>]*> 03a00000 ? moveq r0, #0
-0+2c <[^>]*> 03a00cff ? moveq r0, #65280 ; 0xff00
-0+30 <[^>]*> 03e00cff ? mvneq r0, #65280 ; 0xff00
-0+34 <[^>]*> 051f0004 ? ldreq r0, \[pc, #-4\] ; 0+38 <[^>]*>
+0+2c <[^>]*> 03a00cff ? moveq r0, #65280 @ 0xff00
+0+30 <[^>]*> 03e00cff ? mvneq r0, #65280 @ 0xff00
+0+34 <[^>]*> 051f0004 ? ldreq r0, \[pc, #-4\] @ 0+38 <[^>]*>
0+38 <[^>]*> 000fff00 ? .*
0+3c <[^>]*> 43a0b000 ? movmi fp, #0
-0+40 <[^>]*> 43a0b0ff ? movmi fp, #255 ; 0xff
-0+44 <[^>]*> 43e0b0ff ? mvnmi fp, #255 ; 0xff
-0+48 <[^>]*> 451fb004 ? ldrmi fp, \[pc, #-4\] ; 0+4c <[^>]*>
+0+40 <[^>]*> 43a0b0ff ? movmi fp, #255 @ 0xff
+0+44 <[^>]*> 43e0b0ff ? mvnmi fp, #255 @ 0xff
+0+48 <[^>]*> 451fb004 ? ldrmi fp, \[pc, #-4\] @ 0+4c <[^>]*>
0+4c <[^>]*> 0000fff0 ? .*
-0+50 <[^>]*> e59f0020 ? ldr r0, \[pc, #32\] ; 0+78 <[^>]*>
-0+54 <[^>]*> e59f301c ? ldr r3, \[pc, #28\] ; 0+78 <[^>]*>
-0+58 <[^>]*> e59f8018 ? ldr r8, \[pc, #24\] ; 0+78 <[^>]*>
-0+5c <[^>]*> e59fb014 ? ldr fp, \[pc, #20\] ; 0+78 <[^>]*>
-0+60 <[^>]*> e59fe010 ? ldr lr, \[pc, #16\] ; 0+78 <[^>]*>
-0+64 <[^>]*> e59f0010 ? ldr r0, \[pc, #16\] ; 0+7c <[^>]*>
-0+68 <[^>]*> e59f300c ? ldr r3, \[pc, #12\] ; 0+7c <[^>]*>
-0+6c <[^>]*> e59f8008 ? ldr r8, \[pc, #8\] ; 0+7c <[^>]*>
-0+70 <[^>]*> e59fb004 ? ldr fp, \[pc, #4\] ; 0+7c <[^>]*>
-0+74 <[^>]*> e51fe000 ? ldr lr, \[pc, #-0\] ; 0+7c <[^>]*>
+0+50 <[^>]*> e59f0020 ? ldr r0, \[pc, #32\] @ 0+78 <[^>]*>
+0+54 <[^>]*> e59f301c ? ldr r3, \[pc, #28\] @ 0+78 <[^>]*>
+0+58 <[^>]*> e59f8018 ? ldr r8, \[pc, #24\] @ 0+78 <[^>]*>
+0+5c <[^>]*> e59fb014 ? ldr fp, \[pc, #20\] @ 0+78 <[^>]*>
+0+60 <[^>]*> e59fe010 ? ldr lr, \[pc, #16\] @ 0+78 <[^>]*>
+0+64 <[^>]*> e59f0010 ? ldr r0, \[pc, #16\] @ 0+7c <[^>]*>
+0+68 <[^>]*> e59f300c ? ldr r3, \[pc, #12\] @ 0+7c <[^>]*>
+0+6c <[^>]*> e59f8008 ? ldr r8, \[pc, #8\] @ 0+7c <[^>]*>
+0+70 <[^>]*> e59fb004 ? ldr fp, \[pc, #4\] @ 0+7c <[^>]*>
+0+74 <[^>]*> e51fe000 ? ldr lr, \[pc, #-0\] @ 0+7c <[^>]*>
#pass
.*: +file format .*arm.*
Disassembly of section .text:
-0+00 <[^>]*> e59f0010 ? ldr r0, \[pc, #16\] ; 0+18 <[^>]*>
-0+04 <[^>]*> e1df00fc ? ldrsh r0, \[pc, #12\] ; 0+18 <[^>]*>
-0+08 <[^>]*> ed9f0a02 ? vldr s0, \[pc, #8\] ; 0+18 <[^>]*>
-0+0c <[^>]*> 4802 ? ldr r0, \[pc, #8\] ; \(0+18 <[^>]*>\)
-0+0e <[^>]*> 4802 ? ldr r0, \[pc, #8\] ; \(0+18 <[^>]*>\)
-0+10 <[^>]*> ed9f 0a01 ? vldr s0, \[pc, #4\] ; 0+18 <[^>]*>
-0+14 <[^>]*> f8df 0000 ? ldr\.w r0, \[pc\] ; 0+18 <[^>]*>
+0+00 <[^>]*> e59f0010 ? ldr r0, \[pc, #16\] @ 0+18 <[^>]*>
+0+04 <[^>]*> e1df00fc ? ldrsh r0, \[pc, #12\] @ 0+18 <[^>]*>
+0+08 <[^>]*> ed9f0a02 ? vldr s0, \[pc, #8\] @ 0+18 <[^>]*>
+0+0c <[^>]*> 4802 ? ldr r0, \[pc, #8\] @ \(0+18 <[^>]*>\)
+0+0e <[^>]*> 4802 ? ldr r0, \[pc, #8\] @ \(0+18 <[^>]*>\)
+0+10 <[^>]*> ed9f 0a01 ? vldr s0, \[pc, #4\] @ 0+18 <[^>]*>
+0+14 <[^>]*> f8df 0000 ? ldr\.w r0, \[pc\] @ 0+18 <[^>]*>
#...
Disassembly of section [^>]+:
0+00 <[^>]+> f8d1 1005 ldr.w r1, \[r1, #5\]
0+04 <[^>]+> f852 1f05 ldr.w r1, \[r2, #5\]!
-0+08 <[^>]+> f8df 1005 ldr.w r1, \[pc, #5\] ; 0+11 <[^>]+0x11>
+0+08 <[^>]+> f8df 1005 ldr.w r1, \[pc, #5\] @ 0+11 <[^>]+0x11>
0+0c <[^>]+> f8d1 f005 ldr.w pc, \[r1, #5\]
-0+10 <[^>]+> f8df f004 ldr.w pc, \[pc, #4\] ; 0+18 <[^>]+0x18>
+0+10 <[^>]+> f8df f004 ldr.w pc, \[pc, #4\] @ 0+18 <[^>]+0x18>
0+14 <[^>]+> bfa2 ittt ge
-0+16 <[^>]+> 4901 ldrge r1, \[pc, #4\] ; \(0+1c <[^>]+0x1c>\)
+0+16 <[^>]+> 4901 ldrge r1, \[pc, #4\] @ \(0+1c <[^>]+0x1c>\)
0+18 <[^>]+> bf00 nopge
0+1a <[^>]+> bf00 nopge
0+1c <[^>]+> bfa8 it ge
-0+1e <[^>]+> f8df f004 ldrge.w pc, \[pc, #4\] ; 0+24 <[^>]+0x24>
+0+1e <[^>]+> f8df f004 ldrge.w pc, \[pc, #4\] @ 0+24 <[^>]+0x24>
0+22 <[^>]+> bfa2 ittt ge
-0+24 <[^>]+> f85f 1ab8 ldrge.w r1, \[pc, #-2744\] ; fffff570 <[^>]+>
+0+24 <[^>]+> f85f 1ab8 ldrge.w r1, \[pc, #-2744\] @ fffff570 <[^>]+>
0+28 <[^>]+> bf00 nopge
0+2a <[^>]+> bf00 nopge
0+2c <[^>]+> bfa8 it ge
-0+2e <[^>]+> f85f fab6 ldrge.w pc, \[pc, #-2742\] ; fffff57a <[^>]+>
-0+32 <[^>]+> f85f 1ab9 ldr.w r1, \[pc, #-2745\] ; fffff57b <[^>]+>
-0+36 <[^>]+> f85f fab6 ldr.w pc, \[pc, #-2742\] ; fffff582 <[^>]+>
+0+2e <[^>]+> f85f fab6 ldrge.w pc, \[pc, #-2742\] @ fffff57a <[^>]+>
+0+32 <[^>]+> f85f 1ab9 ldr.w r1, \[pc, #-2745\] @ fffff57b <[^>]+>
+0+36 <[^>]+> f85f fab6 ldr.w pc, \[pc, #-2742\] @ fffff582 <[^>]+>
0+3a <[^>]+> bfa2 ittt ge
0+3c <[^>]+> 5851 ldrge r1, \[r2, r1\]
0+3e <[^>]+> bf00 nopge
Disassembly of section \.text:
0+00 <[^>]+> e5911005 ldr r1, \[r1, #5\]
0+04 <[^>]+> e5b21005 ldr r1, \[r2, #5\]!
-0+08 <[^>]+> e59f1005 ldr r1, \[pc, #5\] ; 0+15 <[^>]+0x15>
+0+08 <[^>]+> e59f1005 ldr r1, \[pc, #5\] @ 0+15 <[^>]+0x15>
0+0c <[^>]+> e591f005 ldr pc, \[r1, #5\]
-0+10 <[^>]+> e59ff004 ldr pc, \[pc, #4\] ; 0+1c <[^>]+0x1c>
-0+14 <[^>]+> e51ffabc ldr pc, \[pc, #-2748\] ; fffff560 <[^>]+>
-0+18 <[^>]+> e51f1abf ldr r1, \[pc, #-2751\] ; fffff561 <[^>]+>
+0+10 <[^>]+> e59ff004 ldr pc, \[pc, #4\] @ 0+1c <[^>]+0x1c>
+0+14 <[^>]+> e51ffabc ldr pc, \[pc, #-2748\] @ fffff560 <[^>]+>
+0+18 <[^>]+> e51f1abf ldr r1, \[pc, #-2751\] @ fffff561 <[^>]+>
0+1c <[^>]+> e7911002 ldr r1, \[r1, r2\]
0+20 <[^>]+> e79f2002 ldr r2, \[pc, r2\]
0+24 <[^>]+> e7b21003 ldr r1, \[r2, r3\]!
0+28 <[^>]+> e791100c ldr r1, \[r1, ip\]
0+2c <[^>]+> e581100a str r1, \[r1, #10\]
-0+30 <[^>]+> e58f100a str r1, \[pc, #10\] ; 0+42 <[^>]+0x42>
+0+30 <[^>]+> e58f100a str r1, \[pc, #10\] @ 0+42 <[^>]+0x42>
0+34 <[^>]+> e5a2100a str r1, \[r2, #10\]!
0+38 <[^>]+> e7811002 str r1, \[r1, r2\]
0+3c <[^>]+> e78f1002 str r1, \[pc, r2\]
0+08c <[^>]*> e4e21000 strbt r1, \[r2\], #0
0+090 <[^>]*> 5d465300 stclpl 3, cr5, \[r6, #-0\]
0+094 <[^>]*> 5dc65300 stclpl 3, cr5, \[r6\]
-0+098 <[^>]*> e59f0004 ldr r0, \[pc, #4\] ; .*
-0+09c <[^>]*> e59f0000 ldr r0, \[pc\] ; .*
-0+0a0 <[^>]*> e51f0004 ldr r0, \[pc, #-4\] ; .*
+0+098 <[^>]*> e59f0004 ldr r0, \[pc, #4\] @ .*
+0+09c <[^>]*> e59f0000 ldr r0, \[pc\] @ .*
+0+0a0 <[^>]*> e51f0004 ldr r0, \[pc, #-4\] @ .*
0+0a4 <[^>]*> 00000000 .word 0x00000000
.*: +file format .*arm.*
Disassembly of section .text:
-(0[0-9a-f]+) <[^>]+> e51f1008 ldr r1, \[pc, #-8\] ; \1 <[^>]*>
+(0[0-9a-f]+) <[^>]+> e51f1008 ldr r1, \[pc, #-8\] @ \1 <[^>]*>
0[0-9a-f]+ <[^>]+> e79f1002 ldr r1, \[pc, r2\]
0[0-9a-f]+ <[^>]+> e7df1002 ldrb r1, \[pc, r2\]
0[0-9a-f]+ <[^>]+> e18f00d2 ldrd r0, \[pc, r2\]
0[0-9a-f]+ <[^>]+> e19f10b2 ldrh r1, \[pc, r2\]
0[0-9a-f]+ <[^>]+> e19f10d2 ldrsb r1, \[pc, r2\]
0[0-9a-f]+ <[^>]+> e19f10f2 ldrsh r1, \[pc, r2\]
-(0[0-9a-f]+) <[^>]+> f55ff008 pld \[pc, #-8\] ; \1 <[^>]*>
+(0[0-9a-f]+) <[^>]+> f55ff008 pld \[pc, #-8\] @ \1 <[^>]*>
0[0-9a-f]+ <[^>]+> f7dff001 pld \[pc, r1\]
-(0[0-9a-f]+) <[^>]+> f45ff008 pli \[pc, #-8\] ; \1 <[^>]*>
+(0[0-9a-f]+) <[^>]+> f45ff008 pli \[pc, #-8\] @ \1 <[^>]*>
0[0-9a-f]+ <[^>]+> f6dff001 pli \[pc, r1\]
-0[0-9a-f]+ <[^>]+> e58f1004 str r1, \[pc, #4\] ; 0+038 <[^>]*>
+0[0-9a-f]+ <[^>]+> e58f1004 str r1, \[pc, #4\] @ 0+038 <[^>]*>
0[0-9a-f]+ <[^>]+> e78f1002 str r1, \[pc, r2\]
0[0-9a-f]+ <[^>]+> e7cf1002 strb r1, \[pc, r2\]
0[0-9a-f]+ <[^>]+> e18f00f2 strd r0, \[pc, r2\]
Disassembly of section .text:
-[^>]*> 4800 ldr r0, \[pc, #0\] ; \(00000004 [^>]*>\)
-[^>]*> 4801 ldr r0, \[pc, #4\] ; \(00000008 [^>]*>\)
+[^>]*> 4800 ldr r0, \[pc, #0\] @ \(00000004 [^>]*>\)
+[^>]*> 4801 ldr r0, \[pc, #4\] @ \(00000008 [^>]*>\)
#...
Disassembly of section .text:
-[^>]*> f240 0030 movw r0, #48 ; 0x30
-[^>]*> 4800 ldr r0, \[pc, #0\] ; \(00000008 [^>]*>\)
+[^>]*> f240 0030 movw r0, #48 @ 0x30
+[^>]*> 4800 ldr r0, \[pc, #0\] @ \(00000008 [^>]*>\)
#...
Disassembly of section .text:
-[^>]*> f04f 0030 mov.w r0, #48 ; 0x30
-[^>]*> f04f 40e0 mov.w r0, #1879048192 ; 0x70000000
+[^>]*> f04f 0030 mov.w r0, #48 @ 0x30
+[^>]*> f04f 40e0 mov.w r0, #1879048192 @ 0x70000000
Disassembly of section .text:
0+0 <[^>]*> e8bd8030 ? pop {r4, r5, pc}
-0+4 <[^>]*> e1a00000 ? nop ; \(mov r0, r0\)
-0+8 <[^>]*> e1a00000 ? nop ; \(mov r0, r0\)
-0+c <[^>]*> e1a00000 ? nop ; \(mov r0, r0\)
+0+4 <[^>]*> e1a00000 ? nop @ \(mov r0, r0\)
+0+8 <[^>]*> e1a00000 ? nop @ \(mov r0, r0\)
+0+c <[^>]*> e1a00000 ? nop @ \(mov r0, r0\)
Disassembly of section .code:
00000000 <.code>:
- 0: e1a00000 nop ; \(mov r0, r0\)
+ 0: e1a00000 nop @ \(mov r0, r0\)
Disassembly of section .tcode:
00000000 <.tcode>:
- 0: 46c0 nop ; \(mov r8, r8\)
+ 0: 46c0 nop @ \(mov r8, r8\)
Disassembly of section .text:
00000000 <foo>:
- 0: e1a00000 nop ; \(mov r0, r0\)
+ 0: e1a00000 nop @ \(mov r0, r0\)
4: 64636261 .word 0x64636261
- 8: e1a00000 nop ; \(mov r0, r0\)
+ 8: e1a00000 nop @ \(mov r0, r0\)
c: 00636261 .word 0x00636261
- 10: e1a00000 nop ; \(mov r0, r0\)
+ 10: e1a00000 nop @ \(mov r0, r0\)
14: 00676665 .word 0x00676665
- 18: e1a00000 nop ; \(mov r0, r0\)
+ 18: e1a00000 nop @ \(mov r0, r0\)
1c: 006a6968 .word 0x006a6968
- 20: e1a00000 nop ; \(mov r0, r0\)
+ 20: e1a00000 nop @ \(mov r0, r0\)
24: 0000006b .word 0x0000006b
- 28: e1a00000 nop ; \(mov r0, r0\)
+ 28: e1a00000 nop @ \(mov r0, r0\)
2c: 0000006c .word 0x0000006c
30: 00000000 .word 0x00000000
- 34: e1a00000 nop ; \(mov r0, r0\)
+ 34: e1a00000 nop @ \(mov r0, r0\)
38: 0000006d .word 0x0000006d
...
- 48: e1a00000 nop ; \(mov r0, r0\)
+ 48: e1a00000 nop @ \(mov r0, r0\)
4c: 3fc00000 .word 0x3fc00000
- 50: e1a00000 nop ; \(mov r0, r0\)
+ 50: e1a00000 nop @ \(mov r0, r0\)
54: 40200000 .word 0x40200000
- 58: e1a00000 nop ; \(mov r0, r0\)
+ 58: e1a00000 nop @ \(mov r0, r0\)
5c: 00000000 .word 0x00000000
60: 400c0000 .word 0x400c0000
- 64: e1a00000 nop ; \(mov r0, r0\)
+ 64: e1a00000 nop @ \(mov r0, r0\)
68: 00000000 .word 0x00000000
6c: 40120000 .word 0x40120000
- 70: e1a00000 nop ; \(mov r0, r0\)
+ 70: e1a00000 nop @ \(mov r0, r0\)
74: 00000004 .word 0x00000004
78: 00000004 .word 0x00000004
7c: 00000004 .word 0x00000004
80: 00000004 .word 0x00000004
- 84: e1a00000 nop ; \(mov r0, r0\)
+ 84: e1a00000 nop @ \(mov r0, r0\)
88: 00000000 .word 0x00000000
- 8c: e1a00000 nop ; \(mov r0, r0\)
+ 8c: e1a00000 nop @ \(mov r0, r0\)
90: 00000000 .word 0x00000000
- 94: e1a00000 nop ; \(mov r0, r0\)
+ 94: e1a00000 nop @ \(mov r0, r0\)
98: 00000000 .word 0x00000000
- 9c: e1a00000 nop ; \(mov r0, r0\)
+ 9c: e1a00000 nop @ \(mov r0, r0\)
a0: 7778797a .word 0x7778797a
- a4: e1a00000 nop ; \(mov r0, r0\)
- a8: e1a00000 nop ; \(mov r0, r0\)
- ac: e51f0000 ldr r0, \[pc, #-0\] ; b4 <string\+0x4>
+ a4: e1a00000 nop @ \(mov r0, r0\)
+ a8: e1a00000 nop @ \(mov r0, r0\)
+ ac: e51f0000 ldr r0, \[pc, #-0\] @ b4 <string\+0x4>
000000b0 <string>:
b0: 6261 .short 0x6261
b2: 63 .byte 0x63
Disassembly of section .text.f1:
00000000 <f1>:
- 0: e1a00000 nop ; \(mov r0, r0\)
- 4: e1a00000 nop ; \(mov r0, r0\)
+ 0: e1a00000 nop @ \(mov r0, r0\)
+ 4: e1a00000 nop @ \(mov r0, r0\)
00000008 <f1a>:
- 8: e1a00000 nop ; \(mov r0, r0\)
+ 8: e1a00000 nop @ \(mov r0, r0\)
Disassembly of section .text.f2:
00000000 <f2>:
- 0: e1a00000 nop ; \(mov r0, r0\)
+ 0: e1a00000 nop @ \(mov r0, r0\)
4: 00000001 .word 0x00000001
00000008 <f2a>:
- 8: e1a00000 nop ; \(mov r0, r0\)
+ 8: e1a00000 nop @ \(mov r0, r0\)
Disassembly of section .text:
0+00 <foo>:
- 0: e1a00000 nop ; \(mov r0, r0\)
- 4: 46c0 nop ; \(mov r8, r8\)
- 6: 46c0 nop ; \(mov r8, r8\)
+ 0: e1a00000 nop @ \(mov r0, r0\)
+ 4: 46c0 nop @ \(mov r8, r8\)
+ 6: 46c0 nop @ \(mov r8, r8\)
8: 00000002 .word 0x00000002
c: 00010001 .word 0x00010001
10: 0003 .short 0x0003
- 12: 46c0 nop ; \(mov r8, r8\)
- 14: 46c0 nop ; \(mov r8, r8\)
+ 12: 46c0 nop @ \(mov r8, r8\)
+ 14: 46c0 nop @ \(mov r8, r8\)
16: 0001 .short 0x0001
18: ebfffff8 bl 0 <foo>
1c: 0008 .short 0x0008
Disassembly of section .text:
0+00 <foo>:
- 0: e1a00000 nop ; \(mov r0, r0\)
- 4: 46c0 nop ; \(mov r8, r8\)
- 6: 46c0 nop ; \(mov r8, r8\)
+ 0: e1a00000 nop @ \(mov r0, r0\)
+ 4: 46c0 nop @ \(mov r8, r8\)
+ 6: 46c0 nop @ \(mov r8, r8\)
8: 00000002 .word 0x00000002
c: 00010001 .word 0x00010001
10: 0003 .short 0x0003
- 12: 46c0 nop ; \(mov r8, r8\)
- 14: 46c0 nop ; \(mov r8, r8\)
+ 12: 46c0 nop @ \(mov r8, r8\)
+ 14: 46c0 nop @ \(mov r8, r8\)
16: 0001 .short 0x0001
18: ebfffff8 bl 0 <foo>
1c: 0008 .short 0x0008
Disassembly of section .text:
-0+000 <.*> fe011a10 mcr2 10, 0, r1, cr1, cr0, \{0\} ; <UNPREDICTABLE>
-0+004 <.*> fe011b10 mcr2 11, 0, r1, cr1, cr0, \{0\} ; <UNPREDICTABLE>
-0+008 <.*> fe811a10 mcr2 10, 4, r1, cr1, cr0, \{0\} ; <UNPREDICTABLE>
-0+00c <.*> fe811b10 mcr2 11, 4, r1, cr1, cr0, \{0\} ; <UNPREDICTABLE>
-0+010 <.*> fe811a50 mcr2 10, 4, r1, cr1, cr0, \{2\} ; <UNPREDICTABLE>
-0+014 <.*> fe811b50 mcr2 11, 4, r1, cr1, cr0, \{2\} ; <UNPREDICTABLE>
-0+018 <.*> fefb0ae0 ; <UNDEFINED> instruction: 0xfefb0ae0
-0+01c <.*> fefb0be0 ; <UNDEFINED> instruction: 0xfefb0be0
-0+020 <.*> fefb0ae0 ; <UNDEFINED> instruction: 0xfefb0ae0
-0+024 <.*> fefb0be0 ; <UNDEFINED> instruction: 0xfefb0be0
-0+028 <.*> fef80ae0 ; <UNDEFINED> instruction: 0xfef80ae0
-0+02c <.*> fef80be0 ; <UNDEFINED> instruction: 0xfef80be0
-0+030 <.*> fef90ae0 ; <UNDEFINED> instruction: 0xfef90ae0
-0+034 <.*> fef90be0 ; <UNDEFINED> instruction: 0xfef90be0
-0+038 <.*> fefa0ae0 ; <UNDEFINED> instruction: 0xfefa0ae0
-0+03c <.*> fefa0be0 ; <UNDEFINED> instruction: 0xfefa0be0
+0+000 <.*> fe011a10 mcr2 10, 0, r1, cr1, cr0, \{0\} @ <UNPREDICTABLE>
+0+004 <.*> fe011b10 mcr2 11, 0, r1, cr1, cr0, \{0\} @ <UNPREDICTABLE>
+0+008 <.*> fe811a10 mcr2 10, 4, r1, cr1, cr0, \{0\} @ <UNPREDICTABLE>
+0+00c <.*> fe811b10 mcr2 11, 4, r1, cr1, cr0, \{0\} @ <UNPREDICTABLE>
+0+010 <.*> fe811a50 mcr2 10, 4, r1, cr1, cr0, \{2\} @ <UNPREDICTABLE>
+0+014 <.*> fe811b50 mcr2 11, 4, r1, cr1, cr0, \{2\} @ <UNPREDICTABLE>
+0+018 <.*> fefb0ae0 @ <UNDEFINED> instruction: 0xfefb0ae0
+0+01c <.*> fefb0be0 @ <UNDEFINED> instruction: 0xfefb0be0
+0+020 <.*> fefb0ae0 @ <UNDEFINED> instruction: 0xfefb0ae0
+0+024 <.*> fefb0be0 @ <UNDEFINED> instruction: 0xfefb0be0
+0+028 <.*> fef80ae0 @ <UNDEFINED> instruction: 0xfef80ae0
+0+02c <.*> fef80be0 @ <UNDEFINED> instruction: 0xfef80be0
+0+030 <.*> fef90ae0 @ <UNDEFINED> instruction: 0xfef90ae0
+0+034 <.*> fef90be0 @ <UNDEFINED> instruction: 0xfef90be0
+0+038 <.*> fefa0ae0 @ <UNDEFINED> instruction: 0xfefa0ae0
+0+03c <.*> fefa0be0 @ <UNDEFINED> instruction: 0xfefa0be0
Disassembly of section .text:
-0+000 <.*> fe011a10 mcr2 10, 0, r1, cr1, cr0, \{0\} ; <UNPREDICTABLE>
-0+004 <.*> fe011b10 mcr2 11, 0, r1, cr1, cr0, \{0\} ; <UNPREDICTABLE>
-0+008 <.*> fe811a10 mcr2 10, 4, r1, cr1, cr0, \{0\} ; <UNPREDICTABLE>
-0+00c <.*> fe811b10 mcr2 11, 4, r1, cr1, cr0, \{0\} ; <UNPREDICTABLE>
-0+010 <.*> fe811a50 mcr2 10, 4, r1, cr1, cr0, \{2\} ; <UNPREDICTABLE>
-0+014 <.*> fe811b50 mcr2 11, 4, r1, cr1, cr0, \{2\} ; <UNPREDICTABLE>
-0+018 <.*> fefb0ae0 ; <UNDEFINED> instruction: 0xfefb0ae0
-0+01c <.*> fefb0be0 ; <UNDEFINED> instruction: 0xfefb0be0
-0+020 <.*> fefb0ae0 ; <UNDEFINED> instruction: 0xfefb0ae0
-0+024 <.*> fefb0be0 ; <UNDEFINED> instruction: 0xfefb0be0
-0+028 <.*> fef80ae0 ; <UNDEFINED> instruction: 0xfef80ae0
-0+02c <.*> fef80be0 ; <UNDEFINED> instruction: 0xfef80be0
-0+030 <.*> fef90ae0 ; <UNDEFINED> instruction: 0xfef90ae0
-0+034 <.*> fef90be0 ; <UNDEFINED> instruction: 0xfef90be0
-0+038 <.*> fefa0ae0 ; <UNDEFINED> instruction: 0xfefa0ae0
-0+03c <.*> fefa0be0 ; <UNDEFINED> instruction: 0xfefa0be0
+0+000 <.*> fe011a10 mcr2 10, 0, r1, cr1, cr0, \{0\} @ <UNPREDICTABLE>
+0+004 <.*> fe011b10 mcr2 11, 0, r1, cr1, cr0, \{0\} @ <UNPREDICTABLE>
+0+008 <.*> fe811a10 mcr2 10, 4, r1, cr1, cr0, \{0\} @ <UNPREDICTABLE>
+0+00c <.*> fe811b10 mcr2 11, 4, r1, cr1, cr0, \{0\} @ <UNPREDICTABLE>
+0+010 <.*> fe811a50 mcr2 10, 4, r1, cr1, cr0, \{2\} @ <UNPREDICTABLE>
+0+014 <.*> fe811b50 mcr2 11, 4, r1, cr1, cr0, \{2\} @ <UNPREDICTABLE>
+0+018 <.*> fefb0ae0 @ <UNDEFINED> instruction: 0xfefb0ae0
+0+01c <.*> fefb0be0 @ <UNDEFINED> instruction: 0xfefb0be0
+0+020 <.*> fefb0ae0 @ <UNDEFINED> instruction: 0xfefb0ae0
+0+024 <.*> fefb0be0 @ <UNDEFINED> instruction: 0xfefb0be0
+0+028 <.*> fef80ae0 @ <UNDEFINED> instruction: 0xfef80ae0
+0+02c <.*> fef80be0 @ <UNDEFINED> instruction: 0xfef80be0
+0+030 <.*> fef90ae0 @ <UNDEFINED> instruction: 0xfef90ae0
+0+034 <.*> fef90be0 @ <UNDEFINED> instruction: 0xfef90be0
+0+038 <.*> fefa0ae0 @ <UNDEFINED> instruction: 0xfefa0ae0
+0+03c <.*> fefa0be0 @ <UNDEFINED> instruction: 0xfefa0be0
0+00 <[^>]*> e10f4000 mrs r4, CPSR
0+04 <[^>]*> e10f5000 mrs r5, CPSR
0+08 <[^>]*> e14f6000 mrs r6, SPSR
-0+0c <[^>]*> e328f101 msr CPSR_f, #1073741824 ; 0x40000000
-0+10 <[^>]*> e328f202 msr CPSR_f, #536870912 ; 0x20000000
-0+14 <[^>]*> e369f201 msr SPSR_fc, #268435456 ; 0x10000000
+0+0c <[^>]*> e328f101 msr CPSR_f, #1073741824 @ 0x40000000
+0+10 <[^>]*> e328f202 msr CPSR_f, #536870912 @ 0x20000000
+0+14 <[^>]*> e369f201 msr SPSR_fc, #268435456 @ 0x10000000
0+18 <[^>]*> e128f004 msr CPSR_f, r4
0+1c <[^>]*> e128f005 msr CPSR_f, r5
0+20 <[^>]*> e169f006 msr SPSR_fc, r6
0+00 <[^>]*> e10f4000 mrs r4, CPSR
0+04 <[^>]*> e10f5000 mrs r5, CPSR
0+08 <[^>]*> e14f6000 mrs r6, SPSR
-0+0c <[^>]*> e32cf101 msr CPSR_fs, #1073741824 ; 0x40000000
-0+10 <[^>]*> e328f202 msr CPSR_f, #536870912 ; 0x20000000
-0+14 <[^>]*> e369f201 msr SPSR_fc, #268435456 ; 0x10000000
+0+0c <[^>]*> e32cf101 msr CPSR_fs, #1073741824 @ 0x40000000
+0+10 <[^>]*> e328f202 msr CPSR_f, #536870912 @ 0x20000000
+0+14 <[^>]*> e369f201 msr SPSR_fc, #268435456 @ 0x10000000
0+18 <[^>]*> e128f004 msr CPSR_f, r4
0+1c <[^>]*> e128f005 msr CPSR_f, r5
0+20 <[^>]*> e169f006 msr SPSR_fc, r6
.*: +file format .*arm.*
Disassembly of section .text:
-00000000 <[^>]*> e328f113 msr CPSR_f, #-1073741820 ; 0xc0000004
-00000004 <[^>]*> e324f113 msr CPSR_s, #-1073741820 ; 0xc0000004
-00000008 <[^>]*> e328f113 msr CPSR_f, #-1073741820 ; 0xc0000004
-0000000c <[^>]*> e32cf113 msr CPSR_fs, #-1073741820 ; 0xc0000004
-00000010 <[^>]*> e329f113 msr CPSR_fc, #-1073741820 ; 0xc0000004
-00000014 <[^>]*> e324f113 msr CPSR_s, #-1073741820 ; 0xc0000004
-00000018 <[^>]*> e328f113 msr CPSR_f, #-1073741820 ; 0xc0000004
-0000001c <[^>]*> e321f113 msr CPSR_c, #-1073741820 ; 0xc0000004
-00000020 <[^>]*> e322f113 msr CPSR_x, #-1073741820 ; 0xc0000004
-00000024 <[^>]*> e32cf113 msr CPSR_fs, #-1073741820 ; 0xc0000004
-00000028 <[^>]*> e32af113 msr CPSR_fx, #-1073741820 ; 0xc0000004
-0000002c <[^>]*> e329f113 msr CPSR_fc, #-1073741820 ; 0xc0000004
-00000030 <[^>]*> e32cf113 msr CPSR_fs, #-1073741820 ; 0xc0000004
-00000034 <[^>]*> e326f113 msr CPSR_sx, #-1073741820 ; 0xc0000004
-00000038 <[^>]*> e325f113 msr CPSR_sc, #-1073741820 ; 0xc0000004
-0000003c <[^>]*> e32af113 msr CPSR_fx, #-1073741820 ; 0xc0000004
-00000040 <[^>]*> e326f113 msr CPSR_sx, #-1073741820 ; 0xc0000004
-00000044 <[^>]*> e323f113 msr CPSR_xc, #-1073741820 ; 0xc0000004
-00000048 <[^>]*> e329f113 msr CPSR_fc, #-1073741820 ; 0xc0000004
-0000004c <[^>]*> e325f113 msr CPSR_sc, #-1073741820 ; 0xc0000004
-00000050 <[^>]*> e323f113 msr CPSR_xc, #-1073741820 ; 0xc0000004
-00000054 <[^>]*> e32ef113 msr CPSR_fsx, #-1073741820 ; 0xc0000004
-00000058 <[^>]*> e32df113 msr CPSR_fsc, #-1073741820 ; 0xc0000004
-0000005c <[^>]*> e32ef113 msr CPSR_fsx, #-1073741820 ; 0xc0000004
-00000060 <[^>]*> e32bf113 msr CPSR_fxc, #-1073741820 ; 0xc0000004
-00000064 <[^>]*> e32df113 msr CPSR_fsc, #-1073741820 ; 0xc0000004
-00000068 <[^>]*> e32bf113 msr CPSR_fxc, #-1073741820 ; 0xc0000004
-0000006c <[^>]*> e32ef113 msr CPSR_fsx, #-1073741820 ; 0xc0000004
-00000070 <[^>]*> e32df113 msr CPSR_fsc, #-1073741820 ; 0xc0000004
-00000074 <[^>]*> e32ef113 msr CPSR_fsx, #-1073741820 ; 0xc0000004
-00000078 <[^>]*> e327f113 msr CPSR_sxc, #-1073741820 ; 0xc0000004
-0000007c <[^>]*> e32df113 msr CPSR_fsc, #-1073741820 ; 0xc0000004
-00000080 <[^>]*> e327f113 msr CPSR_sxc, #-1073741820 ; 0xc0000004
-00000084 <[^>]*> e32ef113 msr CPSR_fsx, #-1073741820 ; 0xc0000004
-00000088 <[^>]*> e32bf113 msr CPSR_fxc, #-1073741820 ; 0xc0000004
-0000008c <[^>]*> e32ef113 msr CPSR_fsx, #-1073741820 ; 0xc0000004
-00000090 <[^>]*> e327f113 msr CPSR_sxc, #-1073741820 ; 0xc0000004
-00000094 <[^>]*> e32bf113 msr CPSR_fxc, #-1073741820 ; 0xc0000004
-00000098 <[^>]*> e327f113 msr CPSR_sxc, #-1073741820 ; 0xc0000004
-0000009c <[^>]*> e32df113 msr CPSR_fsc, #-1073741820 ; 0xc0000004
-000000a0 <[^>]*> e32bf113 msr CPSR_fxc, #-1073741820 ; 0xc0000004
-000000a4 <[^>]*> e32df113 msr CPSR_fsc, #-1073741820 ; 0xc0000004
-000000a8 <[^>]*> e327f113 msr CPSR_sxc, #-1073741820 ; 0xc0000004
-000000ac <[^>]*> e32bf113 msr CPSR_fxc, #-1073741820 ; 0xc0000004
-000000b0 <[^>]*> e327f113 msr CPSR_sxc, #-1073741820 ; 0xc0000004
-000000b4 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-000000b8 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-000000bc <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-000000c0 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-000000c4 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-000000c8 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-000000cc <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-000000d0 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-000000d4 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-000000d8 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-000000dc <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-000000e0 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-000000e4 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-000000e8 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-000000ec <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-000000f0 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-000000f4 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-000000f8 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-000000fc <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-00000100 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-00000104 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-00000108 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-0000010c <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-00000110 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004
-00000114 <[^>]*> e369f113 msr SPSR_fc, #-1073741820 ; 0xc0000004
-00000118 <[^>]*> e364f113 msr SPSR_s, #-1073741820 ; 0xc0000004
-0000011c <[^>]*> e368f113 msr SPSR_f, #-1073741820 ; 0xc0000004
-00000120 <[^>]*> e361f113 msr SPSR_c, #-1073741820 ; 0xc0000004
-00000124 <[^>]*> e362f113 msr SPSR_x, #-1073741820 ; 0xc0000004
-00000128 <[^>]*> e36cf113 msr SPSR_fs, #-1073741820 ; 0xc0000004
-0000012c <[^>]*> e36af113 msr SPSR_fx, #-1073741820 ; 0xc0000004
-00000130 <[^>]*> e369f113 msr SPSR_fc, #-1073741820 ; 0xc0000004
-00000134 <[^>]*> e36cf113 msr SPSR_fs, #-1073741820 ; 0xc0000004
-00000138 <[^>]*> e366f113 msr SPSR_sx, #-1073741820 ; 0xc0000004
-0000013c <[^>]*> e365f113 msr SPSR_sc, #-1073741820 ; 0xc0000004
-00000140 <[^>]*> e36af113 msr SPSR_fx, #-1073741820 ; 0xc0000004
-00000144 <[^>]*> e366f113 msr SPSR_sx, #-1073741820 ; 0xc0000004
-00000148 <[^>]*> e363f113 msr SPSR_xc, #-1073741820 ; 0xc0000004
-0000014c <[^>]*> e369f113 msr SPSR_fc, #-1073741820 ; 0xc0000004
-00000150 <[^>]*> e365f113 msr SPSR_sc, #-1073741820 ; 0xc0000004
-00000154 <[^>]*> e363f113 msr SPSR_xc, #-1073741820 ; 0xc0000004
-00000158 <[^>]*> e36ef113 msr SPSR_fsx, #-1073741820 ; 0xc0000004
-0000015c <[^>]*> e36df113 msr SPSR_fsc, #-1073741820 ; 0xc0000004
-00000160 <[^>]*> e36ef113 msr SPSR_fsx, #-1073741820 ; 0xc0000004
-00000164 <[^>]*> e36bf113 msr SPSR_fxc, #-1073741820 ; 0xc0000004
-00000168 <[^>]*> e36df113 msr SPSR_fsc, #-1073741820 ; 0xc0000004
-0000016c <[^>]*> e36bf113 msr SPSR_fxc, #-1073741820 ; 0xc0000004
-00000170 <[^>]*> e36ef113 msr SPSR_fsx, #-1073741820 ; 0xc0000004
-00000174 <[^>]*> e36df113 msr SPSR_fsc, #-1073741820 ; 0xc0000004
-00000178 <[^>]*> e36ef113 msr SPSR_fsx, #-1073741820 ; 0xc0000004
-0000017c <[^>]*> e367f113 msr SPSR_sxc, #-1073741820 ; 0xc0000004
-00000180 <[^>]*> e36df113 msr SPSR_fsc, #-1073741820 ; 0xc0000004
-00000184 <[^>]*> e367f113 msr SPSR_sxc, #-1073741820 ; 0xc0000004
-00000188 <[^>]*> e36ef113 msr SPSR_fsx, #-1073741820 ; 0xc0000004
-0000018c <[^>]*> e36bf113 msr SPSR_fxc, #-1073741820 ; 0xc0000004
-00000190 <[^>]*> e36ef113 msr SPSR_fsx, #-1073741820 ; 0xc0000004
-00000194 <[^>]*> e367f113 msr SPSR_sxc, #-1073741820 ; 0xc0000004
-00000198 <[^>]*> e36bf113 msr SPSR_fxc, #-1073741820 ; 0xc0000004
-0000019c <[^>]*> e367f113 msr SPSR_sxc, #-1073741820 ; 0xc0000004
-000001a0 <[^>]*> e36df113 msr SPSR_fsc, #-1073741820 ; 0xc0000004
-000001a4 <[^>]*> e36bf113 msr SPSR_fxc, #-1073741820 ; 0xc0000004
-000001a8 <[^>]*> e36df113 msr SPSR_fsc, #-1073741820 ; 0xc0000004
-000001ac <[^>]*> e367f113 msr SPSR_sxc, #-1073741820 ; 0xc0000004
-000001b0 <[^>]*> e36bf113 msr SPSR_fxc, #-1073741820 ; 0xc0000004
-000001b4 <[^>]*> e367f113 msr SPSR_sxc, #-1073741820 ; 0xc0000004
-000001b8 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
-000001bc <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
-000001c0 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
-000001c4 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
-000001c8 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
-000001cc <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
-000001d0 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
-000001d4 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
-000001d8 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
-000001dc <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
-000001e0 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
-000001e4 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
-000001e8 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
-000001ec <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
-000001f0 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
-000001f4 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
-000001f8 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
-000001fc <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
-00000200 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
-00000204 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
-00000208 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
-0000020c <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
-00000210 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
-00000214 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004
+00000000 <[^>]*> e328f113 msr CPSR_f, #-1073741820 @ 0xc0000004
+00000004 <[^>]*> e324f113 msr CPSR_s, #-1073741820 @ 0xc0000004
+00000008 <[^>]*> e328f113 msr CPSR_f, #-1073741820 @ 0xc0000004
+0000000c <[^>]*> e32cf113 msr CPSR_fs, #-1073741820 @ 0xc0000004
+00000010 <[^>]*> e329f113 msr CPSR_fc, #-1073741820 @ 0xc0000004
+00000014 <[^>]*> e324f113 msr CPSR_s, #-1073741820 @ 0xc0000004
+00000018 <[^>]*> e328f113 msr CPSR_f, #-1073741820 @ 0xc0000004
+0000001c <[^>]*> e321f113 msr CPSR_c, #-1073741820 @ 0xc0000004
+00000020 <[^>]*> e322f113 msr CPSR_x, #-1073741820 @ 0xc0000004
+00000024 <[^>]*> e32cf113 msr CPSR_fs, #-1073741820 @ 0xc0000004
+00000028 <[^>]*> e32af113 msr CPSR_fx, #-1073741820 @ 0xc0000004
+0000002c <[^>]*> e329f113 msr CPSR_fc, #-1073741820 @ 0xc0000004
+00000030 <[^>]*> e32cf113 msr CPSR_fs, #-1073741820 @ 0xc0000004
+00000034 <[^>]*> e326f113 msr CPSR_sx, #-1073741820 @ 0xc0000004
+00000038 <[^>]*> e325f113 msr CPSR_sc, #-1073741820 @ 0xc0000004
+0000003c <[^>]*> e32af113 msr CPSR_fx, #-1073741820 @ 0xc0000004
+00000040 <[^>]*> e326f113 msr CPSR_sx, #-1073741820 @ 0xc0000004
+00000044 <[^>]*> e323f113 msr CPSR_xc, #-1073741820 @ 0xc0000004
+00000048 <[^>]*> e329f113 msr CPSR_fc, #-1073741820 @ 0xc0000004
+0000004c <[^>]*> e325f113 msr CPSR_sc, #-1073741820 @ 0xc0000004
+00000050 <[^>]*> e323f113 msr CPSR_xc, #-1073741820 @ 0xc0000004
+00000054 <[^>]*> e32ef113 msr CPSR_fsx, #-1073741820 @ 0xc0000004
+00000058 <[^>]*> e32df113 msr CPSR_fsc, #-1073741820 @ 0xc0000004
+0000005c <[^>]*> e32ef113 msr CPSR_fsx, #-1073741820 @ 0xc0000004
+00000060 <[^>]*> e32bf113 msr CPSR_fxc, #-1073741820 @ 0xc0000004
+00000064 <[^>]*> e32df113 msr CPSR_fsc, #-1073741820 @ 0xc0000004
+00000068 <[^>]*> e32bf113 msr CPSR_fxc, #-1073741820 @ 0xc0000004
+0000006c <[^>]*> e32ef113 msr CPSR_fsx, #-1073741820 @ 0xc0000004
+00000070 <[^>]*> e32df113 msr CPSR_fsc, #-1073741820 @ 0xc0000004
+00000074 <[^>]*> e32ef113 msr CPSR_fsx, #-1073741820 @ 0xc0000004
+00000078 <[^>]*> e327f113 msr CPSR_sxc, #-1073741820 @ 0xc0000004
+0000007c <[^>]*> e32df113 msr CPSR_fsc, #-1073741820 @ 0xc0000004
+00000080 <[^>]*> e327f113 msr CPSR_sxc, #-1073741820 @ 0xc0000004
+00000084 <[^>]*> e32ef113 msr CPSR_fsx, #-1073741820 @ 0xc0000004
+00000088 <[^>]*> e32bf113 msr CPSR_fxc, #-1073741820 @ 0xc0000004
+0000008c <[^>]*> e32ef113 msr CPSR_fsx, #-1073741820 @ 0xc0000004
+00000090 <[^>]*> e327f113 msr CPSR_sxc, #-1073741820 @ 0xc0000004
+00000094 <[^>]*> e32bf113 msr CPSR_fxc, #-1073741820 @ 0xc0000004
+00000098 <[^>]*> e327f113 msr CPSR_sxc, #-1073741820 @ 0xc0000004
+0000009c <[^>]*> e32df113 msr CPSR_fsc, #-1073741820 @ 0xc0000004
+000000a0 <[^>]*> e32bf113 msr CPSR_fxc, #-1073741820 @ 0xc0000004
+000000a4 <[^>]*> e32df113 msr CPSR_fsc, #-1073741820 @ 0xc0000004
+000000a8 <[^>]*> e327f113 msr CPSR_sxc, #-1073741820 @ 0xc0000004
+000000ac <[^>]*> e32bf113 msr CPSR_fxc, #-1073741820 @ 0xc0000004
+000000b0 <[^>]*> e327f113 msr CPSR_sxc, #-1073741820 @ 0xc0000004
+000000b4 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+000000b8 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+000000bc <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+000000c0 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+000000c4 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+000000c8 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+000000cc <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+000000d0 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+000000d4 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+000000d8 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+000000dc <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+000000e0 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+000000e4 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+000000e8 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+000000ec <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+000000f0 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+000000f4 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+000000f8 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+000000fc <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+00000100 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+00000104 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+00000108 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+0000010c <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+00000110 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 @ 0xc0000004
+00000114 <[^>]*> e369f113 msr SPSR_fc, #-1073741820 @ 0xc0000004
+00000118 <[^>]*> e364f113 msr SPSR_s, #-1073741820 @ 0xc0000004
+0000011c <[^>]*> e368f113 msr SPSR_f, #-1073741820 @ 0xc0000004
+00000120 <[^>]*> e361f113 msr SPSR_c, #-1073741820 @ 0xc0000004
+00000124 <[^>]*> e362f113 msr SPSR_x, #-1073741820 @ 0xc0000004
+00000128 <[^>]*> e36cf113 msr SPSR_fs, #-1073741820 @ 0xc0000004
+0000012c <[^>]*> e36af113 msr SPSR_fx, #-1073741820 @ 0xc0000004
+00000130 <[^>]*> e369f113 msr SPSR_fc, #-1073741820 @ 0xc0000004
+00000134 <[^>]*> e36cf113 msr SPSR_fs, #-1073741820 @ 0xc0000004
+00000138 <[^>]*> e366f113 msr SPSR_sx, #-1073741820 @ 0xc0000004
+0000013c <[^>]*> e365f113 msr SPSR_sc, #-1073741820 @ 0xc0000004
+00000140 <[^>]*> e36af113 msr SPSR_fx, #-1073741820 @ 0xc0000004
+00000144 <[^>]*> e366f113 msr SPSR_sx, #-1073741820 @ 0xc0000004
+00000148 <[^>]*> e363f113 msr SPSR_xc, #-1073741820 @ 0xc0000004
+0000014c <[^>]*> e369f113 msr SPSR_fc, #-1073741820 @ 0xc0000004
+00000150 <[^>]*> e365f113 msr SPSR_sc, #-1073741820 @ 0xc0000004
+00000154 <[^>]*> e363f113 msr SPSR_xc, #-1073741820 @ 0xc0000004
+00000158 <[^>]*> e36ef113 msr SPSR_fsx, #-1073741820 @ 0xc0000004
+0000015c <[^>]*> e36df113 msr SPSR_fsc, #-1073741820 @ 0xc0000004
+00000160 <[^>]*> e36ef113 msr SPSR_fsx, #-1073741820 @ 0xc0000004
+00000164 <[^>]*> e36bf113 msr SPSR_fxc, #-1073741820 @ 0xc0000004
+00000168 <[^>]*> e36df113 msr SPSR_fsc, #-1073741820 @ 0xc0000004
+0000016c <[^>]*> e36bf113 msr SPSR_fxc, #-1073741820 @ 0xc0000004
+00000170 <[^>]*> e36ef113 msr SPSR_fsx, #-1073741820 @ 0xc0000004
+00000174 <[^>]*> e36df113 msr SPSR_fsc, #-1073741820 @ 0xc0000004
+00000178 <[^>]*> e36ef113 msr SPSR_fsx, #-1073741820 @ 0xc0000004
+0000017c <[^>]*> e367f113 msr SPSR_sxc, #-1073741820 @ 0xc0000004
+00000180 <[^>]*> e36df113 msr SPSR_fsc, #-1073741820 @ 0xc0000004
+00000184 <[^>]*> e367f113 msr SPSR_sxc, #-1073741820 @ 0xc0000004
+00000188 <[^>]*> e36ef113 msr SPSR_fsx, #-1073741820 @ 0xc0000004
+0000018c <[^>]*> e36bf113 msr SPSR_fxc, #-1073741820 @ 0xc0000004
+00000190 <[^>]*> e36ef113 msr SPSR_fsx, #-1073741820 @ 0xc0000004
+00000194 <[^>]*> e367f113 msr SPSR_sxc, #-1073741820 @ 0xc0000004
+00000198 <[^>]*> e36bf113 msr SPSR_fxc, #-1073741820 @ 0xc0000004
+0000019c <[^>]*> e367f113 msr SPSR_sxc, #-1073741820 @ 0xc0000004
+000001a0 <[^>]*> e36df113 msr SPSR_fsc, #-1073741820 @ 0xc0000004
+000001a4 <[^>]*> e36bf113 msr SPSR_fxc, #-1073741820 @ 0xc0000004
+000001a8 <[^>]*> e36df113 msr SPSR_fsc, #-1073741820 @ 0xc0000004
+000001ac <[^>]*> e367f113 msr SPSR_sxc, #-1073741820 @ 0xc0000004
+000001b0 <[^>]*> e36bf113 msr SPSR_fxc, #-1073741820 @ 0xc0000004
+000001b4 <[^>]*> e367f113 msr SPSR_sxc, #-1073741820 @ 0xc0000004
+000001b8 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
+000001bc <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
+000001c0 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
+000001c4 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
+000001c8 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
+000001cc <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
+000001d0 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
+000001d4 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
+000001d8 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
+000001dc <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
+000001e0 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
+000001e4 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
+000001e8 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
+000001ec <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
+000001f0 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
+000001f4 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
+000001f8 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
+000001fc <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
+00000200 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
+00000204 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
+00000208 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
+0000020c <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
+00000210 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
+00000214 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 @ 0xc0000004
[^>]*> ef0e e154 vand q7, q7, q2
[^>]*> ef0e e158 vand q7, q7, q4
[^>]*> ef0e e15e vand q7, q7, q7
-[^>]*> ef80 0170 vbic.i32 q0, #0 ; 0x00000000
-[^>]*> ef80 0170 vbic.i32 q0, #0 ; 0x00000000
-[^>]*> ff87 017f vbic.i32 q0, #255 ; 0x000000ff
-[^>]*> ff87 037f vbic.i32 q0, #65280 ; 0x0000ff00
-[^>]*> ff87 057f vbic.i32 q0, #16711680 ; 0x00ff0000
-[^>]*> ff87 077f vbic.i32 q0, #4278190080 ; 0xff000000
-[^>]*> ef80 0970 vbic.i16 q0, #0 ; 0x0000
-[^>]*> ff87 0b7f vbic.i16 q0, #65280 ; 0xff00
-[^>]*> ff87 097f vbic.i16 q0, #255 ; 0x00ff
-[^>]*> ef80 2170 vbic.i32 q1, #0 ; 0x00000000
-[^>]*> ef80 2170 vbic.i32 q1, #0 ; 0x00000000
-[^>]*> ff87 217f vbic.i32 q1, #255 ; 0x000000ff
-[^>]*> ff87 237f vbic.i32 q1, #65280 ; 0x0000ff00
-[^>]*> ff87 257f vbic.i32 q1, #16711680 ; 0x00ff0000
-[^>]*> ff87 277f vbic.i32 q1, #4278190080 ; 0xff000000
-[^>]*> ef80 2970 vbic.i16 q1, #0 ; 0x0000
-[^>]*> ff87 2b7f vbic.i16 q1, #65280 ; 0xff00
-[^>]*> ff87 297f vbic.i16 q1, #255 ; 0x00ff
-[^>]*> ef80 4170 vbic.i32 q2, #0 ; 0x00000000
-[^>]*> ef80 4170 vbic.i32 q2, #0 ; 0x00000000
-[^>]*> ff87 417f vbic.i32 q2, #255 ; 0x000000ff
-[^>]*> ff87 437f vbic.i32 q2, #65280 ; 0x0000ff00
-[^>]*> ff87 457f vbic.i32 q2, #16711680 ; 0x00ff0000
-[^>]*> ff87 477f vbic.i32 q2, #4278190080 ; 0xff000000
-[^>]*> ef80 4970 vbic.i16 q2, #0 ; 0x0000
-[^>]*> ff87 4b7f vbic.i16 q2, #65280 ; 0xff00
-[^>]*> ff87 497f vbic.i16 q2, #255 ; 0x00ff
-[^>]*> ef80 8170 vbic.i32 q4, #0 ; 0x00000000
-[^>]*> ef80 8170 vbic.i32 q4, #0 ; 0x00000000
-[^>]*> ff87 817f vbic.i32 q4, #255 ; 0x000000ff
-[^>]*> ff87 837f vbic.i32 q4, #65280 ; 0x0000ff00
-[^>]*> ff87 857f vbic.i32 q4, #16711680 ; 0x00ff0000
-[^>]*> ff87 877f vbic.i32 q4, #4278190080 ; 0xff000000
-[^>]*> ef80 8970 vbic.i16 q4, #0 ; 0x0000
-[^>]*> ff87 8b7f vbic.i16 q4, #65280 ; 0xff00
-[^>]*> ff87 897f vbic.i16 q4, #255 ; 0x00ff
-[^>]*> ef80 e170 vbic.i32 q7, #0 ; 0x00000000
-[^>]*> ef80 e170 vbic.i32 q7, #0 ; 0x00000000
-[^>]*> ff87 e17f vbic.i32 q7, #255 ; 0x000000ff
-[^>]*> ff87 e37f vbic.i32 q7, #65280 ; 0x0000ff00
-[^>]*> ff87 e57f vbic.i32 q7, #16711680 ; 0x00ff0000
-[^>]*> ff87 e77f vbic.i32 q7, #4278190080 ; 0xff000000
-[^>]*> ef80 e970 vbic.i16 q7, #0 ; 0x0000
-[^>]*> ff87 eb7f vbic.i16 q7, #65280 ; 0xff00
-[^>]*> ff87 e97f vbic.i16 q7, #255 ; 0x00ff
+[^>]*> ef80 0170 vbic.i32 q0, #0 @ 0x00000000
+[^>]*> ef80 0170 vbic.i32 q0, #0 @ 0x00000000
+[^>]*> ff87 017f vbic.i32 q0, #255 @ 0x000000ff
+[^>]*> ff87 037f vbic.i32 q0, #65280 @ 0x0000ff00
+[^>]*> ff87 057f vbic.i32 q0, #16711680 @ 0x00ff0000
+[^>]*> ff87 077f vbic.i32 q0, #4278190080 @ 0xff000000
+[^>]*> ef80 0970 vbic.i16 q0, #0 @ 0x0000
+[^>]*> ff87 0b7f vbic.i16 q0, #65280 @ 0xff00
+[^>]*> ff87 097f vbic.i16 q0, #255 @ 0x00ff
+[^>]*> ef80 2170 vbic.i32 q1, #0 @ 0x00000000
+[^>]*> ef80 2170 vbic.i32 q1, #0 @ 0x00000000
+[^>]*> ff87 217f vbic.i32 q1, #255 @ 0x000000ff
+[^>]*> ff87 237f vbic.i32 q1, #65280 @ 0x0000ff00
+[^>]*> ff87 257f vbic.i32 q1, #16711680 @ 0x00ff0000
+[^>]*> ff87 277f vbic.i32 q1, #4278190080 @ 0xff000000
+[^>]*> ef80 2970 vbic.i16 q1, #0 @ 0x0000
+[^>]*> ff87 2b7f vbic.i16 q1, #65280 @ 0xff00
+[^>]*> ff87 297f vbic.i16 q1, #255 @ 0x00ff
+[^>]*> ef80 4170 vbic.i32 q2, #0 @ 0x00000000
+[^>]*> ef80 4170 vbic.i32 q2, #0 @ 0x00000000
+[^>]*> ff87 417f vbic.i32 q2, #255 @ 0x000000ff
+[^>]*> ff87 437f vbic.i32 q2, #65280 @ 0x0000ff00
+[^>]*> ff87 457f vbic.i32 q2, #16711680 @ 0x00ff0000
+[^>]*> ff87 477f vbic.i32 q2, #4278190080 @ 0xff000000
+[^>]*> ef80 4970 vbic.i16 q2, #0 @ 0x0000
+[^>]*> ff87 4b7f vbic.i16 q2, #65280 @ 0xff00
+[^>]*> ff87 497f vbic.i16 q2, #255 @ 0x00ff
+[^>]*> ef80 8170 vbic.i32 q4, #0 @ 0x00000000
+[^>]*> ef80 8170 vbic.i32 q4, #0 @ 0x00000000
+[^>]*> ff87 817f vbic.i32 q4, #255 @ 0x000000ff
+[^>]*> ff87 837f vbic.i32 q4, #65280 @ 0x0000ff00
+[^>]*> ff87 857f vbic.i32 q4, #16711680 @ 0x00ff0000
+[^>]*> ff87 877f vbic.i32 q4, #4278190080 @ 0xff000000
+[^>]*> ef80 8970 vbic.i16 q4, #0 @ 0x0000
+[^>]*> ff87 8b7f vbic.i16 q4, #65280 @ 0xff00
+[^>]*> ff87 897f vbic.i16 q4, #255 @ 0x00ff
+[^>]*> ef80 e170 vbic.i32 q7, #0 @ 0x00000000
+[^>]*> ef80 e170 vbic.i32 q7, #0 @ 0x00000000
+[^>]*> ff87 e17f vbic.i32 q7, #255 @ 0x000000ff
+[^>]*> ff87 e37f vbic.i32 q7, #65280 @ 0x0000ff00
+[^>]*> ff87 e57f vbic.i32 q7, #16711680 @ 0x00ff0000
+[^>]*> ff87 e77f vbic.i32 q7, #4278190080 @ 0xff000000
+[^>]*> ef80 e970 vbic.i16 q7, #0 @ 0x0000
+[^>]*> ff87 eb7f vbic.i16 q7, #65280 @ 0xff00
+[^>]*> ff87 e97f vbic.i16 q7, #255 @ 0x00ff
[^>]*> fe71 ef4d vpstete
[^>]*> ef02 0154 vandt q0, q1, q2
[^>]*> ef02 0154 vande q0, q1, q2
-[^>]*> ef80 0170 vbict.i32 q0, #0 ; 0x00000000
-[^>]*> ff87 097f vbice.i16 q0, #255 ; 0x00ff
+[^>]*> ef80 0170 vbict.i32 q0, #0 @ 0x00000000
+[^>]*> ff87 097f vbice.i16 q0, #255 @ 0x00ff
[^>]*> ef1e e15e vbic q7, q7, q7
[^>]*> ef1e e15e vbic q7, q7, q7
[^>]*> ef1e e15e vbic q7, q7, q7
-[^>]*> ef80 0170 vbic.i32 q0, #0 ; 0x00000000
-[^>]*> ff87 017f vbic.i32 q0, #255 ; 0x000000ff
-[^>]*> ff87 037f vbic.i32 q0, #65280 ; 0x0000ff00
-[^>]*> ff87 077f vbic.i32 q0, #4278190080 ; 0xff000000
-[^>]*> ff87 057f vbic.i32 q0, #16711680 ; 0x00ff0000
-[^>]*> ef80 0970 vbic.i16 q0, #0 ; 0x0000
-[^>]*> ff87 097f vbic.i16 q0, #255 ; 0x00ff
-[^>]*> ff87 0b7f vbic.i16 q0, #65280 ; 0xff00
+[^>]*> ef80 0170 vbic.i32 q0, #0 @ 0x00000000
+[^>]*> ff87 017f vbic.i32 q0, #255 @ 0x000000ff
+[^>]*> ff87 037f vbic.i32 q0, #65280 @ 0x0000ff00
+[^>]*> ff87 077f vbic.i32 q0, #4278190080 @ 0xff000000
+[^>]*> ff87 057f vbic.i32 q0, #16711680 @ 0x00ff0000
+[^>]*> ef80 0970 vbic.i16 q0, #0 @ 0x0000
+[^>]*> ff87 097f vbic.i16 q0, #255 @ 0x00ff
+[^>]*> ff87 0b7f vbic.i16 q0, #65280 @ 0xff00
[^>]*> fe71 ef4d vpstete
[^>]*> ef12 0154 vbict q0, q1, q2
[^>]*> ef12 0154 vbice q0, q1, q2
-[^>]*> ef80 0170 vbict.i32 q0, #0 ; 0x00000000
-[^>]*> ff87 0b7f vbice.i16 q0, #65280 ; 0xff00
+[^>]*> ef80 0170 vbict.i32 q0, #0 @ 0x00000000
+[^>]*> ff87 0b7f vbice.i16 q0, #65280 @ 0xff00
[^>]*> ee3f 0e05 vcvtb.f16.f32 q0, q2
[^>]*> ee3f 1e09 vcvtt.f16.f32 q0, q4
[^>]*> ee3f 0e09 vcvtb.f16.f32 q0, q4
-[^>]*> ee3f 1e11 ; <UNDEFINED> instruction: 0xee3f1e11
-[^>]*> ee3f 0e11 ; <UNDEFINED> instruction: 0xee3f0e11
-[^>]*> ee3f 1e1d ; <UNDEFINED> instruction: 0xee3f1e1d
-[^>]*> ee3f 0e1d ; <UNDEFINED> instruction: 0xee3f0e1d
+[^>]*> ee3f 1e11 @ <UNDEFINED> instruction: 0xee3f1e11
+[^>]*> ee3f 0e11 @ <UNDEFINED> instruction: 0xee3f0e11
+[^>]*> ee3f 1e1d @ <UNDEFINED> instruction: 0xee3f1e1d
+[^>]*> ee3f 0e1d @ <UNDEFINED> instruction: 0xee3f0e1d
[^>]*> ee3f 5e01 vcvtt.f16.f32 q2, q0
[^>]*> ee3f 4e01 vcvtb.f16.f32 q2, q0
[^>]*> ee3f 5e05 vcvtt.f16.f32 q2, q2
[^>]*> ee3f 4e05 vcvtb.f16.f32 q2, q2
[^>]*> ee3f 5e09 vcvtt.f16.f32 q2, q4
[^>]*> ee3f 4e09 vcvtb.f16.f32 q2, q4
-[^>]*> ee3f 5e11 ; <UNDEFINED> instruction: 0xee3f5e11
-[^>]*> ee3f 4e11 ; <UNDEFINED> instruction: 0xee3f4e11
-[^>]*> ee3f 5e1d ; <UNDEFINED> instruction: 0xee3f5e1d
-[^>]*> ee3f 4e1d ; <UNDEFINED> instruction: 0xee3f4e1d
+[^>]*> ee3f 5e11 @ <UNDEFINED> instruction: 0xee3f5e11
+[^>]*> ee3f 4e11 @ <UNDEFINED> instruction: 0xee3f4e11
+[^>]*> ee3f 5e1d @ <UNDEFINED> instruction: 0xee3f5e1d
+[^>]*> ee3f 4e1d @ <UNDEFINED> instruction: 0xee3f4e1d
[^>]*> ee3f 9e01 vcvtt.f16.f32 q4, q0
[^>]*> ee3f 8e01 vcvtb.f16.f32 q4, q0
[^>]*> ee3f 9e05 vcvtt.f16.f32 q4, q2
[^>]*> ee3f 8e05 vcvtb.f16.f32 q4, q2
[^>]*> ee3f 9e09 vcvtt.f16.f32 q4, q4
[^>]*> ee3f 8e09 vcvtb.f16.f32 q4, q4
-[^>]*> ee3f 9e11 ; <UNDEFINED> instruction: 0xee3f9e11
-[^>]*> ee3f 8e11 ; <UNDEFINED> instruction: 0xee3f8e11
-[^>]*> ee3f 9e1d ; <UNDEFINED> instruction: 0xee3f9e1d
-[^>]*> ee3f 8e1d ; <UNDEFINED> instruction: 0xee3f8e1d
+[^>]*> ee3f 9e11 @ <UNDEFINED> instruction: 0xee3f9e11
+[^>]*> ee3f 8e11 @ <UNDEFINED> instruction: 0xee3f8e11
+[^>]*> ee3f 9e1d @ <UNDEFINED> instruction: 0xee3f9e1d
+[^>]*> ee3f 8e1d @ <UNDEFINED> instruction: 0xee3f8e1d
[^>]*> ee3f 1e01 vcvtt.f16.f32 q0, q0
[^>]*> ee3f 0e01 vcvtb.f16.f32 q0, q0
[^>]*> ee3f 1e05 vcvtt.f16.f32 q0, q2
[^>]*> ee3f 0e05 vcvtb.f16.f32 q0, q2
[^>]*> ee3f 1e09 vcvtt.f16.f32 q0, q4
[^>]*> ee3f 0e09 vcvtb.f16.f32 q0, q4
-[^>]*> ee3f 1e11 ; <UNDEFINED> instruction: 0xee3f1e11
-[^>]*> ee3f 0e11 ; <UNDEFINED> instruction: 0xee3f0e11
-[^>]*> ee3f 1e1d ; <UNDEFINED> instruction: 0xee3f1e1d
-[^>]*> ee3f 0e1d ; <UNDEFINED> instruction: 0xee3f0e1d
+[^>]*> ee3f 1e11 @ <UNDEFINED> instruction: 0xee3f1e11
+[^>]*> ee3f 0e11 @ <UNDEFINED> instruction: 0xee3f0e11
+[^>]*> ee3f 1e1d @ <UNDEFINED> instruction: 0xee3f1e1d
+[^>]*> ee3f 0e1d @ <UNDEFINED> instruction: 0xee3f0e1d
[^>]*> ee3f de01 vcvtt.f16.f32 q6, q0
[^>]*> ee3f ce01 vcvtb.f16.f32 q6, q0
[^>]*> ee3f de05 vcvtt.f16.f32 q6, q2
[^>]*> ee3f ce05 vcvtb.f16.f32 q6, q2
[^>]*> ee3f de09 vcvtt.f16.f32 q6, q4
[^>]*> ee3f ce09 vcvtb.f16.f32 q6, q4
-[^>]*> ee3f de11 ; <UNDEFINED> instruction: 0xee3fde11
-[^>]*> ee3f ce11 ; <UNDEFINED> instruction: 0xee3fce11
-[^>]*> ee3f de1d ; <UNDEFINED> instruction: 0xee3fde1d
-[^>]*> ee3f ce1d ; <UNDEFINED> instruction: 0xee3fce1d
+[^>]*> ee3f de11 @ <UNDEFINED> instruction: 0xee3fde11
+[^>]*> ee3f ce11 @ <UNDEFINED> instruction: 0xee3fce11
+[^>]*> ee3f de1d @ <UNDEFINED> instruction: 0xee3fde1d
+[^>]*> ee3f ce1d @ <UNDEFINED> instruction: 0xee3fce1d
[^>]*> fe3f 1e01 vcvtt.f32.f16 q0, q0
[^>]*> fe3f 0e01 vcvtb.f32.f16 q0, q0
[^>]*> fe3f 1e05 vcvtt.f32.f16 q0, q2
[^>]*> fe3f 0e05 vcvtb.f32.f16 q0, q2
[^>]*> fe3f 1e09 vcvtt.f32.f16 q0, q4
[^>]*> fe3f 0e09 vcvtb.f32.f16 q0, q4
-[^>]*> fe3f 1e11 ; <UNDEFINED> instruction: 0xfe3f1e11
-[^>]*> fe3f 0e11 ; <UNDEFINED> instruction: 0xfe3f0e11
-[^>]*> fe3f 1e1d ; <UNDEFINED> instruction: 0xfe3f1e1d
-[^>]*> fe3f 0e1d ; <UNDEFINED> instruction: 0xfe3f0e1d
+[^>]*> fe3f 1e11 @ <UNDEFINED> instruction: 0xfe3f1e11
+[^>]*> fe3f 0e11 @ <UNDEFINED> instruction: 0xfe3f0e11
+[^>]*> fe3f 1e1d @ <UNDEFINED> instruction: 0xfe3f1e1d
+[^>]*> fe3f 0e1d @ <UNDEFINED> instruction: 0xfe3f0e1d
[^>]*> fe3f 5e01 vcvtt.f32.f16 q2, q0
[^>]*> fe3f 4e01 vcvtb.f32.f16 q2, q0
[^>]*> fe3f 5e05 vcvtt.f32.f16 q2, q2
[^>]*> fe3f 4e05 vcvtb.f32.f16 q2, q2
[^>]*> fe3f 5e09 vcvtt.f32.f16 q2, q4
[^>]*> fe3f 4e09 vcvtb.f32.f16 q2, q4
-[^>]*> fe3f 5e11 ; <UNDEFINED> instruction: 0xfe3f5e11
-[^>]*> fe3f 4e11 ; <UNDEFINED> instruction: 0xfe3f4e11
-[^>]*> fe3f 5e1d ; <UNDEFINED> instruction: 0xfe3f5e1d
-[^>]*> fe3f 4e1d ; <UNDEFINED> instruction: 0xfe3f4e1d
+[^>]*> fe3f 5e11 @ <UNDEFINED> instruction: 0xfe3f5e11
+[^>]*> fe3f 4e11 @ <UNDEFINED> instruction: 0xfe3f4e11
+[^>]*> fe3f 5e1d @ <UNDEFINED> instruction: 0xfe3f5e1d
+[^>]*> fe3f 4e1d @ <UNDEFINED> instruction: 0xfe3f4e1d
[^>]*> fe3f 9e01 vcvtt.f32.f16 q4, q0
[^>]*> fe3f 8e01 vcvtb.f32.f16 q4, q0
[^>]*> fe3f 9e05 vcvtt.f32.f16 q4, q2
[^>]*> fe3f 8e05 vcvtb.f32.f16 q4, q2
[^>]*> fe3f 9e09 vcvtt.f32.f16 q4, q4
[^>]*> fe3f 8e09 vcvtb.f32.f16 q4, q4
-[^>]*> fe3f 9e11 ; <UNDEFINED> instruction: 0xfe3f9e11
-[^>]*> fe3f 8e11 ; <UNDEFINED> instruction: 0xfe3f8e11
-[^>]*> fe3f 9e1d ; <UNDEFINED> instruction: 0xfe3f9e1d
-[^>]*> fe3f 8e1d ; <UNDEFINED> instruction: 0xfe3f8e1d
+[^>]*> fe3f 9e11 @ <UNDEFINED> instruction: 0xfe3f9e11
+[^>]*> fe3f 8e11 @ <UNDEFINED> instruction: 0xfe3f8e11
+[^>]*> fe3f 9e1d @ <UNDEFINED> instruction: 0xfe3f9e1d
+[^>]*> fe3f 8e1d @ <UNDEFINED> instruction: 0xfe3f8e1d
[^>]*> fe3f 1e01 vcvtt.f32.f16 q0, q0
[^>]*> fe3f 0e01 vcvtb.f32.f16 q0, q0
[^>]*> fe3f 1e05 vcvtt.f32.f16 q0, q2
[^>]*> fe3f 0e05 vcvtb.f32.f16 q0, q2
[^>]*> fe3f 1e09 vcvtt.f32.f16 q0, q4
[^>]*> fe3f 0e09 vcvtb.f32.f16 q0, q4
-[^>]*> fe3f 1e11 ; <UNDEFINED> instruction: 0xfe3f1e11
-[^>]*> fe3f 0e11 ; <UNDEFINED> instruction: 0xfe3f0e11
-[^>]*> fe3f 1e1d ; <UNDEFINED> instruction: 0xfe3f1e1d
-[^>]*> fe3f 0e1d ; <UNDEFINED> instruction: 0xfe3f0e1d
+[^>]*> fe3f 1e11 @ <UNDEFINED> instruction: 0xfe3f1e11
+[^>]*> fe3f 0e11 @ <UNDEFINED> instruction: 0xfe3f0e11
+[^>]*> fe3f 1e1d @ <UNDEFINED> instruction: 0xfe3f1e1d
+[^>]*> fe3f 0e1d @ <UNDEFINED> instruction: 0xfe3f0e1d
[^>]*> fe3f de01 vcvtt.f32.f16 q6, q0
[^>]*> fe3f ce01 vcvtb.f32.f16 q6, q0
[^>]*> fe3f de05 vcvtt.f32.f16 q6, q2
[^>]*> fe3f ce05 vcvtb.f32.f16 q6, q2
[^>]*> fe3f de09 vcvtt.f32.f16 q6, q4
[^>]*> fe3f ce09 vcvtb.f32.f16 q6, q4
-[^>]*> fe3f de11 ; <UNDEFINED> instruction: 0xfe3fde11
-[^>]*> fe3f ce11 ; <UNDEFINED> instruction: 0xfe3fce11
-[^>]*> fe3f de1d ; <UNDEFINED> instruction: 0xfe3fde1d
-[^>]*> fe3f ce1d ; <UNDEFINED> instruction: 0xfe3fce1d
+[^>]*> fe3f de11 @ <UNDEFINED> instruction: 0xfe3fde11
+[^>]*> fe3f ce11 @ <UNDEFINED> instruction: 0xfe3fce11
+[^>]*> fe3f de1d @ <UNDEFINED> instruction: 0xfe3fde1d
+[^>]*> fe3f ce1d @ <UNDEFINED> instruction: 0xfe3fce1d
[^>]*> fe31 af4d vpsttee
[^>]*> ee3f 1e05 vcvttt.f16.f32 q0, q2
[^>]*> ee3f 0e05 vcvtbt.f16.f32 q0, q2
[^>]*> ee35 eb10 vmov.32 lr, d5\[1\]
[^>]*> ee39 eb10 vmov.32 lr, d9\[1\]
[^>]*> ee3f eb10 vmov.32 lr, d15\[1\]
-[^>]*> ef80 0050 vmov.i32 q0, #0 ; 0x00000000
-[^>]*> ff87 005f vmov.i32 q0, #255 ; 0x000000ff
-[^>]*> ff87 025f vmov.i32 q0, #65280 ; 0x0000ff00
-[^>]*> ff87 065f vmov.i32 q0, #4278190080 ; 0xff000000
-[^>]*> ff87 045f vmov.i32 q0, #16711680 ; 0x00ff0000
-[^>]*> ef80 0850 vmov.i16 q0, #0 ; 0x0000
-[^>]*> ff87 085f vmov.i16 q0, #255 ; 0x00ff
-[^>]*> ff87 0a5f vmov.i16 q0, #65280 ; 0xff00
-[^>]*> ef80 0e50 vmov.i8 q0, #0 ; 0x00
-[^>]*> ff87 0e5f vmov.i8 q0, #255 ; 0xff
+[^>]*> ef80 0050 vmov.i32 q0, #0 @ 0x00000000
+[^>]*> ff87 005f vmov.i32 q0, #255 @ 0x000000ff
+[^>]*> ff87 025f vmov.i32 q0, #65280 @ 0x0000ff00
+[^>]*> ff87 065f vmov.i32 q0, #4278190080 @ 0xff000000
+[^>]*> ff87 045f vmov.i32 q0, #16711680 @ 0x00ff0000
+[^>]*> ef80 0850 vmov.i16 q0, #0 @ 0x0000
+[^>]*> ff87 085f vmov.i16 q0, #255 @ 0x00ff
+[^>]*> ff87 0a5f vmov.i16 q0, #65280 @ 0xff00
+[^>]*> ef80 0e50 vmov.i8 q0, #0 @ 0x00
+[^>]*> ff87 0e5f vmov.i8 q0, #255 @ 0xff
[^>]*> ff80 0e70 vmov.i64 q0, #0xff00000000000000
[^>]*> ef84 0e70 vmov.i64 q0, #0x00ff000000000000
[^>]*> ef82 0e70 vmov.i64 q0, #0x0000ff0000000000
[^>]*> ee35 eb10 vmov.32 lr, d5\[1\]
[^>]*> ee39 eb10 vmov.32 lr, d9\[1\]
[^>]*> ee3f eb10 vmov.32 lr, d15\[1\]
-[^>]*> ef80 0050 vmov.i32 q0, #0 ; 0x00000000
-[^>]*> ff87 005f vmov.i32 q0, #255 ; 0x000000ff
-[^>]*> ff87 025f vmov.i32 q0, #65280 ; 0x0000ff00
-[^>]*> ff87 065f vmov.i32 q0, #4278190080 ; 0xff000000
-[^>]*> ff87 045f vmov.i32 q0, #16711680 ; 0x00ff0000
-[^>]*> ef80 0850 vmov.i16 q0, #0 ; 0x0000
-[^>]*> ff87 085f vmov.i16 q0, #255 ; 0x00ff
-[^>]*> ff87 0a5f vmov.i16 q0, #65280 ; 0xff00
-[^>]*> ef80 0e50 vmov.i8 q0, #0 ; 0x00
-[^>]*> ff87 0e5f vmov.i8 q0, #255 ; 0xff
+[^>]*> ef80 0050 vmov.i32 q0, #0 @ 0x00000000
+[^>]*> ff87 005f vmov.i32 q0, #255 @ 0x000000ff
+[^>]*> ff87 025f vmov.i32 q0, #65280 @ 0x0000ff00
+[^>]*> ff87 065f vmov.i32 q0, #4278190080 @ 0xff000000
+[^>]*> ff87 045f vmov.i32 q0, #16711680 @ 0x00ff0000
+[^>]*> ef80 0850 vmov.i16 q0, #0 @ 0x0000
+[^>]*> ff87 085f vmov.i16 q0, #255 @ 0x00ff
+[^>]*> ff87 0a5f vmov.i16 q0, #65280 @ 0xff00
+[^>]*> ef80 0e50 vmov.i8 q0, #0 @ 0x00
+[^>]*> ff87 0e5f vmov.i8 q0, #255 @ 0xff
[^>]*> ff80 0e70 vmov.i64 q0, #0xff00000000000000
[^>]*> ef84 0e70 vmov.i64 q0, #0x00ff000000000000
[^>]*> ef82 0e70 vmov.i64 q0, #0x0000ff0000000000
[^>]*> ee1f c990 vmov.f16 ip, s31
[^>]*> ee0f e990 vmov.f16 s31, lr
[^>]*> ee1f e990 vmov.f16 lr, s31
-[^>]*> ef80 0050 vmov.i32 q0, #0 ; 0x00000000
-[^>]*> ff83 0f5f vmov.f32 q0, #-31 ; 0xc1f80000
-[^>]*> ff83 0f5f vmov.f32 q0, #-31 ; 0xc1f80000
-[^>]*> ff87 0f5f vmov.f32 q0, #-1.9375 ; 0xbff80000
-[^>]*> ef87 0f50 vmov.f32 q0, #1 ; 0x3f800000
-[^>]*> eeb0 0900 vmov.f16 s0, #0 ; 0x40000000 2.0
-[^>]*> eeb0 0a04 vmov.f32 s0, #4 ; 0x40200000 2.5
+[^>]*> ef80 0050 vmov.i32 q0, #0 @ 0x00000000
+[^>]*> ff83 0f5f vmov.f32 q0, #-31 @ 0xc1f80000
+[^>]*> ff83 0f5f vmov.f32 q0, #-31 @ 0xc1f80000
+[^>]*> ff87 0f5f vmov.f32 q0, #-1.9375 @ 0xbff80000
+[^>]*> ef87 0f50 vmov.f32 q0, #1 @ 0x3f800000
+[^>]*> eeb0 0900 vmov.f16 s0, #0 @ 0x40000000 2.0
+[^>]*> eeb0 0a04 vmov.f32 s0, #4 @ 0x40200000 2.5
.*: +file format .*arm.*
Disassembly of section .text:
-[^>]*> ff80 0d70 vmvn.i32 q0, #8454143 ; 0x0080ffff
-[^>]*> ff80 0f70 ; <UNDEFINED> instruction: 0xff800f70
+[^>]*> ff80 0d70 vmvn.i32 q0, #8454143 @ 0x0080ffff
+[^>]*> ff80 0f70 @ <UNDEFINED> instruction: 0xff800f70
[^>]*> ef80 0e70 vmov.i64 q0, #0x0000000000000000
-[^>]*> ef80 0070 vmvn.i32 q0, #0 ; 0x00000000
-[^>]*> ef80 0270 vmvn.i32 q0, #0 ; 0x00000000
-[^>]*> ef80 0470 vmvn.i32 q0, #0 ; 0x00000000
-[^>]*> ef80 0670 vmvn.i32 q0, #0 ; 0x00000000
-[^>]*> ef80 0870 vmvn.i16 q0, #0 ; 0x0000
-[^>]*> ef80 0a70 vmvn.i16 q0, #0 ; 0x0000
-[^>]*> ef80 0c70 vmvn.i32 q0, #255 ; 0x000000ff
-[^>]*> ef80 0150 vorr.i32 q0, #0 ; 0x00000000
-[^>]*> ef80 0350 vorr.i32 q0, #0 ; 0x00000000
-[^>]*> ef80 0550 vorr.i32 q0, #0 ; 0x00000000
-[^>]*> ef80 0950 vorr.i16 q0, #0 ; 0x0000
-[^>]*> ef80 0b50 vorr.i16 q0, #0 ; 0x0000
-[^>]*> ef80 0170 vbic.i32 q0, #0 ; 0x00000000
-[^>]*> ef80 0370 vbic.i32 q0, #0 ; 0x00000000
-[^>]*> ef80 0570 vbic.i32 q0, #0 ; 0x00000000
-[^>]*> ef80 0770 vbic.i32 q0, #0 ; 0x00000000
-[^>]*> ef80 0970 vbic.i16 q0, #0 ; 0x0000
-[^>]*> ef80 0b70 vbic.i16 q0, #0 ; 0x0000
-[^>]*> ef80 0050 vmov.i32 q0, #0 ; 0x00000000
-[^>]*> ef80 0250 vmov.i32 q0, #0 ; 0x00000000
-[^>]*> ef80 0450 vmov.i32 q0, #0 ; 0x00000000
-[^>]*> ef80 0650 vmov.i32 q0, #0 ; 0x00000000
-[^>]*> ef80 0850 vmov.i16 q0, #0 ; 0x0000
-[^>]*> ef80 0a50 vmov.i16 q0, #0 ; 0x0000
-[^>]*> ef80 0c50 vmov.i32 q0, #255 ; 0x000000ff
-[^>]*> ef80 0e50 vmov.i8 q0, #0 ; 0x00
-[^>]*> ef80 0d50 vmov.i32 q0, #65535 ; 0x0000ffff
-[^>]*> ef80 0f50 vmov.f32 q0, #2 ; 0x40000000
-[^>]*> ff80 0d70 vmvn.i32 q0, #8454143 ; 0x0080ffff
-[^>]*> ff80 0d50 vmov.i32 q0, #8454143 ; 0x0080ffff
+[^>]*> ef80 0070 vmvn.i32 q0, #0 @ 0x00000000
+[^>]*> ef80 0270 vmvn.i32 q0, #0 @ 0x00000000
+[^>]*> ef80 0470 vmvn.i32 q0, #0 @ 0x00000000
+[^>]*> ef80 0670 vmvn.i32 q0, #0 @ 0x00000000
+[^>]*> ef80 0870 vmvn.i16 q0, #0 @ 0x0000
+[^>]*> ef80 0a70 vmvn.i16 q0, #0 @ 0x0000
+[^>]*> ef80 0c70 vmvn.i32 q0, #255 @ 0x000000ff
+[^>]*> ef80 0150 vorr.i32 q0, #0 @ 0x00000000
+[^>]*> ef80 0350 vorr.i32 q0, #0 @ 0x00000000
+[^>]*> ef80 0550 vorr.i32 q0, #0 @ 0x00000000
+[^>]*> ef80 0950 vorr.i16 q0, #0 @ 0x0000
+[^>]*> ef80 0b50 vorr.i16 q0, #0 @ 0x0000
+[^>]*> ef80 0170 vbic.i32 q0, #0 @ 0x00000000
+[^>]*> ef80 0370 vbic.i32 q0, #0 @ 0x00000000
+[^>]*> ef80 0570 vbic.i32 q0, #0 @ 0x00000000
+[^>]*> ef80 0770 vbic.i32 q0, #0 @ 0x00000000
+[^>]*> ef80 0970 vbic.i16 q0, #0 @ 0x0000
+[^>]*> ef80 0b70 vbic.i16 q0, #0 @ 0x0000
+[^>]*> ef80 0050 vmov.i32 q0, #0 @ 0x00000000
+[^>]*> ef80 0250 vmov.i32 q0, #0 @ 0x00000000
+[^>]*> ef80 0450 vmov.i32 q0, #0 @ 0x00000000
+[^>]*> ef80 0650 vmov.i32 q0, #0 @ 0x00000000
+[^>]*> ef80 0850 vmov.i16 q0, #0 @ 0x0000
+[^>]*> ef80 0a50 vmov.i16 q0, #0 @ 0x0000
+[^>]*> ef80 0c50 vmov.i32 q0, #255 @ 0x000000ff
+[^>]*> ef80 0e50 vmov.i8 q0, #0 @ 0x00
+[^>]*> ef80 0d50 vmov.i32 q0, #65535 @ 0x0000ffff
+[^>]*> ef80 0f50 vmov.f32 q0, #2 @ 0x40000000
+[^>]*> ff80 0d70 vmvn.i32 q0, #8454143 @ 0x0080ffff
+[^>]*> ff80 0d50 vmov.i32 q0, #8454143 @ 0x0080ffff
[^>]*> ffb0 05c4 vmvn q0, q2
[^>]*> ffb0 05c8 vmvn q0, q4
[^>]*> ffb0 05ce vmvn q0, q7
-[^>]*> ef80 0070 vmvn.i32 q0, #0 ; 0x00000000
-[^>]*> ef80 0870 vmvn.i16 q0, #0 ; 0x0000
-[^>]*> ff87 007f vmvn.i32 q0, #255 ; 0x000000ff
-[^>]*> ff87 027f vmvn.i32 q0, #65280 ; 0x0000ff00
-[^>]*> ff87 047f vmvn.i32 q0, #16711680 ; 0x00ff0000
-[^>]*> ff87 067f vmvn.i32 q0, #4278190080 ; 0xff000000
-[^>]*> ff82 0c7b vmvn.i32 q0, #44031 ; 0x0000abff
-[^>]*> ff87 087f vmvn.i16 q0, #255 ; 0x00ff
-[^>]*> ff87 0a7f vmvn.i16 q0, #65280 ; 0xff00
-[^>]*> ff87 0a5e vmov.i16 q0, #65024 ; 0xfe00
-[^>]*> ef80 0e50 vmov.i8 q0, #0 ; 0x00
+[^>]*> ef80 0070 vmvn.i32 q0, #0 @ 0x00000000
+[^>]*> ef80 0870 vmvn.i16 q0, #0 @ 0x0000
+[^>]*> ff87 007f vmvn.i32 q0, #255 @ 0x000000ff
+[^>]*> ff87 027f vmvn.i32 q0, #65280 @ 0x0000ff00
+[^>]*> ff87 047f vmvn.i32 q0, #16711680 @ 0x00ff0000
+[^>]*> ff87 067f vmvn.i32 q0, #4278190080 @ 0xff000000
+[^>]*> ff82 0c7b vmvn.i32 q0, #44031 @ 0x0000abff
+[^>]*> ff87 087f vmvn.i16 q0, #255 @ 0x00ff
+[^>]*> ff87 0a7f vmvn.i16 q0, #65280 @ 0xff00
+[^>]*> ff87 0a5e vmov.i16 q0, #65024 @ 0xfe00
+[^>]*> ef80 0e50 vmov.i8 q0, #0 @ 0x00
[^>]*> ffb0 25c0 vmvn q1, q0
[^>]*> ffb0 25c2 vmvn q1, q1
[^>]*> ffb0 25c4 vmvn q1, q2
[^>]*> ffb0 25c8 vmvn q1, q4
[^>]*> ffb0 25ce vmvn q1, q7
-[^>]*> ef80 2070 vmvn.i32 q1, #0 ; 0x00000000
-[^>]*> ef80 2870 vmvn.i16 q1, #0 ; 0x0000
-[^>]*> ff87 207f vmvn.i32 q1, #255 ; 0x000000ff
-[^>]*> ff87 227f vmvn.i32 q1, #65280 ; 0x0000ff00
-[^>]*> ff87 247f vmvn.i32 q1, #16711680 ; 0x00ff0000
-[^>]*> ff87 267f vmvn.i32 q1, #4278190080 ; 0xff000000
-[^>]*> ff82 2c7b vmvn.i32 q1, #44031 ; 0x0000abff
-[^>]*> ff87 287f vmvn.i16 q1, #255 ; 0x00ff
-[^>]*> ff87 2a7f vmvn.i16 q1, #65280 ; 0xff00
-[^>]*> ff87 2a5e vmov.i16 q1, #65024 ; 0xfe00
-[^>]*> ef80 2e50 vmov.i8 q1, #0 ; 0x00
+[^>]*> ef80 2070 vmvn.i32 q1, #0 @ 0x00000000
+[^>]*> ef80 2870 vmvn.i16 q1, #0 @ 0x0000
+[^>]*> ff87 207f vmvn.i32 q1, #255 @ 0x000000ff
+[^>]*> ff87 227f vmvn.i32 q1, #65280 @ 0x0000ff00
+[^>]*> ff87 247f vmvn.i32 q1, #16711680 @ 0x00ff0000
+[^>]*> ff87 267f vmvn.i32 q1, #4278190080 @ 0xff000000
+[^>]*> ff82 2c7b vmvn.i32 q1, #44031 @ 0x0000abff
+[^>]*> ff87 287f vmvn.i16 q1, #255 @ 0x00ff
+[^>]*> ff87 2a7f vmvn.i16 q1, #65280 @ 0xff00
+[^>]*> ff87 2a5e vmov.i16 q1, #65024 @ 0xfe00
+[^>]*> ef80 2e50 vmov.i8 q1, #0 @ 0x00
[^>]*> ffb0 45c0 vmvn q2, q0
[^>]*> ffb0 45c2 vmvn q2, q1
[^>]*> ffb0 45c4 vmvn q2, q2
[^>]*> ffb0 45c8 vmvn q2, q4
[^>]*> ffb0 45ce vmvn q2, q7
-[^>]*> ef80 4070 vmvn.i32 q2, #0 ; 0x00000000
-[^>]*> ef80 4870 vmvn.i16 q2, #0 ; 0x0000
-[^>]*> ff87 407f vmvn.i32 q2, #255 ; 0x000000ff
-[^>]*> ff87 427f vmvn.i32 q2, #65280 ; 0x0000ff00
-[^>]*> ff87 447f vmvn.i32 q2, #16711680 ; 0x00ff0000
-[^>]*> ff87 467f vmvn.i32 q2, #4278190080 ; 0xff000000
-[^>]*> ff82 4c7b vmvn.i32 q2, #44031 ; 0x0000abff
-[^>]*> ff87 487f vmvn.i16 q2, #255 ; 0x00ff
-[^>]*> ff87 4a7f vmvn.i16 q2, #65280 ; 0xff00
-[^>]*> ff87 4a5e vmov.i16 q2, #65024 ; 0xfe00
-[^>]*> ef80 4e50 vmov.i8 q2, #0 ; 0x00
+[^>]*> ef80 4070 vmvn.i32 q2, #0 @ 0x00000000
+[^>]*> ef80 4870 vmvn.i16 q2, #0 @ 0x0000
+[^>]*> ff87 407f vmvn.i32 q2, #255 @ 0x000000ff
+[^>]*> ff87 427f vmvn.i32 q2, #65280 @ 0x0000ff00
+[^>]*> ff87 447f vmvn.i32 q2, #16711680 @ 0x00ff0000
+[^>]*> ff87 467f vmvn.i32 q2, #4278190080 @ 0xff000000
+[^>]*> ff82 4c7b vmvn.i32 q2, #44031 @ 0x0000abff
+[^>]*> ff87 487f vmvn.i16 q2, #255 @ 0x00ff
+[^>]*> ff87 4a7f vmvn.i16 q2, #65280 @ 0xff00
+[^>]*> ff87 4a5e vmov.i16 q2, #65024 @ 0xfe00
+[^>]*> ef80 4e50 vmov.i8 q2, #0 @ 0x00
[^>]*> ffb0 85c0 vmvn q4, q0
[^>]*> ffb0 85c2 vmvn q4, q1
[^>]*> ffb0 85c4 vmvn q4, q2
[^>]*> ffb0 85c8 vmvn q4, q4
[^>]*> ffb0 85ce vmvn q4, q7
-[^>]*> ef80 8070 vmvn.i32 q4, #0 ; 0x00000000
-[^>]*> ef80 8870 vmvn.i16 q4, #0 ; 0x0000
-[^>]*> ff87 807f vmvn.i32 q4, #255 ; 0x000000ff
-[^>]*> ff87 827f vmvn.i32 q4, #65280 ; 0x0000ff00
-[^>]*> ff87 847f vmvn.i32 q4, #16711680 ; 0x00ff0000
-[^>]*> ff87 867f vmvn.i32 q4, #4278190080 ; 0xff000000
-[^>]*> ff82 8c7b vmvn.i32 q4, #44031 ; 0x0000abff
-[^>]*> ff87 887f vmvn.i16 q4, #255 ; 0x00ff
-[^>]*> ff87 8a7f vmvn.i16 q4, #65280 ; 0xff00
-[^>]*> ff87 8a5e vmov.i16 q4, #65024 ; 0xfe00
-[^>]*> ef80 8e50 vmov.i8 q4, #0 ; 0x00
+[^>]*> ef80 8070 vmvn.i32 q4, #0 @ 0x00000000
+[^>]*> ef80 8870 vmvn.i16 q4, #0 @ 0x0000
+[^>]*> ff87 807f vmvn.i32 q4, #255 @ 0x000000ff
+[^>]*> ff87 827f vmvn.i32 q4, #65280 @ 0x0000ff00
+[^>]*> ff87 847f vmvn.i32 q4, #16711680 @ 0x00ff0000
+[^>]*> ff87 867f vmvn.i32 q4, #4278190080 @ 0xff000000
+[^>]*> ff82 8c7b vmvn.i32 q4, #44031 @ 0x0000abff
+[^>]*> ff87 887f vmvn.i16 q4, #255 @ 0x00ff
+[^>]*> ff87 8a7f vmvn.i16 q4, #65280 @ 0xff00
+[^>]*> ff87 8a5e vmov.i16 q4, #65024 @ 0xfe00
+[^>]*> ef80 8e50 vmov.i8 q4, #0 @ 0x00
[^>]*> ffb0 e5c0 vmvn q7, q0
[^>]*> ffb0 e5c2 vmvn q7, q1
[^>]*> ffb0 e5c4 vmvn q7, q2
[^>]*> ffb0 e5c8 vmvn q7, q4
[^>]*> ffb0 e5ce vmvn q7, q7
-[^>]*> ef80 e070 vmvn.i32 q7, #0 ; 0x00000000
-[^>]*> ef80 e870 vmvn.i16 q7, #0 ; 0x0000
-[^>]*> ff87 e07f vmvn.i32 q7, #255 ; 0x000000ff
-[^>]*> ff87 e27f vmvn.i32 q7, #65280 ; 0x0000ff00
-[^>]*> ff87 e47f vmvn.i32 q7, #16711680 ; 0x00ff0000
-[^>]*> ff87 e67f vmvn.i32 q7, #4278190080 ; 0xff000000
-[^>]*> ff82 ec7b vmvn.i32 q7, #44031 ; 0x0000abff
-[^>]*> ff87 e87f vmvn.i16 q7, #255 ; 0x00ff
-[^>]*> ff87 ea7f vmvn.i16 q7, #65280 ; 0xff00
-[^>]*> ff87 ea5e vmov.i16 q7, #65024 ; 0xfe00
-[^>]*> ef80 ee50 vmov.i8 q7, #0 ; 0x00
+[^>]*> ef80 e070 vmvn.i32 q7, #0 @ 0x00000000
+[^>]*> ef80 e870 vmvn.i16 q7, #0 @ 0x0000
+[^>]*> ff87 e07f vmvn.i32 q7, #255 @ 0x000000ff
+[^>]*> ff87 e27f vmvn.i32 q7, #65280 @ 0x0000ff00
+[^>]*> ff87 e47f vmvn.i32 q7, #16711680 @ 0x00ff0000
+[^>]*> ff87 e67f vmvn.i32 q7, #4278190080 @ 0xff000000
+[^>]*> ff82 ec7b vmvn.i32 q7, #44031 @ 0x0000abff
+[^>]*> ff87 e87f vmvn.i16 q7, #255 @ 0x00ff
+[^>]*> ff87 ea7f vmvn.i16 q7, #65280 @ 0xff00
+[^>]*> ff87 ea5e vmov.i16 q7, #65024 @ 0xfe00
+[^>]*> ef80 ee50 vmov.i8 q7, #0 @ 0x00
[^>]*> fe71 ef4d vpstete
-[^>]*> ff87 007f vmvnt.i32 q0, #255 ; 0x000000ff
-[^>]*> ff87 ca7f vmvne.i16 q6, #65280 ; 0xff00
+[^>]*> ff87 007f vmvnt.i32 q0, #255 @ 0x000000ff
+[^>]*> ff87 ca7f vmvne.i16 q6, #65280 @ 0xff00
[^>]*> ffb0 05c2 vmvnt q0, q1
[^>]*> ffb0 e5c6 vmvne q7, q3
[^>]*> ef3e e15e vorn q7, q7, q7
[^>]*> ef3e e15e vorn q7, q7, q7
[^>]*> ef3e e15e vorn q7, q7, q7
-[^>]*> ef80 0150 vorr.i32 q0, #0 ; 0x00000000
-[^>]*> ef80 e150 vorr.i32 q7, #0 ; 0x00000000
-[^>]*> ff87 015f vorr.i32 q0, #255 ; 0x000000ff
-[^>]*> ff87 035f vorr.i32 q0, #65280 ; 0x0000ff00
-[^>]*> ff87 055f vorr.i32 q0, #16711680 ; 0x00ff0000
-[^>]*> ff87 075f vorr.i32 q0, #4278190080 ; 0xff000000
-[^>]*> ef80 0950 vorr.i16 q0, #0 ; 0x0000
-[^>]*> ff87 0b5f vorr.i16 q0, #65280 ; 0xff00
-[^>]*> ff87 095f vorr.i16 q0, #255 ; 0x00ff
+[^>]*> ef80 0150 vorr.i32 q0, #0 @ 0x00000000
+[^>]*> ef80 e150 vorr.i32 q7, #0 @ 0x00000000
+[^>]*> ff87 015f vorr.i32 q0, #255 @ 0x000000ff
+[^>]*> ff87 035f vorr.i32 q0, #65280 @ 0x0000ff00
+[^>]*> ff87 055f vorr.i32 q0, #16711680 @ 0x00ff0000
+[^>]*> ff87 075f vorr.i32 q0, #4278190080 @ 0xff000000
+[^>]*> ef80 0950 vorr.i16 q0, #0 @ 0x0000
+[^>]*> ff87 0b5f vorr.i16 q0, #65280 @ 0xff00
+[^>]*> ff87 095f vorr.i16 q0, #255 @ 0x00ff
[^>]*> fe71 ef4d vpstete
[^>]*> ef32 0154 vornt q0, q1, q2
[^>]*> ef32 0154 vorne q0, q1, q2
-[^>]*> ef80 0150 vorrt.i32 q0, #0 ; 0x00000000
-[^>]*> ef80 0950 vorre.i16 q0, #0 ; 0x0000
+[^>]*> ef80 0150 vorrt.i32 q0, #0 @ 0x00000000
+[^>]*> ef80 0950 vorre.i16 q0, #0 @ 0x0000
[^>]*> ef2e e15e vmov q7, q7
[^>]*> ef2e e15e vmov q7, q7
[^>]*> ef2e e15e vmov q7, q7
-[^>]*> ef80 0150 vorr.i32 q0, #0 ; 0x00000000
-[^>]*> ff87 015f vorr.i32 q0, #255 ; 0x000000ff
-[^>]*> ff87 035f vorr.i32 q0, #65280 ; 0x0000ff00
-[^>]*> ff87 075f vorr.i32 q0, #4278190080 ; 0xff000000
-[^>]*> ff87 055f vorr.i32 q0, #16711680 ; 0x00ff0000
-[^>]*> ef80 0950 vorr.i16 q0, #0 ; 0x0000
-[^>]*> ff87 095f vorr.i16 q0, #255 ; 0x00ff
-[^>]*> ff87 0b5f vorr.i16 q0, #65280 ; 0xff00
+[^>]*> ef80 0150 vorr.i32 q0, #0 @ 0x00000000
+[^>]*> ff87 015f vorr.i32 q0, #255 @ 0x000000ff
+[^>]*> ff87 035f vorr.i32 q0, #65280 @ 0x0000ff00
+[^>]*> ff87 075f vorr.i32 q0, #4278190080 @ 0xff000000
+[^>]*> ff87 055f vorr.i32 q0, #16711680 @ 0x00ff0000
+[^>]*> ef80 0950 vorr.i16 q0, #0 @ 0x0000
+[^>]*> ff87 095f vorr.i16 q0, #255 @ 0x00ff
+[^>]*> ff87 0b5f vorr.i16 q0, #65280 @ 0xff00
[^>]*> fe71 ef4d vpstete
[^>]*> ef22 0154 vorrt q0, q1, q2
[^>]*> ef22 0154 vorre q0, q1, q2
-[^>]*> ef80 0150 vorrt.i32 q0, #0 ; 0x00000000
-[^>]*> ff87 0b5f vorre.i16 q0, #65280 ; 0xff00
+[^>]*> ef80 0150 vorrt.i32 q0, #0 @ 0x00000000
+[^>]*> ff87 0b5f vorre.i16 q0, #65280 @ 0xff00
0[0-9a-f]+ <[^>]+> bf01 itttt eq
0[0-9a-f]+ <[^>]+> ef22 0152 vorreq q0, q1, q1
0[0-9a-f]+ <[^>]+> ef21 0111 vorreq d0, d1, d1
-0[0-9a-f]+ <[^>]+> ef80 0050 vmoveq\.i32 q0, #0 ; 0x00000000
-0[0-9a-f]+ <[^>]+> ef80 0010 vmoveq\.i32 d0, #0 ; 0x00000000
+0[0-9a-f]+ <[^>]+> ef80 0050 vmoveq\.i32 q0, #0 @ 0x00000000
+0[0-9a-f]+ <[^>]+> ef80 0010 vmoveq\.i32 d0, #0 @ 0x00000000
0[0-9a-f]+ <[^>]+> bf01 itttt eq
0[0-9a-f]+ <[^>]+> ee20 2b10 vmoveq\.32 d0\[1\], r2
0[0-9a-f]+ <[^>]+> ec42 1b10 vmoveq d0, r1, r2
.*: +file format .*arm.*
Disassembly of section .text:
-0[0-9a-f]+ <[^>]+> f2800050 vmov\.i32 q0, #0 ; 0x00000000
-0[0-9a-f]+ <[^>]+> f2800f50 vmov\.f32 q0, #2 ; 0x40000000
-0[0-9a-f]+ <[^>]+> f2810f50 vmov\.f32 q0, #4 ; 0x40800000
-0[0-9a-f]+ <[^>]+> f2820f50 vmov\.f32 q0, #8 ; 0x41000000
-0[0-9a-f]+ <[^>]+> f2830f50 vmov\.f32 q0, #16 ; 0x41800000
-0[0-9a-f]+ <[^>]+> f2840f50 vmov\.f32 q0, #0\.125 ; 0x3e000000
-0[0-9a-f]+ <[^>]+> f2850f50 vmov\.f32 q0, #0\.25 ; 0x3e800000
-0[0-9a-f]+ <[^>]+> f2860f50 vmov\.f32 q0, #0\.5 ; 0x3f000000
-0[0-9a-f]+ <[^>]+> f2870f50 vmov\.f32 q0, #1 ; 0x3f800000
-0[0-9a-f]+ <[^>]+> f2800f51 vmov\.f32 q0, #2\.125 ; 0x40080000
-0[0-9a-f]+ <[^>]+> f2810f51 vmov\.f32 q0, #4\.25 ; 0x40880000
-0[0-9a-f]+ <[^>]+> f2820f51 vmov\.f32 q0, #8\.5 ; 0x41080000
-0[0-9a-f]+ <[^>]+> f2830f51 vmov\.f32 q0, #17 ; 0x41880000
-0[0-9a-f]+ <[^>]+> f2840f51 vmov\.f32 q0, #0\.1328125 ; 0x3e080000
-0[0-9a-f]+ <[^>]+> f2850f51 vmov\.f32 q0, #0\.265625 ; 0x3e880000
-0[0-9a-f]+ <[^>]+> f2860f51 vmov\.f32 q0, #0\.53125 ; 0x3f080000
-0[0-9a-f]+ <[^>]+> f2870f51 vmov\.f32 q0, #1\.0625 ; 0x3f880000
-0[0-9a-f]+ <[^>]+> f2800f52 vmov\.f32 q0, #2\.25 ; 0x40100000
-0[0-9a-f]+ <[^>]+> f2810f52 vmov\.f32 q0, #4\.5 ; 0x40900000
-0[0-9a-f]+ <[^>]+> f2820f52 vmov\.f32 q0, #9 ; 0x41100000
-0[0-9a-f]+ <[^>]+> f2830f52 vmov\.f32 q0, #18 ; 0x41900000
-0[0-9a-f]+ <[^>]+> f2840f52 vmov\.f32 q0, #0\.140625 ; 0x3e100000
-0[0-9a-f]+ <[^>]+> f2850f52 vmov\.f32 q0, #0\.28125 ; 0x3e900000
-0[0-9a-f]+ <[^>]+> f2860f52 vmov\.f32 q0, #0\.5625 ; 0x3f100000
-0[0-9a-f]+ <[^>]+> f2870f52 vmov\.f32 q0, #1\.125 ; 0x3f900000
-0[0-9a-f]+ <[^>]+> f2800f53 vmov\.f32 q0, #2\.375 ; 0x40180000
-0[0-9a-f]+ <[^>]+> f2810f53 vmov\.f32 q0, #4\.75 ; 0x40980000
-0[0-9a-f]+ <[^>]+> f2820f53 vmov\.f32 q0, #9\.5 ; 0x41180000
-0[0-9a-f]+ <[^>]+> f2830f53 vmov\.f32 q0, #19 ; 0x41980000
-0[0-9a-f]+ <[^>]+> f2840f53 vmov\.f32 q0, #0\.1484375 ; 0x3e180000
-0[0-9a-f]+ <[^>]+> f2850f53 vmov\.f32 q0, #0\.296875 ; 0x3e980000
-0[0-9a-f]+ <[^>]+> f2860f53 vmov\.f32 q0, #0\.59375 ; 0x3f180000
-0[0-9a-f]+ <[^>]+> f2870f53 vmov\.f32 q0, #1\.1875 ; 0x3f980000
-0[0-9a-f]+ <[^>]+> f2800f54 vmov\.f32 q0, #2\.5 ; 0x40200000
-0[0-9a-f]+ <[^>]+> f2810f54 vmov\.f32 q0, #5 ; 0x40a00000
-0[0-9a-f]+ <[^>]+> f2820f54 vmov\.f32 q0, #10 ; 0x41200000
-0[0-9a-f]+ <[^>]+> f2830f54 vmov\.f32 q0, #20 ; 0x41a00000
-0[0-9a-f]+ <[^>]+> f2840f54 vmov\.f32 q0, #0\.15625 ; 0x3e200000
-0[0-9a-f]+ <[^>]+> f2850f54 vmov\.f32 q0, #0\.3125 ; 0x3ea00000
-0[0-9a-f]+ <[^>]+> f2860f54 vmov\.f32 q0, #0\.625 ; 0x3f200000
-0[0-9a-f]+ <[^>]+> f2870f54 vmov\.f32 q0, #1\.25 ; 0x3fa00000
-0[0-9a-f]+ <[^>]+> f2800f55 vmov\.f32 q0, #2\.625 ; 0x40280000
-0[0-9a-f]+ <[^>]+> f2810f55 vmov\.f32 q0, #5\.25 ; 0x40a80000
-0[0-9a-f]+ <[^>]+> f2820f55 vmov\.f32 q0, #10\.5 ; 0x41280000
-0[0-9a-f]+ <[^>]+> f2830f55 vmov\.f32 q0, #21 ; 0x41a80000
-0[0-9a-f]+ <[^>]+> f2840f55 vmov\.f32 q0, #0\.1640625 ; 0x3e280000
-0[0-9a-f]+ <[^>]+> f2850f55 vmov\.f32 q0, #0\.328125 ; 0x3ea80000
-0[0-9a-f]+ <[^>]+> f2860f55 vmov\.f32 q0, #0\.65625 ; 0x3f280000
-0[0-9a-f]+ <[^>]+> f2870f55 vmov\.f32 q0, #1\.3125 ; 0x3fa80000
-0[0-9a-f]+ <[^>]+> f2800f56 vmov\.f32 q0, #2\.75 ; 0x40300000
-0[0-9a-f]+ <[^>]+> f2810f56 vmov\.f32 q0, #5\.5 ; 0x40b00000
-0[0-9a-f]+ <[^>]+> f2820f56 vmov\.f32 q0, #11 ; 0x41300000
-0[0-9a-f]+ <[^>]+> f2830f56 vmov\.f32 q0, #22 ; 0x41b00000
-0[0-9a-f]+ <[^>]+> f2840f56 vmov\.f32 q0, #0\.171875 ; 0x3e300000
-0[0-9a-f]+ <[^>]+> f2850f56 vmov\.f32 q0, #0\.34375 ; 0x3eb00000
-0[0-9a-f]+ <[^>]+> f2860f56 vmov\.f32 q0, #0\.6875 ; 0x3f300000
-0[0-9a-f]+ <[^>]+> f2870f56 vmov\.f32 q0, #1\.375 ; 0x3fb00000
-0[0-9a-f]+ <[^>]+> f2800f57 vmov\.f32 q0, #2\.875 ; 0x40380000
-0[0-9a-f]+ <[^>]+> f2810f57 vmov\.f32 q0, #5\.75 ; 0x40b80000
-0[0-9a-f]+ <[^>]+> f2820f57 vmov\.f32 q0, #11\.5 ; 0x41380000
-0[0-9a-f]+ <[^>]+> f2830f57 vmov\.f32 q0, #23 ; 0x41b80000
-0[0-9a-f]+ <[^>]+> f2840f57 vmov\.f32 q0, #0\.1796875 ; 0x3e380000
-0[0-9a-f]+ <[^>]+> f2850f57 vmov\.f32 q0, #0\.359375 ; 0x3eb80000
-0[0-9a-f]+ <[^>]+> f2860f57 vmov\.f32 q0, #0\.71875 ; 0x3f380000
-0[0-9a-f]+ <[^>]+> f2870f57 vmov\.f32 q0, #1\.4375 ; 0x3fb80000
-0[0-9a-f]+ <[^>]+> f2800f58 vmov\.f32 q0, #3 ; 0x40400000
-0[0-9a-f]+ <[^>]+> f2810f58 vmov\.f32 q0, #6 ; 0x40c00000
-0[0-9a-f]+ <[^>]+> f2820f58 vmov\.f32 q0, #12 ; 0x41400000
-0[0-9a-f]+ <[^>]+> f2830f58 vmov\.f32 q0, #24 ; 0x41c00000
-0[0-9a-f]+ <[^>]+> f2840f58 vmov\.f32 q0, #0\.1875 ; 0x3e400000
-0[0-9a-f]+ <[^>]+> f2850f58 vmov\.f32 q0, #0\.375 ; 0x3ec00000
-0[0-9a-f]+ <[^>]+> f2860f58 vmov\.f32 q0, #0\.75 ; 0x3f400000
-0[0-9a-f]+ <[^>]+> f2870f58 vmov\.f32 q0, #1\.5 ; 0x3fc00000
-0[0-9a-f]+ <[^>]+> f2800f59 vmov\.f32 q0, #3\.125 ; 0x40480000
-0[0-9a-f]+ <[^>]+> f2810f59 vmov\.f32 q0, #6\.25 ; 0x40c80000
-0[0-9a-f]+ <[^>]+> f2820f59 vmov\.f32 q0, #12\.5 ; 0x41480000
-0[0-9a-f]+ <[^>]+> f2830f59 vmov\.f32 q0, #25 ; 0x41c80000
-0[0-9a-f]+ <[^>]+> f2840f59 vmov\.f32 q0, #0\.1953125 ; 0x3e480000
-0[0-9a-f]+ <[^>]+> f2850f59 vmov\.f32 q0, #0\.390625 ; 0x3ec80000
-0[0-9a-f]+ <[^>]+> f2860f59 vmov\.f32 q0, #0\.78125 ; 0x3f480000
-0[0-9a-f]+ <[^>]+> f2870f59 vmov\.f32 q0, #1\.5625 ; 0x3fc80000
-0[0-9a-f]+ <[^>]+> f2800f5a vmov\.f32 q0, #3\.25 ; 0x40500000
-0[0-9a-f]+ <[^>]+> f2810f5a vmov\.f32 q0, #6\.5 ; 0x40d00000
-0[0-9a-f]+ <[^>]+> f2820f5a vmov\.f32 q0, #13 ; 0x41500000
-0[0-9a-f]+ <[^>]+> f2830f5a vmov\.f32 q0, #26 ; 0x41d00000
-0[0-9a-f]+ <[^>]+> f2840f5a vmov\.f32 q0, #0\.203125 ; 0x3e500000
-0[0-9a-f]+ <[^>]+> f2850f5a vmov\.f32 q0, #0\.40625 ; 0x3ed00000
-0[0-9a-f]+ <[^>]+> f2860f5a vmov\.f32 q0, #0\.8125 ; 0x3f500000
-0[0-9a-f]+ <[^>]+> f2870f5a vmov\.f32 q0, #1\.625 ; 0x3fd00000
-0[0-9a-f]+ <[^>]+> f2800f5b vmov\.f32 q0, #3\.375 ; 0x40580000
-0[0-9a-f]+ <[^>]+> f2810f5b vmov\.f32 q0, #6\.75 ; 0x40d80000
-0[0-9a-f]+ <[^>]+> f2820f5b vmov\.f32 q0, #13\.5 ; 0x41580000
-0[0-9a-f]+ <[^>]+> f2830f5b vmov\.f32 q0, #27 ; 0x41d80000
-0[0-9a-f]+ <[^>]+> f2840f5b vmov\.f32 q0, #0\.2109375 ; 0x3e580000
-0[0-9a-f]+ <[^>]+> f2850f5b vmov\.f32 q0, #0\.421875 ; 0x3ed80000
-0[0-9a-f]+ <[^>]+> f2860f5b vmov\.f32 q0, #0\.84375 ; 0x3f580000
-0[0-9a-f]+ <[^>]+> f2870f5b vmov\.f32 q0, #1\.6875 ; 0x3fd80000
-0[0-9a-f]+ <[^>]+> f2800f5c vmov\.f32 q0, #3\.5 ; 0x40600000
-0[0-9a-f]+ <[^>]+> f2810f5c vmov\.f32 q0, #7 ; 0x40e00000
-0[0-9a-f]+ <[^>]+> f2820f5c vmov\.f32 q0, #14 ; 0x41600000
-0[0-9a-f]+ <[^>]+> f2830f5c vmov\.f32 q0, #28 ; 0x41e00000
-0[0-9a-f]+ <[^>]+> f2840f5c vmov\.f32 q0, #0\.21875 ; 0x3e600000
-0[0-9a-f]+ <[^>]+> f2850f5c vmov\.f32 q0, #0\.4375 ; 0x3ee00000
-0[0-9a-f]+ <[^>]+> f2860f5c vmov\.f32 q0, #0\.875 ; 0x3f600000
-0[0-9a-f]+ <[^>]+> f2870f5c vmov\.f32 q0, #1\.75 ; 0x3fe00000
-0[0-9a-f]+ <[^>]+> f2800f5d vmov\.f32 q0, #3\.625 ; 0x40680000
-0[0-9a-f]+ <[^>]+> f2810f5d vmov\.f32 q0, #7\.25 ; 0x40e80000
-0[0-9a-f]+ <[^>]+> f2820f5d vmov\.f32 q0, #14\.5 ; 0x41680000
-0[0-9a-f]+ <[^>]+> f2830f5d vmov\.f32 q0, #29 ; 0x41e80000
-0[0-9a-f]+ <[^>]+> f2840f5d vmov\.f32 q0, #0\.2265625 ; 0x3e680000
-0[0-9a-f]+ <[^>]+> f2850f5d vmov\.f32 q0, #0\.453125 ; 0x3ee80000
-0[0-9a-f]+ <[^>]+> f2860f5d vmov\.f32 q0, #0\.90625 ; 0x3f680000
-0[0-9a-f]+ <[^>]+> f2870f5d vmov\.f32 q0, #1\.8125 ; 0x3fe80000
-0[0-9a-f]+ <[^>]+> f2800f5e vmov\.f32 q0, #3\.75 ; 0x40700000
-0[0-9a-f]+ <[^>]+> f2810f5e vmov\.f32 q0, #7\.5 ; 0x40f00000
-0[0-9a-f]+ <[^>]+> f2820f5e vmov\.f32 q0, #15 ; 0x41700000
-0[0-9a-f]+ <[^>]+> f2830f5e vmov\.f32 q0, #30 ; 0x41f00000
-0[0-9a-f]+ <[^>]+> f2840f5e vmov\.f32 q0, #0\.234375 ; 0x3e700000
-0[0-9a-f]+ <[^>]+> f2850f5e vmov\.f32 q0, #0\.46875 ; 0x3ef00000
-0[0-9a-f]+ <[^>]+> f2860f5e vmov\.f32 q0, #0\.9375 ; 0x3f700000
-0[0-9a-f]+ <[^>]+> f2870f5e vmov\.f32 q0, #1\.875 ; 0x3ff00000
-0[0-9a-f]+ <[^>]+> f2800f5f vmov\.f32 q0, #3\.875 ; 0x40780000
-0[0-9a-f]+ <[^>]+> f2810f5f vmov\.f32 q0, #7\.75 ; 0x40f80000
-0[0-9a-f]+ <[^>]+> f2820f5f vmov\.f32 q0, #15\.5 ; 0x41780000
-0[0-9a-f]+ <[^>]+> f2830f5f vmov\.f32 q0, #31 ; 0x41f80000
-0[0-9a-f]+ <[^>]+> f2840f5f vmov\.f32 q0, #0\.2421875 ; 0x3e780000
-0[0-9a-f]+ <[^>]+> f2850f5f vmov\.f32 q0, #0\.484375 ; 0x3ef80000
-0[0-9a-f]+ <[^>]+> f2860f5f vmov\.f32 q0, #0\.96875 ; 0x3f780000
-0[0-9a-f]+ <[^>]+> f2870f5f vmov\.f32 q0, #1\.9375 ; 0x3ff80000
-0[0-9a-f]+ <[^>]+> f3800650 vmov\.i32 q0, #-2147483648 ; 0x80000000
-0[0-9a-f]+ <[^>]+> f3800f50 vmov\.f32 q0, #-2 ; 0xc0000000
-0[0-9a-f]+ <[^>]+> f3810f50 vmov\.f32 q0, #-4 ; 0xc0800000
-0[0-9a-f]+ <[^>]+> f3820f50 vmov\.f32 q0, #-8 ; 0xc1000000
-0[0-9a-f]+ <[^>]+> f3830f50 vmov\.f32 q0, #-16 ; 0xc1800000
-0[0-9a-f]+ <[^>]+> f3840f50 vmov\.f32 q0, #-0\.125 ; 0xbe000000
-0[0-9a-f]+ <[^>]+> f3850f50 vmov\.f32 q0, #-0\.25 ; 0xbe800000
-0[0-9a-f]+ <[^>]+> f3860f50 vmov\.f32 q0, #-0\.5 ; 0xbf000000
-0[0-9a-f]+ <[^>]+> f3870f50 vmov\.f32 q0, #-1 ; 0xbf800000
-0[0-9a-f]+ <[^>]+> f3800f51 vmov\.f32 q0, #-2\.125 ; 0xc0080000
-0[0-9a-f]+ <[^>]+> f3810f51 vmov\.f32 q0, #-4\.25 ; 0xc0880000
-0[0-9a-f]+ <[^>]+> f3820f51 vmov\.f32 q0, #-8\.5 ; 0xc1080000
-0[0-9a-f]+ <[^>]+> f3830f51 vmov\.f32 q0, #-17 ; 0xc1880000
-0[0-9a-f]+ <[^>]+> f3840f51 vmov\.f32 q0, #-0\.1328125 ; 0xbe080000
-0[0-9a-f]+ <[^>]+> f3850f51 vmov\.f32 q0, #-0\.265625 ; 0xbe880000
-0[0-9a-f]+ <[^>]+> f3860f51 vmov\.f32 q0, #-0\.53125 ; 0xbf080000
-0[0-9a-f]+ <[^>]+> f3870f51 vmov\.f32 q0, #-1\.0625 ; 0xbf880000
-0[0-9a-f]+ <[^>]+> f3800f52 vmov\.f32 q0, #-2\.25 ; 0xc0100000
-0[0-9a-f]+ <[^>]+> f3810f52 vmov\.f32 q0, #-4\.5 ; 0xc0900000
-0[0-9a-f]+ <[^>]+> f3820f52 vmov\.f32 q0, #-9 ; 0xc1100000
-0[0-9a-f]+ <[^>]+> f3830f52 vmov\.f32 q0, #-18 ; 0xc1900000
-0[0-9a-f]+ <[^>]+> f3840f52 vmov\.f32 q0, #-0\.140625 ; 0xbe100000
-0[0-9a-f]+ <[^>]+> f3850f52 vmov\.f32 q0, #-0\.28125 ; 0xbe900000
-0[0-9a-f]+ <[^>]+> f3860f52 vmov\.f32 q0, #-0\.5625 ; 0xbf100000
-0[0-9a-f]+ <[^>]+> f3870f52 vmov\.f32 q0, #-1\.125 ; 0xbf900000
-0[0-9a-f]+ <[^>]+> f3800f53 vmov\.f32 q0, #-2\.375 ; 0xc0180000
-0[0-9a-f]+ <[^>]+> f3810f53 vmov\.f32 q0, #-4\.75 ; 0xc0980000
-0[0-9a-f]+ <[^>]+> f3820f53 vmov\.f32 q0, #-9\.5 ; 0xc1180000
-0[0-9a-f]+ <[^>]+> f3830f53 vmov\.f32 q0, #-19 ; 0xc1980000
-0[0-9a-f]+ <[^>]+> f3840f53 vmov\.f32 q0, #-0\.1484375 ; 0xbe180000
-0[0-9a-f]+ <[^>]+> f3850f53 vmov\.f32 q0, #-0\.296875 ; 0xbe980000
-0[0-9a-f]+ <[^>]+> f3860f53 vmov\.f32 q0, #-0\.59375 ; 0xbf180000
-0[0-9a-f]+ <[^>]+> f3870f53 vmov\.f32 q0, #-1\.1875 ; 0xbf980000
-0[0-9a-f]+ <[^>]+> f3800f54 vmov\.f32 q0, #-2\.5 ; 0xc0200000
-0[0-9a-f]+ <[^>]+> f3810f54 vmov\.f32 q0, #-5 ; 0xc0a00000
-0[0-9a-f]+ <[^>]+> f3820f54 vmov\.f32 q0, #-10 ; 0xc1200000
-0[0-9a-f]+ <[^>]+> f3830f54 vmov\.f32 q0, #-20 ; 0xc1a00000
-0[0-9a-f]+ <[^>]+> f3840f54 vmov\.f32 q0, #-0\.15625 ; 0xbe200000
-0[0-9a-f]+ <[^>]+> f3850f54 vmov\.f32 q0, #-0\.3125 ; 0xbea00000
-0[0-9a-f]+ <[^>]+> f3860f54 vmov\.f32 q0, #-0\.625 ; 0xbf200000
-0[0-9a-f]+ <[^>]+> f3870f54 vmov\.f32 q0, #-1\.25 ; 0xbfa00000
-0[0-9a-f]+ <[^>]+> f3800f55 vmov\.f32 q0, #-2\.625 ; 0xc0280000
-0[0-9a-f]+ <[^>]+> f3810f55 vmov\.f32 q0, #-5\.25 ; 0xc0a80000
-0[0-9a-f]+ <[^>]+> f3820f55 vmov\.f32 q0, #-10\.5 ; 0xc1280000
-0[0-9a-f]+ <[^>]+> f3830f55 vmov\.f32 q0, #-21 ; 0xc1a80000
-0[0-9a-f]+ <[^>]+> f3840f55 vmov\.f32 q0, #-0\.1640625 ; 0xbe280000
-0[0-9a-f]+ <[^>]+> f3850f55 vmov\.f32 q0, #-0\.328125 ; 0xbea80000
-0[0-9a-f]+ <[^>]+> f3860f55 vmov\.f32 q0, #-0\.65625 ; 0xbf280000
-0[0-9a-f]+ <[^>]+> f3870f55 vmov\.f32 q0, #-1\.3125 ; 0xbfa80000
-0[0-9a-f]+ <[^>]+> f3800f56 vmov\.f32 q0, #-2\.75 ; 0xc0300000
-0[0-9a-f]+ <[^>]+> f3810f56 vmov\.f32 q0, #-5\.5 ; 0xc0b00000
-0[0-9a-f]+ <[^>]+> f3820f56 vmov\.f32 q0, #-11 ; 0xc1300000
-0[0-9a-f]+ <[^>]+> f3830f56 vmov\.f32 q0, #-22 ; 0xc1b00000
-0[0-9a-f]+ <[^>]+> f3840f56 vmov\.f32 q0, #-0\.171875 ; 0xbe300000
-0[0-9a-f]+ <[^>]+> f3850f56 vmov\.f32 q0, #-0\.34375 ; 0xbeb00000
-0[0-9a-f]+ <[^>]+> f3860f56 vmov\.f32 q0, #-0\.6875 ; 0xbf300000
-0[0-9a-f]+ <[^>]+> f3870f56 vmov\.f32 q0, #-1\.375 ; 0xbfb00000
-0[0-9a-f]+ <[^>]+> f3800f57 vmov\.f32 q0, #-2\.875 ; 0xc0380000
-0[0-9a-f]+ <[^>]+> f3810f57 vmov\.f32 q0, #-5\.75 ; 0xc0b80000
-0[0-9a-f]+ <[^>]+> f3820f57 vmov\.f32 q0, #-11\.5 ; 0xc1380000
-0[0-9a-f]+ <[^>]+> f3830f57 vmov\.f32 q0, #-23 ; 0xc1b80000
-0[0-9a-f]+ <[^>]+> f3840f57 vmov\.f32 q0, #-0\.1796875 ; 0xbe380000
-0[0-9a-f]+ <[^>]+> f3850f57 vmov\.f32 q0, #-0\.359375 ; 0xbeb80000
-0[0-9a-f]+ <[^>]+> f3860f57 vmov\.f32 q0, #-0\.71875 ; 0xbf380000
-0[0-9a-f]+ <[^>]+> f3870f57 vmov\.f32 q0, #-1\.4375 ; 0xbfb80000
-0[0-9a-f]+ <[^>]+> f3800f58 vmov\.f32 q0, #-3 ; 0xc0400000
-0[0-9a-f]+ <[^>]+> f3810f58 vmov\.f32 q0, #-6 ; 0xc0c00000
-0[0-9a-f]+ <[^>]+> f3820f58 vmov\.f32 q0, #-12 ; 0xc1400000
-0[0-9a-f]+ <[^>]+> f3830f58 vmov\.f32 q0, #-24 ; 0xc1c00000
-0[0-9a-f]+ <[^>]+> f3840f58 vmov\.f32 q0, #-0\.1875 ; 0xbe400000
-0[0-9a-f]+ <[^>]+> f3850f58 vmov\.f32 q0, #-0\.375 ; 0xbec00000
-0[0-9a-f]+ <[^>]+> f3860f58 vmov\.f32 q0, #-0\.75 ; 0xbf400000
-0[0-9a-f]+ <[^>]+> f3870f58 vmov\.f32 q0, #-1\.5 ; 0xbfc00000
-0[0-9a-f]+ <[^>]+> f3800f59 vmov\.f32 q0, #-3\.125 ; 0xc0480000
-0[0-9a-f]+ <[^>]+> f3810f59 vmov\.f32 q0, #-6\.25 ; 0xc0c80000
-0[0-9a-f]+ <[^>]+> f3820f59 vmov\.f32 q0, #-12\.5 ; 0xc1480000
-0[0-9a-f]+ <[^>]+> f3830f59 vmov\.f32 q0, #-25 ; 0xc1c80000
-0[0-9a-f]+ <[^>]+> f3840f59 vmov\.f32 q0, #-0\.1953125 ; 0xbe480000
-0[0-9a-f]+ <[^>]+> f3850f59 vmov\.f32 q0, #-0\.390625 ; 0xbec80000
-0[0-9a-f]+ <[^>]+> f3860f59 vmov\.f32 q0, #-0\.78125 ; 0xbf480000
-0[0-9a-f]+ <[^>]+> f3870f59 vmov\.f32 q0, #-1\.5625 ; 0xbfc80000
-0[0-9a-f]+ <[^>]+> f3800f5a vmov\.f32 q0, #-3\.25 ; 0xc0500000
-0[0-9a-f]+ <[^>]+> f3810f5a vmov\.f32 q0, #-6\.5 ; 0xc0d00000
-0[0-9a-f]+ <[^>]+> f3820f5a vmov\.f32 q0, #-13 ; 0xc1500000
-0[0-9a-f]+ <[^>]+> f3830f5a vmov\.f32 q0, #-26 ; 0xc1d00000
-0[0-9a-f]+ <[^>]+> f3840f5a vmov\.f32 q0, #-0\.203125 ; 0xbe500000
-0[0-9a-f]+ <[^>]+> f3850f5a vmov\.f32 q0, #-0\.40625 ; 0xbed00000
-0[0-9a-f]+ <[^>]+> f3860f5a vmov\.f32 q0, #-0\.8125 ; 0xbf500000
-0[0-9a-f]+ <[^>]+> f3870f5a vmov\.f32 q0, #-1\.625 ; 0xbfd00000
-0[0-9a-f]+ <[^>]+> f3800f5b vmov\.f32 q0, #-3\.375 ; 0xc0580000
-0[0-9a-f]+ <[^>]+> f3810f5b vmov\.f32 q0, #-6\.75 ; 0xc0d80000
-0[0-9a-f]+ <[^>]+> f3820f5b vmov\.f32 q0, #-13\.5 ; 0xc1580000
-0[0-9a-f]+ <[^>]+> f3830f5b vmov\.f32 q0, #-27 ; 0xc1d80000
-0[0-9a-f]+ <[^>]+> f3840f5b vmov\.f32 q0, #-0\.2109375 ; 0xbe580000
-0[0-9a-f]+ <[^>]+> f3850f5b vmov\.f32 q0, #-0\.421875 ; 0xbed80000
-0[0-9a-f]+ <[^>]+> f3860f5b vmov\.f32 q0, #-0\.84375 ; 0xbf580000
-0[0-9a-f]+ <[^>]+> f3870f5b vmov\.f32 q0, #-1\.6875 ; 0xbfd80000
-0[0-9a-f]+ <[^>]+> f3800f5c vmov\.f32 q0, #-3\.5 ; 0xc0600000
-0[0-9a-f]+ <[^>]+> f3810f5c vmov\.f32 q0, #-7 ; 0xc0e00000
-0[0-9a-f]+ <[^>]+> f3820f5c vmov\.f32 q0, #-14 ; 0xc1600000
-0[0-9a-f]+ <[^>]+> f3830f5c vmov\.f32 q0, #-28 ; 0xc1e00000
-0[0-9a-f]+ <[^>]+> f3840f5c vmov\.f32 q0, #-0\.21875 ; 0xbe600000
-0[0-9a-f]+ <[^>]+> f3850f5c vmov\.f32 q0, #-0\.4375 ; 0xbee00000
-0[0-9a-f]+ <[^>]+> f3860f5c vmov\.f32 q0, #-0\.875 ; 0xbf600000
-0[0-9a-f]+ <[^>]+> f3870f5c vmov\.f32 q0, #-1\.75 ; 0xbfe00000
-0[0-9a-f]+ <[^>]+> f3800f5d vmov\.f32 q0, #-3\.625 ; 0xc0680000
-0[0-9a-f]+ <[^>]+> f3810f5d vmov\.f32 q0, #-7\.25 ; 0xc0e80000
-0[0-9a-f]+ <[^>]+> f3820f5d vmov\.f32 q0, #-14\.5 ; 0xc1680000
-0[0-9a-f]+ <[^>]+> f3830f5d vmov\.f32 q0, #-29 ; 0xc1e80000
-0[0-9a-f]+ <[^>]+> f3840f5d vmov\.f32 q0, #-0\.2265625 ; 0xbe680000
-0[0-9a-f]+ <[^>]+> f3850f5d vmov\.f32 q0, #-0\.453125 ; 0xbee80000
-0[0-9a-f]+ <[^>]+> f3860f5d vmov\.f32 q0, #-0\.90625 ; 0xbf680000
-0[0-9a-f]+ <[^>]+> f3870f5d vmov\.f32 q0, #-1\.8125 ; 0xbfe80000
-0[0-9a-f]+ <[^>]+> f3800f5e vmov\.f32 q0, #-3\.75 ; 0xc0700000
-0[0-9a-f]+ <[^>]+> f3810f5e vmov\.f32 q0, #-7\.5 ; 0xc0f00000
-0[0-9a-f]+ <[^>]+> f3820f5e vmov\.f32 q0, #-15 ; 0xc1700000
-0[0-9a-f]+ <[^>]+> f3830f5e vmov\.f32 q0, #-30 ; 0xc1f00000
-0[0-9a-f]+ <[^>]+> f3840f5e vmov\.f32 q0, #-0\.234375 ; 0xbe700000
-0[0-9a-f]+ <[^>]+> f3850f5e vmov\.f32 q0, #-0\.46875 ; 0xbef00000
-0[0-9a-f]+ <[^>]+> f3860f5e vmov\.f32 q0, #-0\.9375 ; 0xbf700000
-0[0-9a-f]+ <[^>]+> f3870f5e vmov\.f32 q0, #-1\.875 ; 0xbff00000
-0[0-9a-f]+ <[^>]+> f3800f5f vmov\.f32 q0, #-3\.875 ; 0xc0780000
-0[0-9a-f]+ <[^>]+> f3810f5f vmov\.f32 q0, #-7\.75 ; 0xc0f80000
-0[0-9a-f]+ <[^>]+> f3820f5f vmov\.f32 q0, #-15\.5 ; 0xc1780000
-0[0-9a-f]+ <[^>]+> f3830f5f vmov\.f32 q0, #-31 ; 0xc1f80000
-0[0-9a-f]+ <[^>]+> f3840f5f vmov\.f32 q0, #-0\.2421875 ; 0xbe780000
-0[0-9a-f]+ <[^>]+> f3850f5f vmov\.f32 q0, #-0\.484375 ; 0xbef80000
-0[0-9a-f]+ <[^>]+> f3860f5f vmov\.f32 q0, #-0\.96875 ; 0xbf780000
-0[0-9a-f]+ <[^>]+> f3870f5f vmov\.f32 q0, #-1\.9375 ; 0xbff80000
+0[0-9a-f]+ <[^>]+> f2800050 vmov\.i32 q0, #0 @ 0x00000000
+0[0-9a-f]+ <[^>]+> f2800f50 vmov\.f32 q0, #2 @ 0x40000000
+0[0-9a-f]+ <[^>]+> f2810f50 vmov\.f32 q0, #4 @ 0x40800000
+0[0-9a-f]+ <[^>]+> f2820f50 vmov\.f32 q0, #8 @ 0x41000000
+0[0-9a-f]+ <[^>]+> f2830f50 vmov\.f32 q0, #16 @ 0x41800000
+0[0-9a-f]+ <[^>]+> f2840f50 vmov\.f32 q0, #0\.125 @ 0x3e000000
+0[0-9a-f]+ <[^>]+> f2850f50 vmov\.f32 q0, #0\.25 @ 0x3e800000
+0[0-9a-f]+ <[^>]+> f2860f50 vmov\.f32 q0, #0\.5 @ 0x3f000000
+0[0-9a-f]+ <[^>]+> f2870f50 vmov\.f32 q0, #1 @ 0x3f800000
+0[0-9a-f]+ <[^>]+> f2800f51 vmov\.f32 q0, #2\.125 @ 0x40080000
+0[0-9a-f]+ <[^>]+> f2810f51 vmov\.f32 q0, #4\.25 @ 0x40880000
+0[0-9a-f]+ <[^>]+> f2820f51 vmov\.f32 q0, #8\.5 @ 0x41080000
+0[0-9a-f]+ <[^>]+> f2830f51 vmov\.f32 q0, #17 @ 0x41880000
+0[0-9a-f]+ <[^>]+> f2840f51 vmov\.f32 q0, #0\.1328125 @ 0x3e080000
+0[0-9a-f]+ <[^>]+> f2850f51 vmov\.f32 q0, #0\.265625 @ 0x3e880000
+0[0-9a-f]+ <[^>]+> f2860f51 vmov\.f32 q0, #0\.53125 @ 0x3f080000
+0[0-9a-f]+ <[^>]+> f2870f51 vmov\.f32 q0, #1\.0625 @ 0x3f880000
+0[0-9a-f]+ <[^>]+> f2800f52 vmov\.f32 q0, #2\.25 @ 0x40100000
+0[0-9a-f]+ <[^>]+> f2810f52 vmov\.f32 q0, #4\.5 @ 0x40900000
+0[0-9a-f]+ <[^>]+> f2820f52 vmov\.f32 q0, #9 @ 0x41100000
+0[0-9a-f]+ <[^>]+> f2830f52 vmov\.f32 q0, #18 @ 0x41900000
+0[0-9a-f]+ <[^>]+> f2840f52 vmov\.f32 q0, #0\.140625 @ 0x3e100000
+0[0-9a-f]+ <[^>]+> f2850f52 vmov\.f32 q0, #0\.28125 @ 0x3e900000
+0[0-9a-f]+ <[^>]+> f2860f52 vmov\.f32 q0, #0\.5625 @ 0x3f100000
+0[0-9a-f]+ <[^>]+> f2870f52 vmov\.f32 q0, #1\.125 @ 0x3f900000
+0[0-9a-f]+ <[^>]+> f2800f53 vmov\.f32 q0, #2\.375 @ 0x40180000
+0[0-9a-f]+ <[^>]+> f2810f53 vmov\.f32 q0, #4\.75 @ 0x40980000
+0[0-9a-f]+ <[^>]+> f2820f53 vmov\.f32 q0, #9\.5 @ 0x41180000
+0[0-9a-f]+ <[^>]+> f2830f53 vmov\.f32 q0, #19 @ 0x41980000
+0[0-9a-f]+ <[^>]+> f2840f53 vmov\.f32 q0, #0\.1484375 @ 0x3e180000
+0[0-9a-f]+ <[^>]+> f2850f53 vmov\.f32 q0, #0\.296875 @ 0x3e980000
+0[0-9a-f]+ <[^>]+> f2860f53 vmov\.f32 q0, #0\.59375 @ 0x3f180000
+0[0-9a-f]+ <[^>]+> f2870f53 vmov\.f32 q0, #1\.1875 @ 0x3f980000
+0[0-9a-f]+ <[^>]+> f2800f54 vmov\.f32 q0, #2\.5 @ 0x40200000
+0[0-9a-f]+ <[^>]+> f2810f54 vmov\.f32 q0, #5 @ 0x40a00000
+0[0-9a-f]+ <[^>]+> f2820f54 vmov\.f32 q0, #10 @ 0x41200000
+0[0-9a-f]+ <[^>]+> f2830f54 vmov\.f32 q0, #20 @ 0x41a00000
+0[0-9a-f]+ <[^>]+> f2840f54 vmov\.f32 q0, #0\.15625 @ 0x3e200000
+0[0-9a-f]+ <[^>]+> f2850f54 vmov\.f32 q0, #0\.3125 @ 0x3ea00000
+0[0-9a-f]+ <[^>]+> f2860f54 vmov\.f32 q0, #0\.625 @ 0x3f200000
+0[0-9a-f]+ <[^>]+> f2870f54 vmov\.f32 q0, #1\.25 @ 0x3fa00000
+0[0-9a-f]+ <[^>]+> f2800f55 vmov\.f32 q0, #2\.625 @ 0x40280000
+0[0-9a-f]+ <[^>]+> f2810f55 vmov\.f32 q0, #5\.25 @ 0x40a80000
+0[0-9a-f]+ <[^>]+> f2820f55 vmov\.f32 q0, #10\.5 @ 0x41280000
+0[0-9a-f]+ <[^>]+> f2830f55 vmov\.f32 q0, #21 @ 0x41a80000
+0[0-9a-f]+ <[^>]+> f2840f55 vmov\.f32 q0, #0\.1640625 @ 0x3e280000
+0[0-9a-f]+ <[^>]+> f2850f55 vmov\.f32 q0, #0\.328125 @ 0x3ea80000
+0[0-9a-f]+ <[^>]+> f2860f55 vmov\.f32 q0, #0\.65625 @ 0x3f280000
+0[0-9a-f]+ <[^>]+> f2870f55 vmov\.f32 q0, #1\.3125 @ 0x3fa80000
+0[0-9a-f]+ <[^>]+> f2800f56 vmov\.f32 q0, #2\.75 @ 0x40300000
+0[0-9a-f]+ <[^>]+> f2810f56 vmov\.f32 q0, #5\.5 @ 0x40b00000
+0[0-9a-f]+ <[^>]+> f2820f56 vmov\.f32 q0, #11 @ 0x41300000
+0[0-9a-f]+ <[^>]+> f2830f56 vmov\.f32 q0, #22 @ 0x41b00000
+0[0-9a-f]+ <[^>]+> f2840f56 vmov\.f32 q0, #0\.171875 @ 0x3e300000
+0[0-9a-f]+ <[^>]+> f2850f56 vmov\.f32 q0, #0\.34375 @ 0x3eb00000
+0[0-9a-f]+ <[^>]+> f2860f56 vmov\.f32 q0, #0\.6875 @ 0x3f300000
+0[0-9a-f]+ <[^>]+> f2870f56 vmov\.f32 q0, #1\.375 @ 0x3fb00000
+0[0-9a-f]+ <[^>]+> f2800f57 vmov\.f32 q0, #2\.875 @ 0x40380000
+0[0-9a-f]+ <[^>]+> f2810f57 vmov\.f32 q0, #5\.75 @ 0x40b80000
+0[0-9a-f]+ <[^>]+> f2820f57 vmov\.f32 q0, #11\.5 @ 0x41380000
+0[0-9a-f]+ <[^>]+> f2830f57 vmov\.f32 q0, #23 @ 0x41b80000
+0[0-9a-f]+ <[^>]+> f2840f57 vmov\.f32 q0, #0\.1796875 @ 0x3e380000
+0[0-9a-f]+ <[^>]+> f2850f57 vmov\.f32 q0, #0\.359375 @ 0x3eb80000
+0[0-9a-f]+ <[^>]+> f2860f57 vmov\.f32 q0, #0\.71875 @ 0x3f380000
+0[0-9a-f]+ <[^>]+> f2870f57 vmov\.f32 q0, #1\.4375 @ 0x3fb80000
+0[0-9a-f]+ <[^>]+> f2800f58 vmov\.f32 q0, #3 @ 0x40400000
+0[0-9a-f]+ <[^>]+> f2810f58 vmov\.f32 q0, #6 @ 0x40c00000
+0[0-9a-f]+ <[^>]+> f2820f58 vmov\.f32 q0, #12 @ 0x41400000
+0[0-9a-f]+ <[^>]+> f2830f58 vmov\.f32 q0, #24 @ 0x41c00000
+0[0-9a-f]+ <[^>]+> f2840f58 vmov\.f32 q0, #0\.1875 @ 0x3e400000
+0[0-9a-f]+ <[^>]+> f2850f58 vmov\.f32 q0, #0\.375 @ 0x3ec00000
+0[0-9a-f]+ <[^>]+> f2860f58 vmov\.f32 q0, #0\.75 @ 0x3f400000
+0[0-9a-f]+ <[^>]+> f2870f58 vmov\.f32 q0, #1\.5 @ 0x3fc00000
+0[0-9a-f]+ <[^>]+> f2800f59 vmov\.f32 q0, #3\.125 @ 0x40480000
+0[0-9a-f]+ <[^>]+> f2810f59 vmov\.f32 q0, #6\.25 @ 0x40c80000
+0[0-9a-f]+ <[^>]+> f2820f59 vmov\.f32 q0, #12\.5 @ 0x41480000
+0[0-9a-f]+ <[^>]+> f2830f59 vmov\.f32 q0, #25 @ 0x41c80000
+0[0-9a-f]+ <[^>]+> f2840f59 vmov\.f32 q0, #0\.1953125 @ 0x3e480000
+0[0-9a-f]+ <[^>]+> f2850f59 vmov\.f32 q0, #0\.390625 @ 0x3ec80000
+0[0-9a-f]+ <[^>]+> f2860f59 vmov\.f32 q0, #0\.78125 @ 0x3f480000
+0[0-9a-f]+ <[^>]+> f2870f59 vmov\.f32 q0, #1\.5625 @ 0x3fc80000
+0[0-9a-f]+ <[^>]+> f2800f5a vmov\.f32 q0, #3\.25 @ 0x40500000
+0[0-9a-f]+ <[^>]+> f2810f5a vmov\.f32 q0, #6\.5 @ 0x40d00000
+0[0-9a-f]+ <[^>]+> f2820f5a vmov\.f32 q0, #13 @ 0x41500000
+0[0-9a-f]+ <[^>]+> f2830f5a vmov\.f32 q0, #26 @ 0x41d00000
+0[0-9a-f]+ <[^>]+> f2840f5a vmov\.f32 q0, #0\.203125 @ 0x3e500000
+0[0-9a-f]+ <[^>]+> f2850f5a vmov\.f32 q0, #0\.40625 @ 0x3ed00000
+0[0-9a-f]+ <[^>]+> f2860f5a vmov\.f32 q0, #0\.8125 @ 0x3f500000
+0[0-9a-f]+ <[^>]+> f2870f5a vmov\.f32 q0, #1\.625 @ 0x3fd00000
+0[0-9a-f]+ <[^>]+> f2800f5b vmov\.f32 q0, #3\.375 @ 0x40580000
+0[0-9a-f]+ <[^>]+> f2810f5b vmov\.f32 q0, #6\.75 @ 0x40d80000
+0[0-9a-f]+ <[^>]+> f2820f5b vmov\.f32 q0, #13\.5 @ 0x41580000
+0[0-9a-f]+ <[^>]+> f2830f5b vmov\.f32 q0, #27 @ 0x41d80000
+0[0-9a-f]+ <[^>]+> f2840f5b vmov\.f32 q0, #0\.2109375 @ 0x3e580000
+0[0-9a-f]+ <[^>]+> f2850f5b vmov\.f32 q0, #0\.421875 @ 0x3ed80000
+0[0-9a-f]+ <[^>]+> f2860f5b vmov\.f32 q0, #0\.84375 @ 0x3f580000
+0[0-9a-f]+ <[^>]+> f2870f5b vmov\.f32 q0, #1\.6875 @ 0x3fd80000
+0[0-9a-f]+ <[^>]+> f2800f5c vmov\.f32 q0, #3\.5 @ 0x40600000
+0[0-9a-f]+ <[^>]+> f2810f5c vmov\.f32 q0, #7 @ 0x40e00000
+0[0-9a-f]+ <[^>]+> f2820f5c vmov\.f32 q0, #14 @ 0x41600000
+0[0-9a-f]+ <[^>]+> f2830f5c vmov\.f32 q0, #28 @ 0x41e00000
+0[0-9a-f]+ <[^>]+> f2840f5c vmov\.f32 q0, #0\.21875 @ 0x3e600000
+0[0-9a-f]+ <[^>]+> f2850f5c vmov\.f32 q0, #0\.4375 @ 0x3ee00000
+0[0-9a-f]+ <[^>]+> f2860f5c vmov\.f32 q0, #0\.875 @ 0x3f600000
+0[0-9a-f]+ <[^>]+> f2870f5c vmov\.f32 q0, #1\.75 @ 0x3fe00000
+0[0-9a-f]+ <[^>]+> f2800f5d vmov\.f32 q0, #3\.625 @ 0x40680000
+0[0-9a-f]+ <[^>]+> f2810f5d vmov\.f32 q0, #7\.25 @ 0x40e80000
+0[0-9a-f]+ <[^>]+> f2820f5d vmov\.f32 q0, #14\.5 @ 0x41680000
+0[0-9a-f]+ <[^>]+> f2830f5d vmov\.f32 q0, #29 @ 0x41e80000
+0[0-9a-f]+ <[^>]+> f2840f5d vmov\.f32 q0, #0\.2265625 @ 0x3e680000
+0[0-9a-f]+ <[^>]+> f2850f5d vmov\.f32 q0, #0\.453125 @ 0x3ee80000
+0[0-9a-f]+ <[^>]+> f2860f5d vmov\.f32 q0, #0\.90625 @ 0x3f680000
+0[0-9a-f]+ <[^>]+> f2870f5d vmov\.f32 q0, #1\.8125 @ 0x3fe80000
+0[0-9a-f]+ <[^>]+> f2800f5e vmov\.f32 q0, #3\.75 @ 0x40700000
+0[0-9a-f]+ <[^>]+> f2810f5e vmov\.f32 q0, #7\.5 @ 0x40f00000
+0[0-9a-f]+ <[^>]+> f2820f5e vmov\.f32 q0, #15 @ 0x41700000
+0[0-9a-f]+ <[^>]+> f2830f5e vmov\.f32 q0, #30 @ 0x41f00000
+0[0-9a-f]+ <[^>]+> f2840f5e vmov\.f32 q0, #0\.234375 @ 0x3e700000
+0[0-9a-f]+ <[^>]+> f2850f5e vmov\.f32 q0, #0\.46875 @ 0x3ef00000
+0[0-9a-f]+ <[^>]+> f2860f5e vmov\.f32 q0, #0\.9375 @ 0x3f700000
+0[0-9a-f]+ <[^>]+> f2870f5e vmov\.f32 q0, #1\.875 @ 0x3ff00000
+0[0-9a-f]+ <[^>]+> f2800f5f vmov\.f32 q0, #3\.875 @ 0x40780000
+0[0-9a-f]+ <[^>]+> f2810f5f vmov\.f32 q0, #7\.75 @ 0x40f80000
+0[0-9a-f]+ <[^>]+> f2820f5f vmov\.f32 q0, #15\.5 @ 0x41780000
+0[0-9a-f]+ <[^>]+> f2830f5f vmov\.f32 q0, #31 @ 0x41f80000
+0[0-9a-f]+ <[^>]+> f2840f5f vmov\.f32 q0, #0\.2421875 @ 0x3e780000
+0[0-9a-f]+ <[^>]+> f2850f5f vmov\.f32 q0, #0\.484375 @ 0x3ef80000
+0[0-9a-f]+ <[^>]+> f2860f5f vmov\.f32 q0, #0\.96875 @ 0x3f780000
+0[0-9a-f]+ <[^>]+> f2870f5f vmov\.f32 q0, #1\.9375 @ 0x3ff80000
+0[0-9a-f]+ <[^>]+> f3800650 vmov\.i32 q0, #-2147483648 @ 0x80000000
+0[0-9a-f]+ <[^>]+> f3800f50 vmov\.f32 q0, #-2 @ 0xc0000000
+0[0-9a-f]+ <[^>]+> f3810f50 vmov\.f32 q0, #-4 @ 0xc0800000
+0[0-9a-f]+ <[^>]+> f3820f50 vmov\.f32 q0, #-8 @ 0xc1000000
+0[0-9a-f]+ <[^>]+> f3830f50 vmov\.f32 q0, #-16 @ 0xc1800000
+0[0-9a-f]+ <[^>]+> f3840f50 vmov\.f32 q0, #-0\.125 @ 0xbe000000
+0[0-9a-f]+ <[^>]+> f3850f50 vmov\.f32 q0, #-0\.25 @ 0xbe800000
+0[0-9a-f]+ <[^>]+> f3860f50 vmov\.f32 q0, #-0\.5 @ 0xbf000000
+0[0-9a-f]+ <[^>]+> f3870f50 vmov\.f32 q0, #-1 @ 0xbf800000
+0[0-9a-f]+ <[^>]+> f3800f51 vmov\.f32 q0, #-2\.125 @ 0xc0080000
+0[0-9a-f]+ <[^>]+> f3810f51 vmov\.f32 q0, #-4\.25 @ 0xc0880000
+0[0-9a-f]+ <[^>]+> f3820f51 vmov\.f32 q0, #-8\.5 @ 0xc1080000
+0[0-9a-f]+ <[^>]+> f3830f51 vmov\.f32 q0, #-17 @ 0xc1880000
+0[0-9a-f]+ <[^>]+> f3840f51 vmov\.f32 q0, #-0\.1328125 @ 0xbe080000
+0[0-9a-f]+ <[^>]+> f3850f51 vmov\.f32 q0, #-0\.265625 @ 0xbe880000
+0[0-9a-f]+ <[^>]+> f3860f51 vmov\.f32 q0, #-0\.53125 @ 0xbf080000
+0[0-9a-f]+ <[^>]+> f3870f51 vmov\.f32 q0, #-1\.0625 @ 0xbf880000
+0[0-9a-f]+ <[^>]+> f3800f52 vmov\.f32 q0, #-2\.25 @ 0xc0100000
+0[0-9a-f]+ <[^>]+> f3810f52 vmov\.f32 q0, #-4\.5 @ 0xc0900000
+0[0-9a-f]+ <[^>]+> f3820f52 vmov\.f32 q0, #-9 @ 0xc1100000
+0[0-9a-f]+ <[^>]+> f3830f52 vmov\.f32 q0, #-18 @ 0xc1900000
+0[0-9a-f]+ <[^>]+> f3840f52 vmov\.f32 q0, #-0\.140625 @ 0xbe100000
+0[0-9a-f]+ <[^>]+> f3850f52 vmov\.f32 q0, #-0\.28125 @ 0xbe900000
+0[0-9a-f]+ <[^>]+> f3860f52 vmov\.f32 q0, #-0\.5625 @ 0xbf100000
+0[0-9a-f]+ <[^>]+> f3870f52 vmov\.f32 q0, #-1\.125 @ 0xbf900000
+0[0-9a-f]+ <[^>]+> f3800f53 vmov\.f32 q0, #-2\.375 @ 0xc0180000
+0[0-9a-f]+ <[^>]+> f3810f53 vmov\.f32 q0, #-4\.75 @ 0xc0980000
+0[0-9a-f]+ <[^>]+> f3820f53 vmov\.f32 q0, #-9\.5 @ 0xc1180000
+0[0-9a-f]+ <[^>]+> f3830f53 vmov\.f32 q0, #-19 @ 0xc1980000
+0[0-9a-f]+ <[^>]+> f3840f53 vmov\.f32 q0, #-0\.1484375 @ 0xbe180000
+0[0-9a-f]+ <[^>]+> f3850f53 vmov\.f32 q0, #-0\.296875 @ 0xbe980000
+0[0-9a-f]+ <[^>]+> f3860f53 vmov\.f32 q0, #-0\.59375 @ 0xbf180000
+0[0-9a-f]+ <[^>]+> f3870f53 vmov\.f32 q0, #-1\.1875 @ 0xbf980000
+0[0-9a-f]+ <[^>]+> f3800f54 vmov\.f32 q0, #-2\.5 @ 0xc0200000
+0[0-9a-f]+ <[^>]+> f3810f54 vmov\.f32 q0, #-5 @ 0xc0a00000
+0[0-9a-f]+ <[^>]+> f3820f54 vmov\.f32 q0, #-10 @ 0xc1200000
+0[0-9a-f]+ <[^>]+> f3830f54 vmov\.f32 q0, #-20 @ 0xc1a00000
+0[0-9a-f]+ <[^>]+> f3840f54 vmov\.f32 q0, #-0\.15625 @ 0xbe200000
+0[0-9a-f]+ <[^>]+> f3850f54 vmov\.f32 q0, #-0\.3125 @ 0xbea00000
+0[0-9a-f]+ <[^>]+> f3860f54 vmov\.f32 q0, #-0\.625 @ 0xbf200000
+0[0-9a-f]+ <[^>]+> f3870f54 vmov\.f32 q0, #-1\.25 @ 0xbfa00000
+0[0-9a-f]+ <[^>]+> f3800f55 vmov\.f32 q0, #-2\.625 @ 0xc0280000
+0[0-9a-f]+ <[^>]+> f3810f55 vmov\.f32 q0, #-5\.25 @ 0xc0a80000
+0[0-9a-f]+ <[^>]+> f3820f55 vmov\.f32 q0, #-10\.5 @ 0xc1280000
+0[0-9a-f]+ <[^>]+> f3830f55 vmov\.f32 q0, #-21 @ 0xc1a80000
+0[0-9a-f]+ <[^>]+> f3840f55 vmov\.f32 q0, #-0\.1640625 @ 0xbe280000
+0[0-9a-f]+ <[^>]+> f3850f55 vmov\.f32 q0, #-0\.328125 @ 0xbea80000
+0[0-9a-f]+ <[^>]+> f3860f55 vmov\.f32 q0, #-0\.65625 @ 0xbf280000
+0[0-9a-f]+ <[^>]+> f3870f55 vmov\.f32 q0, #-1\.3125 @ 0xbfa80000
+0[0-9a-f]+ <[^>]+> f3800f56 vmov\.f32 q0, #-2\.75 @ 0xc0300000
+0[0-9a-f]+ <[^>]+> f3810f56 vmov\.f32 q0, #-5\.5 @ 0xc0b00000
+0[0-9a-f]+ <[^>]+> f3820f56 vmov\.f32 q0, #-11 @ 0xc1300000
+0[0-9a-f]+ <[^>]+> f3830f56 vmov\.f32 q0, #-22 @ 0xc1b00000
+0[0-9a-f]+ <[^>]+> f3840f56 vmov\.f32 q0, #-0\.171875 @ 0xbe300000
+0[0-9a-f]+ <[^>]+> f3850f56 vmov\.f32 q0, #-0\.34375 @ 0xbeb00000
+0[0-9a-f]+ <[^>]+> f3860f56 vmov\.f32 q0, #-0\.6875 @ 0xbf300000
+0[0-9a-f]+ <[^>]+> f3870f56 vmov\.f32 q0, #-1\.375 @ 0xbfb00000
+0[0-9a-f]+ <[^>]+> f3800f57 vmov\.f32 q0, #-2\.875 @ 0xc0380000
+0[0-9a-f]+ <[^>]+> f3810f57 vmov\.f32 q0, #-5\.75 @ 0xc0b80000
+0[0-9a-f]+ <[^>]+> f3820f57 vmov\.f32 q0, #-11\.5 @ 0xc1380000
+0[0-9a-f]+ <[^>]+> f3830f57 vmov\.f32 q0, #-23 @ 0xc1b80000
+0[0-9a-f]+ <[^>]+> f3840f57 vmov\.f32 q0, #-0\.1796875 @ 0xbe380000
+0[0-9a-f]+ <[^>]+> f3850f57 vmov\.f32 q0, #-0\.359375 @ 0xbeb80000
+0[0-9a-f]+ <[^>]+> f3860f57 vmov\.f32 q0, #-0\.71875 @ 0xbf380000
+0[0-9a-f]+ <[^>]+> f3870f57 vmov\.f32 q0, #-1\.4375 @ 0xbfb80000
+0[0-9a-f]+ <[^>]+> f3800f58 vmov\.f32 q0, #-3 @ 0xc0400000
+0[0-9a-f]+ <[^>]+> f3810f58 vmov\.f32 q0, #-6 @ 0xc0c00000
+0[0-9a-f]+ <[^>]+> f3820f58 vmov\.f32 q0, #-12 @ 0xc1400000
+0[0-9a-f]+ <[^>]+> f3830f58 vmov\.f32 q0, #-24 @ 0xc1c00000
+0[0-9a-f]+ <[^>]+> f3840f58 vmov\.f32 q0, #-0\.1875 @ 0xbe400000
+0[0-9a-f]+ <[^>]+> f3850f58 vmov\.f32 q0, #-0\.375 @ 0xbec00000
+0[0-9a-f]+ <[^>]+> f3860f58 vmov\.f32 q0, #-0\.75 @ 0xbf400000
+0[0-9a-f]+ <[^>]+> f3870f58 vmov\.f32 q0, #-1\.5 @ 0xbfc00000
+0[0-9a-f]+ <[^>]+> f3800f59 vmov\.f32 q0, #-3\.125 @ 0xc0480000
+0[0-9a-f]+ <[^>]+> f3810f59 vmov\.f32 q0, #-6\.25 @ 0xc0c80000
+0[0-9a-f]+ <[^>]+> f3820f59 vmov\.f32 q0, #-12\.5 @ 0xc1480000
+0[0-9a-f]+ <[^>]+> f3830f59 vmov\.f32 q0, #-25 @ 0xc1c80000
+0[0-9a-f]+ <[^>]+> f3840f59 vmov\.f32 q0, #-0\.1953125 @ 0xbe480000
+0[0-9a-f]+ <[^>]+> f3850f59 vmov\.f32 q0, #-0\.390625 @ 0xbec80000
+0[0-9a-f]+ <[^>]+> f3860f59 vmov\.f32 q0, #-0\.78125 @ 0xbf480000
+0[0-9a-f]+ <[^>]+> f3870f59 vmov\.f32 q0, #-1\.5625 @ 0xbfc80000
+0[0-9a-f]+ <[^>]+> f3800f5a vmov\.f32 q0, #-3\.25 @ 0xc0500000
+0[0-9a-f]+ <[^>]+> f3810f5a vmov\.f32 q0, #-6\.5 @ 0xc0d00000
+0[0-9a-f]+ <[^>]+> f3820f5a vmov\.f32 q0, #-13 @ 0xc1500000
+0[0-9a-f]+ <[^>]+> f3830f5a vmov\.f32 q0, #-26 @ 0xc1d00000
+0[0-9a-f]+ <[^>]+> f3840f5a vmov\.f32 q0, #-0\.203125 @ 0xbe500000
+0[0-9a-f]+ <[^>]+> f3850f5a vmov\.f32 q0, #-0\.40625 @ 0xbed00000
+0[0-9a-f]+ <[^>]+> f3860f5a vmov\.f32 q0, #-0\.8125 @ 0xbf500000
+0[0-9a-f]+ <[^>]+> f3870f5a vmov\.f32 q0, #-1\.625 @ 0xbfd00000
+0[0-9a-f]+ <[^>]+> f3800f5b vmov\.f32 q0, #-3\.375 @ 0xc0580000
+0[0-9a-f]+ <[^>]+> f3810f5b vmov\.f32 q0, #-6\.75 @ 0xc0d80000
+0[0-9a-f]+ <[^>]+> f3820f5b vmov\.f32 q0, #-13\.5 @ 0xc1580000
+0[0-9a-f]+ <[^>]+> f3830f5b vmov\.f32 q0, #-27 @ 0xc1d80000
+0[0-9a-f]+ <[^>]+> f3840f5b vmov\.f32 q0, #-0\.2109375 @ 0xbe580000
+0[0-9a-f]+ <[^>]+> f3850f5b vmov\.f32 q0, #-0\.421875 @ 0xbed80000
+0[0-9a-f]+ <[^>]+> f3860f5b vmov\.f32 q0, #-0\.84375 @ 0xbf580000
+0[0-9a-f]+ <[^>]+> f3870f5b vmov\.f32 q0, #-1\.6875 @ 0xbfd80000
+0[0-9a-f]+ <[^>]+> f3800f5c vmov\.f32 q0, #-3\.5 @ 0xc0600000
+0[0-9a-f]+ <[^>]+> f3810f5c vmov\.f32 q0, #-7 @ 0xc0e00000
+0[0-9a-f]+ <[^>]+> f3820f5c vmov\.f32 q0, #-14 @ 0xc1600000
+0[0-9a-f]+ <[^>]+> f3830f5c vmov\.f32 q0, #-28 @ 0xc1e00000
+0[0-9a-f]+ <[^>]+> f3840f5c vmov\.f32 q0, #-0\.21875 @ 0xbe600000
+0[0-9a-f]+ <[^>]+> f3850f5c vmov\.f32 q0, #-0\.4375 @ 0xbee00000
+0[0-9a-f]+ <[^>]+> f3860f5c vmov\.f32 q0, #-0\.875 @ 0xbf600000
+0[0-9a-f]+ <[^>]+> f3870f5c vmov\.f32 q0, #-1\.75 @ 0xbfe00000
+0[0-9a-f]+ <[^>]+> f3800f5d vmov\.f32 q0, #-3\.625 @ 0xc0680000
+0[0-9a-f]+ <[^>]+> f3810f5d vmov\.f32 q0, #-7\.25 @ 0xc0e80000
+0[0-9a-f]+ <[^>]+> f3820f5d vmov\.f32 q0, #-14\.5 @ 0xc1680000
+0[0-9a-f]+ <[^>]+> f3830f5d vmov\.f32 q0, #-29 @ 0xc1e80000
+0[0-9a-f]+ <[^>]+> f3840f5d vmov\.f32 q0, #-0\.2265625 @ 0xbe680000
+0[0-9a-f]+ <[^>]+> f3850f5d vmov\.f32 q0, #-0\.453125 @ 0xbee80000
+0[0-9a-f]+ <[^>]+> f3860f5d vmov\.f32 q0, #-0\.90625 @ 0xbf680000
+0[0-9a-f]+ <[^>]+> f3870f5d vmov\.f32 q0, #-1\.8125 @ 0xbfe80000
+0[0-9a-f]+ <[^>]+> f3800f5e vmov\.f32 q0, #-3\.75 @ 0xc0700000
+0[0-9a-f]+ <[^>]+> f3810f5e vmov\.f32 q0, #-7\.5 @ 0xc0f00000
+0[0-9a-f]+ <[^>]+> f3820f5e vmov\.f32 q0, #-15 @ 0xc1700000
+0[0-9a-f]+ <[^>]+> f3830f5e vmov\.f32 q0, #-30 @ 0xc1f00000
+0[0-9a-f]+ <[^>]+> f3840f5e vmov\.f32 q0, #-0\.234375 @ 0xbe700000
+0[0-9a-f]+ <[^>]+> f3850f5e vmov\.f32 q0, #-0\.46875 @ 0xbef00000
+0[0-9a-f]+ <[^>]+> f3860f5e vmov\.f32 q0, #-0\.9375 @ 0xbf700000
+0[0-9a-f]+ <[^>]+> f3870f5e vmov\.f32 q0, #-1\.875 @ 0xbff00000
+0[0-9a-f]+ <[^>]+> f3800f5f vmov\.f32 q0, #-3\.875 @ 0xc0780000
+0[0-9a-f]+ <[^>]+> f3810f5f vmov\.f32 q0, #-7\.75 @ 0xc0f80000
+0[0-9a-f]+ <[^>]+> f3820f5f vmov\.f32 q0, #-15\.5 @ 0xc1780000
+0[0-9a-f]+ <[^>]+> f3830f5f vmov\.f32 q0, #-31 @ 0xc1f80000
+0[0-9a-f]+ <[^>]+> f3840f5f vmov\.f32 q0, #-0\.2421875 @ 0xbe780000
+0[0-9a-f]+ <[^>]+> f3850f5f vmov\.f32 q0, #-0\.484375 @ 0xbef80000
+0[0-9a-f]+ <[^>]+> f3860f5f vmov\.f32 q0, #-0\.96875 @ 0xbf780000
+0[0-9a-f]+ <[^>]+> f3870f5f vmov\.f32 q0, #-1\.9375 @ 0xbff80000
0[0-9a-f]+ <[^>]+> f3879e3f vmov\.i64 d9, #0xffffffffffffffff
0[0-9a-f]+ <[^>]+> f3000150 veor q0, q0, q0
0[0-9a-f]+ <[^>]+> f3000150 veor q0, q0, q0
0[0-9a-f]+ <[^>]+> f3000110 veor d0, d0, d0
-0[0-9a-f]+ <[^>]+> f3820175 vbic\.i32 q0, #165 ; 0x000000a5
-0[0-9a-f]+ <[^>]+> f3820175 vbic\.i32 q0, #165 ; 0x000000a5
-0[0-9a-f]+ <[^>]+> f3820135 vbic\.i32 d0, #165 ; 0x000000a5
-0[0-9a-f]+ <[^>]+> f3820375 vbic\.i32 q0, #42240 ; 0x0000a500
-0[0-9a-f]+ <[^>]+> f3820375 vbic\.i32 q0, #42240 ; 0x0000a500
-0[0-9a-f]+ <[^>]+> f3820335 vbic\.i32 d0, #42240 ; 0x0000a500
-0[0-9a-f]+ <[^>]+> f3820575 vbic\.i32 q0, #10813440 ; 0x00a50000
-0[0-9a-f]+ <[^>]+> f3820575 vbic\.i32 q0, #10813440 ; 0x00a50000
-0[0-9a-f]+ <[^>]+> f3820535 vbic\.i32 d0, #10813440 ; 0x00a50000
-0[0-9a-f]+ <[^>]+> f3820775 vbic\.i32 q0, #-1526726656 ; 0xa5000000
-0[0-9a-f]+ <[^>]+> f3820775 vbic\.i32 q0, #-1526726656 ; 0xa5000000
-0[0-9a-f]+ <[^>]+> f3820735 vbic\.i32 d0, #-1526726656 ; 0xa5000000
-0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820935 vbic\.i16 d0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f3820b35 vbic\.i16 d0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387013f vbic\.i32 d0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387013f vbic\.i32 d0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387013f vbic\.i32 d0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387037f vbic\.i32 q0, #65280 ; 0x0000ff00
-0[0-9a-f]+ <[^>]+> f387037f vbic\.i32 q0, #65280 ; 0x0000ff00
-0[0-9a-f]+ <[^>]+> f387033f vbic\.i32 d0, #65280 ; 0x0000ff00
-0[0-9a-f]+ <[^>]+> f387057f vbic\.i32 q0, #16711680 ; 0x00ff0000
-0[0-9a-f]+ <[^>]+> f387057f vbic\.i32 q0, #16711680 ; 0x00ff0000
-0[0-9a-f]+ <[^>]+> f387053f vbic\.i32 d0, #16711680 ; 0x00ff0000
-0[0-9a-f]+ <[^>]+> f387077f vbic\.i32 q0, #-16777216 ; 0xff000000
-0[0-9a-f]+ <[^>]+> f387077f vbic\.i32 q0, #-16777216 ; 0xff000000
-0[0-9a-f]+ <[^>]+> f387073f vbic\.i32 d0, #-16777216 ; 0xff000000
-0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820935 vbic\.i16 d0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f3820b35 vbic\.i16 d0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f387097f vbic\.i16 q0, #255 ; 0x00ff
-0[0-9a-f]+ <[^>]+> f387097f vbic\.i16 q0, #255 ; 0x00ff
-0[0-9a-f]+ <[^>]+> f387093f vbic\.i16 d0, #255 ; 0x00ff
-0[0-9a-f]+ <[^>]+> f3870b7f vbic\.i16 q0, #65280 ; 0xff00
-0[0-9a-f]+ <[^>]+> f3870b7f vbic\.i16 q0, #65280 ; 0xff00
-0[0-9a-f]+ <[^>]+> f3870b3f vbic\.i16 d0, #65280 ; 0xff00
-0[0-9a-f]+ <[^>]+> f2800970 vbic\.i16 q0, #0 ; 0x0000
-0[0-9a-f]+ <[^>]+> f2800970 vbic\.i16 q0, #0 ; 0x0000
-0[0-9a-f]+ <[^>]+> f2800930 vbic\.i16 d0, #0 ; 0x0000
-0[0-9a-f]+ <[^>]+> f3820155 vorr\.i32 q0, #165 ; 0x000000a5
-0[0-9a-f]+ <[^>]+> f3820155 vorr\.i32 q0, #165 ; 0x000000a5
-0[0-9a-f]+ <[^>]+> f3820115 vorr\.i32 d0, #165 ; 0x000000a5
-0[0-9a-f]+ <[^>]+> f3820355 vorr\.i32 q0, #42240 ; 0x0000a500
-0[0-9a-f]+ <[^>]+> f3820355 vorr\.i32 q0, #42240 ; 0x0000a500
-0[0-9a-f]+ <[^>]+> f3820315 vorr\.i32 d0, #42240 ; 0x0000a500
-0[0-9a-f]+ <[^>]+> f3820555 vorr\.i32 q0, #10813440 ; 0x00a50000
-0[0-9a-f]+ <[^>]+> f3820555 vorr\.i32 q0, #10813440 ; 0x00a50000
-0[0-9a-f]+ <[^>]+> f3820515 vorr\.i32 d0, #10813440 ; 0x00a50000
-0[0-9a-f]+ <[^>]+> f3820755 vorr\.i32 q0, #-1526726656 ; 0xa5000000
-0[0-9a-f]+ <[^>]+> f3820755 vorr\.i32 q0, #-1526726656 ; 0xa5000000
-0[0-9a-f]+ <[^>]+> f3820715 vorr\.i32 d0, #-1526726656 ; 0xa5000000
-0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820915 vorr\.i16 d0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f3820b15 vorr\.i16 d0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387035f vorr\.i32 q0, #65280 ; 0x0000ff00
-0[0-9a-f]+ <[^>]+> f387035f vorr\.i32 q0, #65280 ; 0x0000ff00
-0[0-9a-f]+ <[^>]+> f387031f vorr\.i32 d0, #65280 ; 0x0000ff00
-0[0-9a-f]+ <[^>]+> f387055f vorr\.i32 q0, #16711680 ; 0x00ff0000
-0[0-9a-f]+ <[^>]+> f387055f vorr\.i32 q0, #16711680 ; 0x00ff0000
-0[0-9a-f]+ <[^>]+> f387051f vorr\.i32 d0, #16711680 ; 0x00ff0000
-0[0-9a-f]+ <[^>]+> f387075f vorr\.i32 q0, #-16777216 ; 0xff000000
-0[0-9a-f]+ <[^>]+> f387075f vorr\.i32 q0, #-16777216 ; 0xff000000
-0[0-9a-f]+ <[^>]+> f387071f vorr\.i32 d0, #-16777216 ; 0xff000000
-0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820915 vorr\.i16 d0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f3820b15 vorr\.i16 d0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f387095f vorr\.i16 q0, #255 ; 0x00ff
-0[0-9a-f]+ <[^>]+> f387095f vorr\.i16 q0, #255 ; 0x00ff
-0[0-9a-f]+ <[^>]+> f387091f vorr\.i16 d0, #255 ; 0x00ff
-0[0-9a-f]+ <[^>]+> f3870b5f vorr\.i16 q0, #65280 ; 0xff00
-0[0-9a-f]+ <[^>]+> f3870b5f vorr\.i16 q0, #65280 ; 0xff00
-0[0-9a-f]+ <[^>]+> f3870b1f vorr\.i16 d0, #65280 ; 0xff00
-0[0-9a-f]+ <[^>]+> f2800950 vorr\.i16 q0, #0 ; 0x0000
-0[0-9a-f]+ <[^>]+> f2800950 vorr\.i16 q0, #0 ; 0x0000
-0[0-9a-f]+ <[^>]+> f2800910 vorr\.i16 d0, #0 ; 0x0000
-0[0-9a-f]+ <[^>]+> f3820175 vbic\.i32 q0, #165 ; 0x000000a5
-0[0-9a-f]+ <[^>]+> f3820175 vbic\.i32 q0, #165 ; 0x000000a5
-0[0-9a-f]+ <[^>]+> f3820135 vbic\.i32 d0, #165 ; 0x000000a5
-0[0-9a-f]+ <[^>]+> f3820375 vbic\.i32 q0, #42240 ; 0x0000a500
-0[0-9a-f]+ <[^>]+> f3820375 vbic\.i32 q0, #42240 ; 0x0000a500
-0[0-9a-f]+ <[^>]+> f3820335 vbic\.i32 d0, #42240 ; 0x0000a500
-0[0-9a-f]+ <[^>]+> f3820575 vbic\.i32 q0, #10813440 ; 0x00a50000
-0[0-9a-f]+ <[^>]+> f3820575 vbic\.i32 q0, #10813440 ; 0x00a50000
-0[0-9a-f]+ <[^>]+> f3820535 vbic\.i32 d0, #10813440 ; 0x00a50000
-0[0-9a-f]+ <[^>]+> f3820775 vbic\.i32 q0, #-1526726656 ; 0xa5000000
-0[0-9a-f]+ <[^>]+> f3820775 vbic\.i32 q0, #-1526726656 ; 0xa5000000
-0[0-9a-f]+ <[^>]+> f3820735 vbic\.i32 d0, #-1526726656 ; 0xa5000000
-0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820935 vbic\.i16 d0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f3820b35 vbic\.i16 d0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387013f vbic\.i32 d0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387013f vbic\.i32 d0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387013f vbic\.i32 d0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387037f vbic\.i32 q0, #65280 ; 0x0000ff00
-0[0-9a-f]+ <[^>]+> f387037f vbic\.i32 q0, #65280 ; 0x0000ff00
-0[0-9a-f]+ <[^>]+> f387033f vbic\.i32 d0, #65280 ; 0x0000ff00
-0[0-9a-f]+ <[^>]+> f387057f vbic\.i32 q0, #16711680 ; 0x00ff0000
-0[0-9a-f]+ <[^>]+> f387057f vbic\.i32 q0, #16711680 ; 0x00ff0000
-0[0-9a-f]+ <[^>]+> f387053f vbic\.i32 d0, #16711680 ; 0x00ff0000
-0[0-9a-f]+ <[^>]+> f387077f vbic\.i32 q0, #-16777216 ; 0xff000000
-0[0-9a-f]+ <[^>]+> f387077f vbic\.i32 q0, #-16777216 ; 0xff000000
-0[0-9a-f]+ <[^>]+> f387073f vbic\.i32 d0, #-16777216 ; 0xff000000
-0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820935 vbic\.i16 d0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f3820b35 vbic\.i16 d0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f387097f vbic\.i16 q0, #255 ; 0x00ff
-0[0-9a-f]+ <[^>]+> f387097f vbic\.i16 q0, #255 ; 0x00ff
-0[0-9a-f]+ <[^>]+> f387093f vbic\.i16 d0, #255 ; 0x00ff
-0[0-9a-f]+ <[^>]+> f3870b7f vbic\.i16 q0, #65280 ; 0xff00
-0[0-9a-f]+ <[^>]+> f3870b7f vbic\.i16 q0, #65280 ; 0xff00
-0[0-9a-f]+ <[^>]+> f3870b3f vbic\.i16 d0, #65280 ; 0xff00
-0[0-9a-f]+ <[^>]+> f2800970 vbic\.i16 q0, #0 ; 0x0000
-0[0-9a-f]+ <[^>]+> f2800970 vbic\.i16 q0, #0 ; 0x0000
-0[0-9a-f]+ <[^>]+> f2800930 vbic\.i16 d0, #0 ; 0x0000
-0[0-9a-f]+ <[^>]+> f3820155 vorr\.i32 q0, #165 ; 0x000000a5
-0[0-9a-f]+ <[^>]+> f3820155 vorr\.i32 q0, #165 ; 0x000000a5
-0[0-9a-f]+ <[^>]+> f3820115 vorr\.i32 d0, #165 ; 0x000000a5
-0[0-9a-f]+ <[^>]+> f3820355 vorr\.i32 q0, #42240 ; 0x0000a500
-0[0-9a-f]+ <[^>]+> f3820355 vorr\.i32 q0, #42240 ; 0x0000a500
-0[0-9a-f]+ <[^>]+> f3820315 vorr\.i32 d0, #42240 ; 0x0000a500
-0[0-9a-f]+ <[^>]+> f3820555 vorr\.i32 q0, #10813440 ; 0x00a50000
-0[0-9a-f]+ <[^>]+> f3820555 vorr\.i32 q0, #10813440 ; 0x00a50000
-0[0-9a-f]+ <[^>]+> f3820515 vorr\.i32 d0, #10813440 ; 0x00a50000
-0[0-9a-f]+ <[^>]+> f3820755 vorr\.i32 q0, #-1526726656 ; 0xa5000000
-0[0-9a-f]+ <[^>]+> f3820755 vorr\.i32 q0, #-1526726656 ; 0xa5000000
-0[0-9a-f]+ <[^>]+> f3820715 vorr\.i32 d0, #-1526726656 ; 0xa5000000
-0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820915 vorr\.i16 d0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f3820b15 vorr\.i16 d0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 ; 0x000000ff
-0[0-9a-f]+ <[^>]+> f387035f vorr\.i32 q0, #65280 ; 0x0000ff00
-0[0-9a-f]+ <[^>]+> f387035f vorr\.i32 q0, #65280 ; 0x0000ff00
-0[0-9a-f]+ <[^>]+> f387031f vorr\.i32 d0, #65280 ; 0x0000ff00
-0[0-9a-f]+ <[^>]+> f387055f vorr\.i32 q0, #16711680 ; 0x00ff0000
-0[0-9a-f]+ <[^>]+> f387055f vorr\.i32 q0, #16711680 ; 0x00ff0000
-0[0-9a-f]+ <[^>]+> f387051f vorr\.i32 d0, #16711680 ; 0x00ff0000
-0[0-9a-f]+ <[^>]+> f387075f vorr\.i32 q0, #-16777216 ; 0xff000000
-0[0-9a-f]+ <[^>]+> f387075f vorr\.i32 q0, #-16777216 ; 0xff000000
-0[0-9a-f]+ <[^>]+> f387071f vorr\.i32 d0, #-16777216 ; 0xff000000
-0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820915 vorr\.i16 d0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f3820b15 vorr\.i16 d0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f387095f vorr\.i16 q0, #255 ; 0x00ff
-0[0-9a-f]+ <[^>]+> f387095f vorr\.i16 q0, #255 ; 0x00ff
-0[0-9a-f]+ <[^>]+> f387091f vorr\.i16 d0, #255 ; 0x00ff
-0[0-9a-f]+ <[^>]+> f3870b5f vorr\.i16 q0, #65280 ; 0xff00
-0[0-9a-f]+ <[^>]+> f3870b5f vorr\.i16 q0, #65280 ; 0xff00
-0[0-9a-f]+ <[^>]+> f3870b1f vorr\.i16 d0, #65280 ; 0xff00
-0[0-9a-f]+ <[^>]+> f2800950 vorr\.i16 q0, #0 ; 0x0000
-0[0-9a-f]+ <[^>]+> f2800950 vorr\.i16 q0, #0 ; 0x0000
-0[0-9a-f]+ <[^>]+> f2800910 vorr\.i16 d0, #0 ; 0x0000
+0[0-9a-f]+ <[^>]+> f3820175 vbic\.i32 q0, #165 @ 0x000000a5
+0[0-9a-f]+ <[^>]+> f3820175 vbic\.i32 q0, #165 @ 0x000000a5
+0[0-9a-f]+ <[^>]+> f3820135 vbic\.i32 d0, #165 @ 0x000000a5
+0[0-9a-f]+ <[^>]+> f3820375 vbic\.i32 q0, #42240 @ 0x0000a500
+0[0-9a-f]+ <[^>]+> f3820375 vbic\.i32 q0, #42240 @ 0x0000a500
+0[0-9a-f]+ <[^>]+> f3820335 vbic\.i32 d0, #42240 @ 0x0000a500
+0[0-9a-f]+ <[^>]+> f3820575 vbic\.i32 q0, #10813440 @ 0x00a50000
+0[0-9a-f]+ <[^>]+> f3820575 vbic\.i32 q0, #10813440 @ 0x00a50000
+0[0-9a-f]+ <[^>]+> f3820535 vbic\.i32 d0, #10813440 @ 0x00a50000
+0[0-9a-f]+ <[^>]+> f3820775 vbic\.i32 q0, #-1526726656 @ 0xa5000000
+0[0-9a-f]+ <[^>]+> f3820775 vbic\.i32 q0, #-1526726656 @ 0xa5000000
+0[0-9a-f]+ <[^>]+> f3820735 vbic\.i32 d0, #-1526726656 @ 0xa5000000
+0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820935 vbic\.i16 d0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f3820b35 vbic\.i16 d0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387013f vbic\.i32 d0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387013f vbic\.i32 d0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387013f vbic\.i32 d0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387037f vbic\.i32 q0, #65280 @ 0x0000ff00
+0[0-9a-f]+ <[^>]+> f387037f vbic\.i32 q0, #65280 @ 0x0000ff00
+0[0-9a-f]+ <[^>]+> f387033f vbic\.i32 d0, #65280 @ 0x0000ff00
+0[0-9a-f]+ <[^>]+> f387057f vbic\.i32 q0, #16711680 @ 0x00ff0000
+0[0-9a-f]+ <[^>]+> f387057f vbic\.i32 q0, #16711680 @ 0x00ff0000
+0[0-9a-f]+ <[^>]+> f387053f vbic\.i32 d0, #16711680 @ 0x00ff0000
+0[0-9a-f]+ <[^>]+> f387077f vbic\.i32 q0, #-16777216 @ 0xff000000
+0[0-9a-f]+ <[^>]+> f387077f vbic\.i32 q0, #-16777216 @ 0xff000000
+0[0-9a-f]+ <[^>]+> f387073f vbic\.i32 d0, #-16777216 @ 0xff000000
+0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820935 vbic\.i16 d0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f3820b35 vbic\.i16 d0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f387097f vbic\.i16 q0, #255 @ 0x00ff
+0[0-9a-f]+ <[^>]+> f387097f vbic\.i16 q0, #255 @ 0x00ff
+0[0-9a-f]+ <[^>]+> f387093f vbic\.i16 d0, #255 @ 0x00ff
+0[0-9a-f]+ <[^>]+> f3870b7f vbic\.i16 q0, #65280 @ 0xff00
+0[0-9a-f]+ <[^>]+> f3870b7f vbic\.i16 q0, #65280 @ 0xff00
+0[0-9a-f]+ <[^>]+> f3870b3f vbic\.i16 d0, #65280 @ 0xff00
+0[0-9a-f]+ <[^>]+> f2800970 vbic\.i16 q0, #0 @ 0x0000
+0[0-9a-f]+ <[^>]+> f2800970 vbic\.i16 q0, #0 @ 0x0000
+0[0-9a-f]+ <[^>]+> f2800930 vbic\.i16 d0, #0 @ 0x0000
+0[0-9a-f]+ <[^>]+> f3820155 vorr\.i32 q0, #165 @ 0x000000a5
+0[0-9a-f]+ <[^>]+> f3820155 vorr\.i32 q0, #165 @ 0x000000a5
+0[0-9a-f]+ <[^>]+> f3820115 vorr\.i32 d0, #165 @ 0x000000a5
+0[0-9a-f]+ <[^>]+> f3820355 vorr\.i32 q0, #42240 @ 0x0000a500
+0[0-9a-f]+ <[^>]+> f3820355 vorr\.i32 q0, #42240 @ 0x0000a500
+0[0-9a-f]+ <[^>]+> f3820315 vorr\.i32 d0, #42240 @ 0x0000a500
+0[0-9a-f]+ <[^>]+> f3820555 vorr\.i32 q0, #10813440 @ 0x00a50000
+0[0-9a-f]+ <[^>]+> f3820555 vorr\.i32 q0, #10813440 @ 0x00a50000
+0[0-9a-f]+ <[^>]+> f3820515 vorr\.i32 d0, #10813440 @ 0x00a50000
+0[0-9a-f]+ <[^>]+> f3820755 vorr\.i32 q0, #-1526726656 @ 0xa5000000
+0[0-9a-f]+ <[^>]+> f3820755 vorr\.i32 q0, #-1526726656 @ 0xa5000000
+0[0-9a-f]+ <[^>]+> f3820715 vorr\.i32 d0, #-1526726656 @ 0xa5000000
+0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820915 vorr\.i16 d0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f3820b15 vorr\.i16 d0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387035f vorr\.i32 q0, #65280 @ 0x0000ff00
+0[0-9a-f]+ <[^>]+> f387035f vorr\.i32 q0, #65280 @ 0x0000ff00
+0[0-9a-f]+ <[^>]+> f387031f vorr\.i32 d0, #65280 @ 0x0000ff00
+0[0-9a-f]+ <[^>]+> f387055f vorr\.i32 q0, #16711680 @ 0x00ff0000
+0[0-9a-f]+ <[^>]+> f387055f vorr\.i32 q0, #16711680 @ 0x00ff0000
+0[0-9a-f]+ <[^>]+> f387051f vorr\.i32 d0, #16711680 @ 0x00ff0000
+0[0-9a-f]+ <[^>]+> f387075f vorr\.i32 q0, #-16777216 @ 0xff000000
+0[0-9a-f]+ <[^>]+> f387075f vorr\.i32 q0, #-16777216 @ 0xff000000
+0[0-9a-f]+ <[^>]+> f387071f vorr\.i32 d0, #-16777216 @ 0xff000000
+0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820915 vorr\.i16 d0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f3820b15 vorr\.i16 d0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f387095f vorr\.i16 q0, #255 @ 0x00ff
+0[0-9a-f]+ <[^>]+> f387095f vorr\.i16 q0, #255 @ 0x00ff
+0[0-9a-f]+ <[^>]+> f387091f vorr\.i16 d0, #255 @ 0x00ff
+0[0-9a-f]+ <[^>]+> f3870b5f vorr\.i16 q0, #65280 @ 0xff00
+0[0-9a-f]+ <[^>]+> f3870b5f vorr\.i16 q0, #65280 @ 0xff00
+0[0-9a-f]+ <[^>]+> f3870b1f vorr\.i16 d0, #65280 @ 0xff00
+0[0-9a-f]+ <[^>]+> f2800950 vorr\.i16 q0, #0 @ 0x0000
+0[0-9a-f]+ <[^>]+> f2800950 vorr\.i16 q0, #0 @ 0x0000
+0[0-9a-f]+ <[^>]+> f2800910 vorr\.i16 d0, #0 @ 0x0000
+0[0-9a-f]+ <[^>]+> f3820175 vbic\.i32 q0, #165 @ 0x000000a5
+0[0-9a-f]+ <[^>]+> f3820175 vbic\.i32 q0, #165 @ 0x000000a5
+0[0-9a-f]+ <[^>]+> f3820135 vbic\.i32 d0, #165 @ 0x000000a5
+0[0-9a-f]+ <[^>]+> f3820375 vbic\.i32 q0, #42240 @ 0x0000a500
+0[0-9a-f]+ <[^>]+> f3820375 vbic\.i32 q0, #42240 @ 0x0000a500
+0[0-9a-f]+ <[^>]+> f3820335 vbic\.i32 d0, #42240 @ 0x0000a500
+0[0-9a-f]+ <[^>]+> f3820575 vbic\.i32 q0, #10813440 @ 0x00a50000
+0[0-9a-f]+ <[^>]+> f3820575 vbic\.i32 q0, #10813440 @ 0x00a50000
+0[0-9a-f]+ <[^>]+> f3820535 vbic\.i32 d0, #10813440 @ 0x00a50000
+0[0-9a-f]+ <[^>]+> f3820775 vbic\.i32 q0, #-1526726656 @ 0xa5000000
+0[0-9a-f]+ <[^>]+> f3820775 vbic\.i32 q0, #-1526726656 @ 0xa5000000
+0[0-9a-f]+ <[^>]+> f3820735 vbic\.i32 d0, #-1526726656 @ 0xa5000000
+0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820935 vbic\.i16 d0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f3820b35 vbic\.i16 d0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387013f vbic\.i32 d0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387013f vbic\.i32 d0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387013f vbic\.i32 d0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387037f vbic\.i32 q0, #65280 @ 0x0000ff00
+0[0-9a-f]+ <[^>]+> f387037f vbic\.i32 q0, #65280 @ 0x0000ff00
+0[0-9a-f]+ <[^>]+> f387033f vbic\.i32 d0, #65280 @ 0x0000ff00
+0[0-9a-f]+ <[^>]+> f387057f vbic\.i32 q0, #16711680 @ 0x00ff0000
+0[0-9a-f]+ <[^>]+> f387057f vbic\.i32 q0, #16711680 @ 0x00ff0000
+0[0-9a-f]+ <[^>]+> f387053f vbic\.i32 d0, #16711680 @ 0x00ff0000
+0[0-9a-f]+ <[^>]+> f387077f vbic\.i32 q0, #-16777216 @ 0xff000000
+0[0-9a-f]+ <[^>]+> f387077f vbic\.i32 q0, #-16777216 @ 0xff000000
+0[0-9a-f]+ <[^>]+> f387073f vbic\.i32 d0, #-16777216 @ 0xff000000
+0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820935 vbic\.i16 d0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f3820b35 vbic\.i16 d0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f387097f vbic\.i16 q0, #255 @ 0x00ff
+0[0-9a-f]+ <[^>]+> f387097f vbic\.i16 q0, #255 @ 0x00ff
+0[0-9a-f]+ <[^>]+> f387093f vbic\.i16 d0, #255 @ 0x00ff
+0[0-9a-f]+ <[^>]+> f3870b7f vbic\.i16 q0, #65280 @ 0xff00
+0[0-9a-f]+ <[^>]+> f3870b7f vbic\.i16 q0, #65280 @ 0xff00
+0[0-9a-f]+ <[^>]+> f3870b3f vbic\.i16 d0, #65280 @ 0xff00
+0[0-9a-f]+ <[^>]+> f2800970 vbic\.i16 q0, #0 @ 0x0000
+0[0-9a-f]+ <[^>]+> f2800970 vbic\.i16 q0, #0 @ 0x0000
+0[0-9a-f]+ <[^>]+> f2800930 vbic\.i16 d0, #0 @ 0x0000
+0[0-9a-f]+ <[^>]+> f3820155 vorr\.i32 q0, #165 @ 0x000000a5
+0[0-9a-f]+ <[^>]+> f3820155 vorr\.i32 q0, #165 @ 0x000000a5
+0[0-9a-f]+ <[^>]+> f3820115 vorr\.i32 d0, #165 @ 0x000000a5
+0[0-9a-f]+ <[^>]+> f3820355 vorr\.i32 q0, #42240 @ 0x0000a500
+0[0-9a-f]+ <[^>]+> f3820355 vorr\.i32 q0, #42240 @ 0x0000a500
+0[0-9a-f]+ <[^>]+> f3820315 vorr\.i32 d0, #42240 @ 0x0000a500
+0[0-9a-f]+ <[^>]+> f3820555 vorr\.i32 q0, #10813440 @ 0x00a50000
+0[0-9a-f]+ <[^>]+> f3820555 vorr\.i32 q0, #10813440 @ 0x00a50000
+0[0-9a-f]+ <[^>]+> f3820515 vorr\.i32 d0, #10813440 @ 0x00a50000
+0[0-9a-f]+ <[^>]+> f3820755 vorr\.i32 q0, #-1526726656 @ 0xa5000000
+0[0-9a-f]+ <[^>]+> f3820755 vorr\.i32 q0, #-1526726656 @ 0xa5000000
+0[0-9a-f]+ <[^>]+> f3820715 vorr\.i32 d0, #-1526726656 @ 0xa5000000
+0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820915 vorr\.i16 d0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f3820b15 vorr\.i16 d0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 @ 0x000000ff
+0[0-9a-f]+ <[^>]+> f387035f vorr\.i32 q0, #65280 @ 0x0000ff00
+0[0-9a-f]+ <[^>]+> f387035f vorr\.i32 q0, #65280 @ 0x0000ff00
+0[0-9a-f]+ <[^>]+> f387031f vorr\.i32 d0, #65280 @ 0x0000ff00
+0[0-9a-f]+ <[^>]+> f387055f vorr\.i32 q0, #16711680 @ 0x00ff0000
+0[0-9a-f]+ <[^>]+> f387055f vorr\.i32 q0, #16711680 @ 0x00ff0000
+0[0-9a-f]+ <[^>]+> f387051f vorr\.i32 d0, #16711680 @ 0x00ff0000
+0[0-9a-f]+ <[^>]+> f387075f vorr\.i32 q0, #-16777216 @ 0xff000000
+0[0-9a-f]+ <[^>]+> f387075f vorr\.i32 q0, #-16777216 @ 0xff000000
+0[0-9a-f]+ <[^>]+> f387071f vorr\.i32 d0, #-16777216 @ 0xff000000
+0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820915 vorr\.i16 d0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f3820b15 vorr\.i16 d0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f387095f vorr\.i16 q0, #255 @ 0x00ff
+0[0-9a-f]+ <[^>]+> f387095f vorr\.i16 q0, #255 @ 0x00ff
+0[0-9a-f]+ <[^>]+> f387091f vorr\.i16 d0, #255 @ 0x00ff
+0[0-9a-f]+ <[^>]+> f3870b5f vorr\.i16 q0, #65280 @ 0xff00
+0[0-9a-f]+ <[^>]+> f3870b5f vorr\.i16 q0, #65280 @ 0xff00
+0[0-9a-f]+ <[^>]+> f3870b1f vorr\.i16 d0, #65280 @ 0xff00
+0[0-9a-f]+ <[^>]+> f2800950 vorr\.i16 q0, #0 @ 0x0000
+0[0-9a-f]+ <[^>]+> f2800950 vorr\.i16 q0, #0 @ 0x0000
+0[0-9a-f]+ <[^>]+> f2800910 vorr\.i16 d0, #0 @ 0x0000
0[0-9a-f]+ <[^>]+> f3100150 vbsl q0, q0, q0
0[0-9a-f]+ <[^>]+> f3100150 vbsl q0, q0, q0
0[0-9a-f]+ <[^>]+> f3100110 vbsl d0, d0, d0
0[0-9a-f]+ <[^>]+> ee900b30 vmov\.u16 r0, d0\[0\]
0[0-9a-f]+ <[^>]+> ee100b10 vmov\.32 r0, d0\[0\]
0[0-9a-f]+ <[^>]+> ec510b10 vmov r0, r1, d0
-0[0-9a-f]+ <[^>]+> f2870057 vmov\.i32 q0, #119 ; 0x00000077
-0[0-9a-f]+ <[^>]+> f2870017 vmov\.i32 d0, #119 ; 0x00000077
-0[0-9a-f]+ <[^>]+> f2870057 vmov\.i32 q0, #119 ; 0x00000077
-0[0-9a-f]+ <[^>]+> f2870017 vmov\.i32 d0, #119 ; 0x00000077
-0[0-9a-f]+ <[^>]+> f2870057 vmov\.i32 q0, #119 ; 0x00000077
-0[0-9a-f]+ <[^>]+> f2870017 vmov\.i32 d0, #119 ; 0x00000077
-0[0-9a-f]+ <[^>]+> f2870077 vmvn\.i32 q0, #119 ; 0x00000077
-0[0-9a-f]+ <[^>]+> f2870037 vmvn\.i32 d0, #119 ; 0x00000077
-0[0-9a-f]+ <[^>]+> f2870077 vmvn\.i32 q0, #119 ; 0x00000077
-0[0-9a-f]+ <[^>]+> f2870037 vmvn\.i32 d0, #119 ; 0x00000077
-0[0-9a-f]+ <[^>]+> f2870077 vmvn\.i32 q0, #119 ; 0x00000077
-0[0-9a-f]+ <[^>]+> f2870037 vmvn\.i32 d0, #119 ; 0x00000077
-0[0-9a-f]+ <[^>]+> f2870257 vmov\.i32 q0, #30464 ; 0x00007700
-0[0-9a-f]+ <[^>]+> f2870217 vmov\.i32 d0, #30464 ; 0x00007700
-0[0-9a-f]+ <[^>]+> f2870277 vmvn\.i32 q0, #30464 ; 0x00007700
-0[0-9a-f]+ <[^>]+> f2870237 vmvn\.i32 d0, #30464 ; 0x00007700
-0[0-9a-f]+ <[^>]+> f2870457 vmov\.i32 q0, #7798784 ; 0x00770000
-0[0-9a-f]+ <[^>]+> f2870417 vmov\.i32 d0, #7798784 ; 0x00770000
-0[0-9a-f]+ <[^>]+> f2870477 vmvn\.i32 q0, #7798784 ; 0x00770000
-0[0-9a-f]+ <[^>]+> f2870437 vmvn\.i32 d0, #7798784 ; 0x00770000
-0[0-9a-f]+ <[^>]+> f2870657 vmov\.i32 q0, #1996488704 ; 0x77000000
-0[0-9a-f]+ <[^>]+> f2870617 vmov\.i32 d0, #1996488704 ; 0x77000000
-0[0-9a-f]+ <[^>]+> f2870677 vmvn\.i32 q0, #1996488704 ; 0x77000000
-0[0-9a-f]+ <[^>]+> f2870637 vmvn\.i32 d0, #1996488704 ; 0x77000000
-0[0-9a-f]+ <[^>]+> f2870857 vmov\.i16 q0, #119 ; 0x0077
-0[0-9a-f]+ <[^>]+> f2870817 vmov\.i16 d0, #119 ; 0x0077
-0[0-9a-f]+ <[^>]+> f2870877 vmvn\.i16 q0, #119 ; 0x0077
-0[0-9a-f]+ <[^>]+> f2870837 vmvn\.i16 d0, #119 ; 0x0077
-0[0-9a-f]+ <[^>]+> f2870a57 vmov\.i16 q0, #30464 ; 0x7700
-0[0-9a-f]+ <[^>]+> f2870a17 vmov\.i16 d0, #30464 ; 0x7700
-0[0-9a-f]+ <[^>]+> f2870a77 vmvn\.i16 q0, #30464 ; 0x7700
-0[0-9a-f]+ <[^>]+> f2870a37 vmvn\.i16 d0, #30464 ; 0x7700
-0[0-9a-f]+ <[^>]+> f2870c57 vmov\.i32 q0, #30719 ; 0x000077ff
-0[0-9a-f]+ <[^>]+> f2870c17 vmov\.i32 d0, #30719 ; 0x000077ff
-0[0-9a-f]+ <[^>]+> f2870c77 vmvn\.i32 q0, #30719 ; 0x000077ff
-0[0-9a-f]+ <[^>]+> f2870c37 vmvn\.i32 d0, #30719 ; 0x000077ff
-0[0-9a-f]+ <[^>]+> f2870d57 vmov\.i32 q0, #7864319 ; 0x0077ffff
-0[0-9a-f]+ <[^>]+> f2870d17 vmov\.i32 d0, #7864319 ; 0x0077ffff
-0[0-9a-f]+ <[^>]+> f2870d77 vmvn\.i32 q0, #7864319 ; 0x0077ffff
-0[0-9a-f]+ <[^>]+> f2870d37 vmvn\.i32 d0, #7864319 ; 0x0077ffff
-0[0-9a-f]+ <[^>]+> f2870e57 vmov\.i8 q0, #119 ; 0x77
-0[0-9a-f]+ <[^>]+> f2870e17 vmov\.i8 d0, #119 ; 0x77
+0[0-9a-f]+ <[^>]+> f2870057 vmov\.i32 q0, #119 @ 0x00000077
+0[0-9a-f]+ <[^>]+> f2870017 vmov\.i32 d0, #119 @ 0x00000077
+0[0-9a-f]+ <[^>]+> f2870057 vmov\.i32 q0, #119 @ 0x00000077
+0[0-9a-f]+ <[^>]+> f2870017 vmov\.i32 d0, #119 @ 0x00000077
+0[0-9a-f]+ <[^>]+> f2870057 vmov\.i32 q0, #119 @ 0x00000077
+0[0-9a-f]+ <[^>]+> f2870017 vmov\.i32 d0, #119 @ 0x00000077
+0[0-9a-f]+ <[^>]+> f2870077 vmvn\.i32 q0, #119 @ 0x00000077
+0[0-9a-f]+ <[^>]+> f2870037 vmvn\.i32 d0, #119 @ 0x00000077
+0[0-9a-f]+ <[^>]+> f2870077 vmvn\.i32 q0, #119 @ 0x00000077
+0[0-9a-f]+ <[^>]+> f2870037 vmvn\.i32 d0, #119 @ 0x00000077
+0[0-9a-f]+ <[^>]+> f2870077 vmvn\.i32 q0, #119 @ 0x00000077
+0[0-9a-f]+ <[^>]+> f2870037 vmvn\.i32 d0, #119 @ 0x00000077
+0[0-9a-f]+ <[^>]+> f2870257 vmov\.i32 q0, #30464 @ 0x00007700
+0[0-9a-f]+ <[^>]+> f2870217 vmov\.i32 d0, #30464 @ 0x00007700
+0[0-9a-f]+ <[^>]+> f2870277 vmvn\.i32 q0, #30464 @ 0x00007700
+0[0-9a-f]+ <[^>]+> f2870237 vmvn\.i32 d0, #30464 @ 0x00007700
+0[0-9a-f]+ <[^>]+> f2870457 vmov\.i32 q0, #7798784 @ 0x00770000
+0[0-9a-f]+ <[^>]+> f2870417 vmov\.i32 d0, #7798784 @ 0x00770000
+0[0-9a-f]+ <[^>]+> f2870477 vmvn\.i32 q0, #7798784 @ 0x00770000
+0[0-9a-f]+ <[^>]+> f2870437 vmvn\.i32 d0, #7798784 @ 0x00770000
+0[0-9a-f]+ <[^>]+> f2870657 vmov\.i32 q0, #1996488704 @ 0x77000000
+0[0-9a-f]+ <[^>]+> f2870617 vmov\.i32 d0, #1996488704 @ 0x77000000
+0[0-9a-f]+ <[^>]+> f2870677 vmvn\.i32 q0, #1996488704 @ 0x77000000
+0[0-9a-f]+ <[^>]+> f2870637 vmvn\.i32 d0, #1996488704 @ 0x77000000
+0[0-9a-f]+ <[^>]+> f2870857 vmov\.i16 q0, #119 @ 0x0077
+0[0-9a-f]+ <[^>]+> f2870817 vmov\.i16 d0, #119 @ 0x0077
+0[0-9a-f]+ <[^>]+> f2870877 vmvn\.i16 q0, #119 @ 0x0077
+0[0-9a-f]+ <[^>]+> f2870837 vmvn\.i16 d0, #119 @ 0x0077
+0[0-9a-f]+ <[^>]+> f2870a57 vmov\.i16 q0, #30464 @ 0x7700
+0[0-9a-f]+ <[^>]+> f2870a17 vmov\.i16 d0, #30464 @ 0x7700
+0[0-9a-f]+ <[^>]+> f2870a77 vmvn\.i16 q0, #30464 @ 0x7700
+0[0-9a-f]+ <[^>]+> f2870a37 vmvn\.i16 d0, #30464 @ 0x7700
+0[0-9a-f]+ <[^>]+> f2870c57 vmov\.i32 q0, #30719 @ 0x000077ff
+0[0-9a-f]+ <[^>]+> f2870c17 vmov\.i32 d0, #30719 @ 0x000077ff
+0[0-9a-f]+ <[^>]+> f2870c77 vmvn\.i32 q0, #30719 @ 0x000077ff
+0[0-9a-f]+ <[^>]+> f2870c37 vmvn\.i32 d0, #30719 @ 0x000077ff
+0[0-9a-f]+ <[^>]+> f2870d57 vmov\.i32 q0, #7864319 @ 0x0077ffff
+0[0-9a-f]+ <[^>]+> f2870d17 vmov\.i32 d0, #7864319 @ 0x0077ffff
+0[0-9a-f]+ <[^>]+> f2870d77 vmvn\.i32 q0, #7864319 @ 0x0077ffff
+0[0-9a-f]+ <[^>]+> f2870d37 vmvn\.i32 d0, #7864319 @ 0x0077ffff
+0[0-9a-f]+ <[^>]+> f2870e57 vmov\.i8 q0, #119 @ 0x77
+0[0-9a-f]+ <[^>]+> f2870e17 vmov\.i8 d0, #119 @ 0x77
0[0-9a-f]+ <[^>]+> f3810e71 vmov\.i64 q0, #0xff0000ff000000ff
0[0-9a-f]+ <[^>]+> f3810e31 vmov\.i64 d0, #0xff0000ff000000ff
-0[0-9a-f]+ <[^>]+> f2810f51 vmov\.f32 q0, #4\.25 ; 0x40880000
-0[0-9a-f]+ <[^>]+> f2810f11 vmov\.f32 d0, #4\.25 ; 0x40880000
-0[0-9a-f]+ <[^>]+> f3820e55 vmov\.i8 q0, #165 ; 0xa5
-0[0-9a-f]+ <[^>]+> f3820e15 vmov\.i8 d0, #165 ; 0xa5
-0[0-9a-f]+ <[^>]+> f2850e5a vmov\.i8 q0, #90 ; 0x5a
-0[0-9a-f]+ <[^>]+> f2850e1a vmov\.i8 d0, #90 ; 0x5a
-0[0-9a-f]+ <[^>]+> f3820e55 vmov\.i8 q0, #165 ; 0xa5
-0[0-9a-f]+ <[^>]+> f3820e15 vmov\.i8 d0, #165 ; 0xa5
-0[0-9a-f]+ <[^>]+> f2850e5a vmov\.i8 q0, #90 ; 0x5a
-0[0-9a-f]+ <[^>]+> f2850e1a vmov\.i8 d0, #90 ; 0x5a
-0[0-9a-f]+ <[^>]+> f3820855 vmov\.i16 q0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820815 vmov\.i16 d0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820a55 vmov\.i16 q0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f3820a15 vmov\.i16 d0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f3820e55 vmov\.i8 q0, #165 ; 0xa5
-0[0-9a-f]+ <[^>]+> f3820e15 vmov\.i8 d0, #165 ; 0xa5
-0[0-9a-f]+ <[^>]+> f2850e5a vmov\.i8 q0, #90 ; 0x5a
-0[0-9a-f]+ <[^>]+> f2850e1a vmov\.i8 d0, #90 ; 0x5a
-0[0-9a-f]+ <[^>]+> f3820855 vmov\.i16 q0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820815 vmov\.i16 d0, #165 ; 0x00a5
-0[0-9a-f]+ <[^>]+> f3820a55 vmov\.i16 q0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f3820a15 vmov\.i16 d0, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f3820055 vmov\.i32 q0, #165 ; 0x000000a5
-0[0-9a-f]+ <[^>]+> f3820015 vmov\.i32 d0, #165 ; 0x000000a5
-0[0-9a-f]+ <[^>]+> f3820255 vmov\.i32 q0, #42240 ; 0x0000a500
-0[0-9a-f]+ <[^>]+> f3820215 vmov\.i32 d0, #42240 ; 0x0000a500
-0[0-9a-f]+ <[^>]+> f3820455 vmov\.i32 q0, #10813440 ; 0x00a50000
-0[0-9a-f]+ <[^>]+> f3820415 vmov\.i32 d0, #10813440 ; 0x00a50000
-0[0-9a-f]+ <[^>]+> f3820655 vmov\.i32 q0, #-1526726656 ; 0xa5000000
-0[0-9a-f]+ <[^>]+> f3820615 vmov\.i32 d0, #-1526726656 ; 0xa5000000
-0[0-9a-f]+ <[^>]+> f3820c55 vmov\.i32 q0, #42495 ; 0x0000a5ff
-0[0-9a-f]+ <[^>]+> f3820c15 vmov\.i32 d0, #42495 ; 0x0000a5ff
-0[0-9a-f]+ <[^>]+> f3820d55 vmov\.i32 q0, #10878975 ; 0x00a5ffff
-0[0-9a-f]+ <[^>]+> f3820d15 vmov\.i32 d0, #10878975 ; 0x00a5ffff
-0[0-9a-f]+ <[^>]+> f285067a vmvn\.i32 q0, #1509949440 ; 0x5a000000
-0[0-9a-f]+ <[^>]+> f285063a vmvn\.i32 d0, #1509949440 ; 0x5a000000
+0[0-9a-f]+ <[^>]+> f2810f51 vmov\.f32 q0, #4\.25 @ 0x40880000
+0[0-9a-f]+ <[^>]+> f2810f11 vmov\.f32 d0, #4\.25 @ 0x40880000
+0[0-9a-f]+ <[^>]+> f3820e55 vmov\.i8 q0, #165 @ 0xa5
+0[0-9a-f]+ <[^>]+> f3820e15 vmov\.i8 d0, #165 @ 0xa5
+0[0-9a-f]+ <[^>]+> f2850e5a vmov\.i8 q0, #90 @ 0x5a
+0[0-9a-f]+ <[^>]+> f2850e1a vmov\.i8 d0, #90 @ 0x5a
+0[0-9a-f]+ <[^>]+> f3820e55 vmov\.i8 q0, #165 @ 0xa5
+0[0-9a-f]+ <[^>]+> f3820e15 vmov\.i8 d0, #165 @ 0xa5
+0[0-9a-f]+ <[^>]+> f2850e5a vmov\.i8 q0, #90 @ 0x5a
+0[0-9a-f]+ <[^>]+> f2850e1a vmov\.i8 d0, #90 @ 0x5a
+0[0-9a-f]+ <[^>]+> f3820855 vmov\.i16 q0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820815 vmov\.i16 d0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820a55 vmov\.i16 q0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f3820a15 vmov\.i16 d0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f3820e55 vmov\.i8 q0, #165 @ 0xa5
+0[0-9a-f]+ <[^>]+> f3820e15 vmov\.i8 d0, #165 @ 0xa5
+0[0-9a-f]+ <[^>]+> f2850e5a vmov\.i8 q0, #90 @ 0x5a
+0[0-9a-f]+ <[^>]+> f2850e1a vmov\.i8 d0, #90 @ 0x5a
+0[0-9a-f]+ <[^>]+> f3820855 vmov\.i16 q0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820815 vmov\.i16 d0, #165 @ 0x00a5
+0[0-9a-f]+ <[^>]+> f3820a55 vmov\.i16 q0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f3820a15 vmov\.i16 d0, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f3820055 vmov\.i32 q0, #165 @ 0x000000a5
+0[0-9a-f]+ <[^>]+> f3820015 vmov\.i32 d0, #165 @ 0x000000a5
+0[0-9a-f]+ <[^>]+> f3820255 vmov\.i32 q0, #42240 @ 0x0000a500
+0[0-9a-f]+ <[^>]+> f3820215 vmov\.i32 d0, #42240 @ 0x0000a500
+0[0-9a-f]+ <[^>]+> f3820455 vmov\.i32 q0, #10813440 @ 0x00a50000
+0[0-9a-f]+ <[^>]+> f3820415 vmov\.i32 d0, #10813440 @ 0x00a50000
+0[0-9a-f]+ <[^>]+> f3820655 vmov\.i32 q0, #-1526726656 @ 0xa5000000
+0[0-9a-f]+ <[^>]+> f3820615 vmov\.i32 d0, #-1526726656 @ 0xa5000000
+0[0-9a-f]+ <[^>]+> f3820c55 vmov\.i32 q0, #42495 @ 0x0000a5ff
+0[0-9a-f]+ <[^>]+> f3820c15 vmov\.i32 d0, #42495 @ 0x0000a5ff
+0[0-9a-f]+ <[^>]+> f3820d55 vmov\.i32 q0, #10878975 @ 0x00a5ffff
+0[0-9a-f]+ <[^>]+> f3820d15 vmov\.i32 d0, #10878975 @ 0x00a5ffff
+0[0-9a-f]+ <[^>]+> f285067a vmvn\.i32 q0, #1509949440 @ 0x5a000000
+0[0-9a-f]+ <[^>]+> f285063a vmvn\.i32 d0, #1509949440 @ 0x5a000000
0[0-9a-f]+ <[^>]+> f3b005c0 vmvn q0, q0
0[0-9a-f]+ <[^>]+> f3b005c0 vmvn q0, q0
0[0-9a-f]+ <[^>]+> f3b00580 vmvn d0, d0
0[0-9a-f]+ <[^>]+> ed628b10 vstmdb r2!, {d24-d31}
0[0-9a-f]+ <[^>]+> ed223b20 vstmdb r2!, {d3-d18}
0[0-9a-f]+ <backward> 000001f4 .*
-0[0-9a-f]+ <[^>]+> eddf6b0b vldr d22, \[pc, #44\] ; 0[0-9a-f]+ <forward>
+0[0-9a-f]+ <[^>]+> eddf6b0b vldr d22, \[pc, #44\] @ 0[0-9a-f]+ <forward>
0[0-9a-f]+ <[^>]+> ed935b00 vldr d5, \[r3\]
0[0-9a-f]+ <[^>]+> ed135b01 vldr d5, \[r3, #-4\]
0[0-9a-f]+ <[^>]+> ed935b01 vldr d5, \[r3, #4\]
0[0-9a-f]+ <[^>]+> ed035b40 vstr d5, \[r3, #-256\].*
0[0-9a-f]+ <[^>]+> ed835b40 vstr d5, \[r3, #256\].*
0[0-9a-f]+ <forward> 000002bc .*
-0[0-9a-f]+ <[^>]+> ed1f7b11 vldr d7, \[pc, #-68\] ; 0[0-9a-f]+ <backward>
+0[0-9a-f]+ <[^>]+> ed1f7b11 vldr d7, \[pc, #-68\] @ 0[0-9a-f]+ <backward>
Disassembly of section \.text:
-00000000 <.text> f387015f vorr.i32 q0, #255 ; 0x000000ff
-00000004 <.text\+0x4> f387015f vorr.i32 q0, #255 ; 0x000000ff
+00000000 <.text> f387015f vorr.i32 q0, #255 @ 0x000000ff
+00000004 <.text\+0x4> f387015f vorr.i32 q0, #255 @ 0x000000ff
00000008 <.text\+0x8> f2220154 vorr q0, q1, q2
0000000c <.text\+0xc> f2200152 vorr q0, q0, q1
-00000010 <.text\+0x10> f387011f vorr.i32 d0, #255 ; 0x000000ff
-00000014 <.text\+0x14> f387011f vorr.i32 d0, #255 ; 0x000000ff
+00000010 <.text\+0x10> f387011f vorr.i32 d0, #255 @ 0x000000ff
+00000014 <.text\+0x14> f387011f vorr.i32 d0, #255 @ 0x000000ff
00000018 <.text\+0x18> f2210112 vorr d0, d1, d2
0000001c <.text\+0x1c> f2200111 vorr d0, d0, d1
Disassembly of section \.text:
0+000 <[^>]*> 0320f000 ? nopeq \{0\}
0+004 <[^>]*> 7320f000 ? nopvc \{0\}
-0+008 <[^>]*> 7320d700 ? nopvc \{0\} ; <UNPREDICTABLE>
+0+008 <[^>]*> 7320d700 ? nopvc \{0\} @ <UNPREDICTABLE>
.*: +file format .*arm.*
Disassembly of section .text:
-0+00 <[^>]+> e51f0000 ? ldr r0, \[pc, #-0\] ; 0+8 <[^>]+>
-0+04 <[^>]+> e59f0000 ? ldr r0, \[pc\] ; 0+c <[^>]+>
+0+00 <[^>]+> e51f0000 ? ldr r0, \[pc, #-0\] @ 0+8 <[^>]+>
+0+04 <[^>]+> e59f0000 ? ldr r0, \[pc\] @ 0+c <[^>]+>
0+08 <[^>]+> e5110000 ? ldr r0, \[r1, #-0\]
0+0c <[^>]+> e5910000 ? ldr r0, \[r1\]
0+10 <[^>]+> e4110000 ? ldr r0, \[r1\], #-0
0+14 <[^>]+> e4910000 ? ldr r0, \[r1\], #0
-0+18 <[^>]+> e15f00b0 ? ldrh r0, \[pc, #-0\] ; 0+20 <[^>]+>
-0+1c <[^>]+> e1df00b0 ? ldrh r0, \[pc\] ; 0+24 <[^>]+>
+0+18 <[^>]+> e15f00b0 ? ldrh r0, \[pc, #-0\] @ 0+20 <[^>]+>
+0+1c <[^>]+> e1df00b0 ? ldrh r0, \[pc\] @ 0+24 <[^>]+>
0+20 <[^>]+> e15100b0 ? ldrh r0, \[r1, #-0\]
0+24 <[^>]+> e1d100b0 ? ldrh r0, \[r1\]
0+28 <[^>]+> e05100b0 ? ldrh r0, \[r1\], #-0
.*: +file format .*arm.*
Disassembly of section .text:
-0+0 <[^>]+> e51f0004 ? ldr r0, \[pc, #-4\] ; 0+4 <[^>]+>
-0+4 <[^>]+> e1a00000 ? nop ; \(mov r0, r0\)
-0+8 <[^>]+> e1a00000 ? nop ; \(mov r0, r0\)
-0+c <[^>]+> e1a00000 ? nop ; \(mov r0, r0\)
+0+0 <[^>]+> e51f0004 ? ldr r0, \[pc, #-4\] @ 0+4 <[^>]+>
+0+4 <[^>]+> e1a00000 ? nop @ \(mov r0, r0\)
+0+8 <[^>]+> e1a00000 ? nop @ \(mov r0, r0\)
+0+c <[^>]+> e1a00000 ? nop @ \(mov r0, r0\)
Disassembly of section .text:
0+00000 <.*> 4770[ ]+bx[ ]+lr
-0+00002 <.*> 46c0[ ]+nop[ ]+; \(mov r8, r8\)
+0+00002 <.*> 46c0[ ]+nop[ ]+@ \(mov r8, r8\)
0+00004 <.*> e12fff1e[ ]+bx[ ]+lr
0+00008 <.*> f2af 000b[ ]+subw[ ]+r0, pc, #11
0+0000c <.*> 4780[ ]+blx[ ]+r0
0+0000e <.*> f2af 020c[ ]+subw[ ]+r2, pc, #12
0+00012 <.*> 4790[ ]+blx[ ]+r2
0+00014 <.*> e24f401b[ ]+sub[ ]+r4, pc, #27
-0+00018 <.*> e1a00000[ ]+nop[ ]+; \(mov r0, r0\)
+0+00018 <.*> e1a00000[ ]+nop[ ]+@ \(mov r0, r0\)
0+0001c <.*> e12fff34[ ]+blx[ ]+r4
-0+00020 <.*> e24f6024[ ]+sub[ ]+r6, pc, #36[ ]+; 0x24
-0+00024 <.*> e1a00000[ ]+nop[ ]+; \(mov r0, r0\)
+0+00020 <.*> e24f6024[ ]+sub[ ]+r6, pc, #36[ ]+@ 0x24
+0+00024 <.*> e1a00000[ ]+nop[ ]+@ \(mov r0, r0\)
0+00028 <.*> e12fff36[ ]+blx[ ]+r6
-0+0002c <.*> e24f8033[ ]+sub[ ]+r8, pc, #51[ ]+; 0x33
+0+0002c <.*> e24f8033[ ]+sub[ ]+r8, pc, #51[ ]+@ 0x33
0+00030 <.*> e12fff38[ ]+blx[ ]+r8
-0+00034 <.*> e24fa038[ ]+sub[ ]+sl, pc, #56[ ]+; 0x38
+0+00034 <.*> e24fa038[ ]+sub[ ]+sl, pc, #56[ ]+@ 0x38
0+00038 <.*> e12fff3a[ ]+blx[ ]+sl
-0+0003c <.*> 324fc043[ ]+subcc[ ]+ip, pc, #67[ ]+; 0x43
+0+0003c <.*> 324fc043[ ]+subcc[ ]+ip, pc, #67[ ]+@ 0x43
Disassembly of section \.text:
0+000 <foo>:
- 0: 46c0 nop ; .*
+ 0: 46c0 nop @ .*
2: f7ff fffe bl 0 <log_func>
6: e002 b\.n e <func\+0x2>
8: f7ff fffe bl c <func>
0+000c <func>:
- c: 46c0 nop ; .*
- e: 46c0 nop ; .*
+ c: 46c0 nop @ .*
+ e: 46c0 nop @ .*
Disassembly of section .text:
00000000 <f1>:
- 0: 46c0 nop ; \(mov r8, r8\)
- 2: 46c0 nop ; \(mov r8, r8\)
+ 0: 46c0 nop @ \(mov r8, r8\)
+ 2: 46c0 nop @ \(mov r8, r8\)
00000004 <f2>:
4: f2af 0107 subw r1, pc, #7
8: f20f 0305 addw r3, pc, #5
- c: a401 add r4, pc, #4 ; \(adr r4, 14 <f4>\)
- e: 46c0 nop ; \(mov r8, r8\)
+ c: a401 add r4, pc, #4 @ \(adr r4, 14 <f4>\)
+ e: 46c0 nop @ \(mov r8, r8\)
00000010 <f3>:
- 10: 46c0 nop ; \(mov r8, r8\)
- 12: 46c0 nop ; \(mov r8, r8\)
+ 10: 46c0 nop @ \(mov r8, r8\)
+ 12: 46c0 nop @ \(mov r8, r8\)
00000014 <f4>:
- 14: e1a00000 nop ; \(mov r0, r0\)
+ 14: e1a00000 nop @ \(mov r0, r0\)
.*: +file format .*arm.*
Disassembly of section .text:
-0+000 <.*> e52d0004 push {r0} ; \(str r0, \[sp, #-4\]!\)
+0+000 <.*> e52d0004 push {r0} @ \(str r0, \[sp, #-4\]!\)
0+004 <.*> e92d000e push {r1, r2, r3}
-0+008 <.*> e52d9004 push {r9} ; \(str r9, \[sp, #-4\]!\)
-0+00c <.*> e49d9004 pop {r9} ; \(ldr r9, \[sp\], #4\)
+0+008 <.*> e52d9004 push {r9} @ \(str r9, \[sp, #-4\]!\)
+0+00c <.*> e49d9004 pop {r9} @ \(ldr r9, \[sp\], #4\)
0+010 <.*> e8bd000e pop {r1, r2, r3}
-0+014 <.*> e49d0004 pop {r0} ; \(ldr r0, \[sp\], #4\)
+0+014 <.*> e49d0004 pop {r0} @ \(ldr r0, \[sp\], #4\)
Disassembly of section .text:
0+0 <.*> ee060f10 mcr 15, 0, r0, cr6, cr0, \{0\}
-0+4 <.*> e1a00000 nop ; \(mov r0, r0\)
-0+8 <.*> e1a00000 nop ; \(mov r0, r0\)
-0+c <.*> e1a00000 nop ; \(mov r0, r0\)
+0+4 <.*> e1a00000 nop @ \(mov r0, r0\)
+0+8 <.*> e1a00000 nop @ \(mov r0, r0\)
+0+c <.*> e1a00000 nop @ \(mov r0, r0\)
.*: +file format .*arm.*
Disassembly of section .text:
-0+000 <[^>]+> 46c0 nop ; \(mov r8, r8\)
+0+000 <[^>]+> 46c0 nop @ \(mov r8, r8\)
0+002 <[^>]+> f000 8080 beq.w 0+106 <[^>]*>
-0+006 <[^>]+> 46c0 nop ; \(mov r8, r8\)
+0+006 <[^>]+> 46c0 nop @ \(mov r8, r8\)
#...
-0+100 <[^>]+> 46c0 nop ; \(mov r8, r8\)
+0+100 <[^>]+> 46c0 nop @ \(mov r8, r8\)
0+102 <[^>]+> f47f af80 bne.w 0+006 <[^>]*>
-0+106 <[^>]+> 46c0 nop ; \(mov r8, r8\)
+0+106 <[^>]+> 46c0 nop @ \(mov r8, r8\)
.*: +file format .*arm.*
Disassembly of section .text:
-0+000 <[^>]+> f510 707a adds.w r0, r0, #1000 ; 0x3e8
-0+004 <[^>]+> 4800 ldr r0, \[pc, #0\] ; \(0+008 <[^>]+>\)
-0+006 <[^>]+> 4800 ldr r0, \[pc, #0\] ; \(0+008 <[^>]+>\)
+0+000 <[^>]+> f510 707a adds.w r0, r0, #1000 @ 0x3e8
+0+004 <[^>]+> 4800 ldr r0, \[pc, #0\] @ \(0+008 <[^>]+>\)
+0+006 <[^>]+> 4800 ldr r0, \[pc, #0\] @ \(0+008 <[^>]+>\)
00000016 <foo\+0x16> ebad 0d00 sub.w sp, sp, r0
0000001a <foo\+0x1a> ebad 0d40 sub.w sp, sp, r0, lsl #1
0000001e <foo\+0x1e> 9800 ldr r0, \[sp, #0\]
-00000020 <foo\+0x20> 4800 ldr r0, \[pc, #0\] ; \(00000024 <foo\+0x24>\)
+00000020 <foo\+0x20> 4800 ldr r0, \[pc, #0\] @ \(00000024 <foo\+0x24>\)
00000022 <foo\+0x22> f8d0 f000 ldr.w pc, \[r0\]
00000026 <foo\+0x26> f8d0 d000 ldr.w sp, \[r0\]
-0000002a <foo\+0x2a> f8df f000 ldr.w pc, \[pc\] ; 0000002c <foo\+0x2c>
+0000002a <foo\+0x2a> f8df f000 ldr.w pc, \[pc\] @ 0000002c <foo\+0x2c>
0000002e <foo\+0x2e> f8dd d000 ldr.w sp, \[sp\]
00000032 <foo\+0x32> f8dd f000 ldr.w pc, \[sp\]
-00000036 <foo\+0x36> f8df d000 ldr.w sp, \[pc\] ; 00000038 <foo\+0x38>
+00000036 <foo\+0x36> f8df d000 ldr.w sp, \[pc\] @ 00000038 <foo\+0x38>
0000003a <foo\+0x3a> 9000 str r0, \[sp, #0\]
0000003c <foo\+0x3c> f8c0 d000 str.w sp, \[r0\]
00000040 <foo\+0x40> f8cd d000 str.w sp, \[sp\]
000000d4 <foo\+0xd4> ebbd 0040 subs.w r0, sp, r0, lsl #1
000000d8 <foo\+0xd8> ebad 0d40 sub.w sp, sp, r0, lsl #1
000000dc <foo\+0xdc> ebbd 0d40 subs.w sp, sp, r0, lsl #1
-000000e0 <foo\+0xe0> a001 add r0, pc, #4 ; \(adr r0, 000000e8 <foo\+0xe8>\)
+000000e0 <foo\+0xe0> a001 add r0, pc, #4 @ \(adr r0, 000000e8 <foo\+0xe8>\)
000000e2 <foo\+0xe2> f2af 0004 subw r0, pc, #4
000000e6 <foo\+0xe6> f20f 0004 addw r0, pc, #4
000000ea <foo\+0xea> f2af 0004 subw r0, pc, #4
0+90 <[^>]*> e1800001 ? orr r0, r0, r1
0+94 <[^>]*> e1c00001 ? bic r0, r0, r1
0+98 <[^>]*> e0000091 ? mul r0, r1, r0
-0+9c <[^>]*> e1a00000 ? nop ; \(mov r0, r0\)
+0+9c <[^>]*> e1a00000 ? nop @ \(mov r0, r0\)
0+a0 <[^>]*> e1a00069 ? rrx r0, r9
0+a4 <[^>]*> e1b09060 ? rrxs r9, r0
-0+a8 <[^>]*> e1a00000 ? nop ; \(mov r0, r0\)
-0+ac <[^>]*> e1a00000 ? nop ; \(mov r0, r0\)
+0+a8 <[^>]*> e1a00000 ? nop @ \(mov r0, r0\)
+0+ac <[^>]*> e1a00000 ? nop @ \(mov r0, r0\)
0+12 <[^>]*> 4308 * orrs r0, r1
0+14 <[^>]*> 4388 * bics r0, r1
0+16 <[^>]*> 4188 * sbcs r0, r1
-0+18 <[^>]*> 46c0 * nop ; \(mov r8, r8\)
-0+1a <[^>]*> 46c0 * nop ; \(mov r8, r8\)
-0+1c <[^>]*> 46c0 * nop ; \(mov r8, r8\)
-0+1e <[^>]*> 46c0 * nop ; \(mov r8, r8\)
+0+18 <[^>]*> 46c0 * nop @ \(mov r8, r8\)
+0+1a <[^>]*> 46c0 * nop @ \(mov r8, r8\)
+0+1c <[^>]*> 46c0 * nop @ \(mov r8, r8\)
+0+1e <[^>]*> 46c0 * nop @ \(mov r8, r8\)
0+04a <[^>]+> 45f4 cmp ip, lr
0+04c <[^>]+> 4648 mov r0, r9
0+04e <[^>]+> 46a1 mov r9, r4
-0+050 <[^>]+> 46c0 nop ; \(mov r8, r8\)
+0+050 <[^>]+> 46c0 nop @ \(mov r8, r8\)
0+052 <[^>]+> 4738 bx r7
0+054 <[^>]+> 4740 bx r8
-0+056 <[^>]+> 46c0 nop ; \(mov r8, r8\)
+0+056 <[^>]+> 46c0 nop @ \(mov r8, r8\)
0+058 <[^>]+> 4778 bx pc
-0+05a <[^>]+> 4b20 ldr r3, \[pc, #128\] ; \(0+0dc <[^>]+>\)
-0+05c <[^>]+> 4c02 ldr r4, \[pc, #8\] ; \(0+068 <[^>]+>\)
+0+05a <[^>]+> 4b20 ldr r3, \[pc, #128\] @ \(0+0dc <[^>]+>\)
+0+05c <[^>]+> 4c02 ldr r4, \[pc, #8\] @ \(0+068 <[^>]+>\)
0+05e <[^>]+> 5088 str r0, \[r1, r2\]
0+060 <[^>]+> 5511 strb r1, \[r2, r4\]
0+062 <[^>]+> 59f5 ldr r5, \[r6, r7\]
0+064 <[^>]+> 5d62 ldrb r2, \[r4, r5\]
-0+066 <[^>]+> 46c0 nop ; \(mov r8, r8\)
+0+066 <[^>]+> 46c0 nop @ \(mov r8, r8\)
0+068 <[^>]+> 52d1 strh r1, \[r2, r3\]
0+06a <[^>]+> 5a23 ldrh r3, \[r4, r0\]
0+06c <[^>]+> 57f1 ldrsb r1, \[r6, r7\]
0+082 <[^>]+> 93ff str r3, \[sp, #1020\].*
0+084 <[^>]+> 990b ldr r1, \[sp, #44\].*
0+086 <[^>]+> 9a00 ldr r2, \[sp, #0\]
-0+088 <[^>]+> a7ff add r7, pc, #1020 ; \(adr r7, 0+488 <[^>]+>\)
+0+088 <[^>]+> a7ff add r7, pc, #1020 @ \(adr r7, 0+488 <[^>]+>\)
0+08a <[^>]+> ac80 add r4, sp, #512.*
0+08c <[^>]+> b043 add sp, #268.*
0+08e <[^>]+> b09a sub sp, #104.*
0+0ca <[^>]+> b07f add sp, #508.*
0+0cc <[^>]+> b0ff sub sp, #508.*
0+0ce <[^>]+> a8ff add r0, sp, #1020.*
-0+0d0 <[^>]+> a0ff add r0, pc, #1020 ; \(adr r0, 0+4d0 <[^>]+>\)
+0+0d0 <[^>]+> a0ff add r0, pc, #1020 @ \(adr r0, 0+4d0 <[^>]+>\)
0+0d2 <[^>]+> b01a add sp, #104.*
0+0d4 <[^>]+> b09a sub sp, #104.*
0+0d6 <[^>]+> a81a add r0, sp, #104.*
-0+0d8 <[^>]+> a01a add r0, pc, #104 ; \(adr r0, 0+144 <[^>]+>\)
+0+0d8 <[^>]+> a01a add r0, pc, #104 @ \(adr r0, 0+144 <[^>]+>\)
0+0da <[^>]+> 3168 adds r1, #104.*
0+0dc <[^>]+> 2668 movs r6, #104.*
0+0de <[^>]+> 2f68 cmp r7, #104.*
-0+0e0 <[^>]+> 46c0 nop ; \(mov r8, r8\)
-0+0e2 <[^>]+> 46c0 nop ; \(mov r8, r8\)
+0+0e0 <[^>]+> 46c0 nop @ \(mov r8, r8\)
+0+0e2 <[^>]+> 46c0 nop @ \(mov r8, r8\)
0+0e4 <[^>]+> eafffffe b 0+0e4 <[^>]+>
0+0e8 <[^>]+> ea000011 b 0+134 <[^>]+>
0+0ec <[^>]+> ebfffffc bl 0+0e4 <[^>]+>
0+0f4 <[^>]+> e12fff10 bx r0
.*: R_ARM_V4BX.*
0+0f8 <[^>]+> ef123456 (swi|svc) 0x00123456
-0+0fc <[^>]+> a004 add r0, pc, #16 ; \(adr r0, 0+110 <[^>]+>\)
+0+0fc <[^>]+> a004 add r0, pc, #16 @ \(adr r0, 0+110 <[^>]+>\)
0+0fe <[^>]+> e77f b.n 0+000 <[^>]+>
0+100 <[^>]+> e018 b.n 0+134 <[^>]+>
0+102 <[^>]+> f7ff ff7d bl 0+000 <[^>]+>
0+106 <[^>]+> f000 f815 bl 0+134 <[^>]+>
0+10a <[^>]+> 4700 bx r0
0+10c <[^>]+> dfff (swi|svc) 255.*
-0+10e <[^>]+> 46c0 nop ; \(mov r8, r8\)
+0+10e <[^>]+> 46c0 nop @ \(mov r8, r8\)
0+110 <[^>]+> d010 beq.n 0+134 <[^>]+>
0+112 <[^>]+> d10f bne.n 0+134 <[^>]+>
0+114 <[^>]+> d20e bcs.n 0+134 <[^>]+>
0+134 <[^>]+> f000 fc00 bl 0+938 <[^>]+>
\.\.\.
0+938 <[^>]+> f7ff fbfc bl 0+134 <[^>]+>
-0+93c <[^>]+> 4801 ldr r0, \[pc, #4\] ; \(0+944 <[^>]+>\)
-0+93e <[^>]+> 4801 ldr r0, \[pc, #4\] ; \(0+944 <[^>]+>\)
-0+940 <[^>]+> 4801 ldr r0, \[pc, #4\] ; \(0+948 <[^>]+>\)
-0+942 <[^>]+> 4801 ldr r0, \[pc, #4\] ; \(0+948 <[^>]+>\)
+0+93c <[^>]+> 4801 ldr r0, \[pc, #4\] @ \(0+944 <[^>]+>\)
+0+93e <[^>]+> 4801 ldr r0, \[pc, #4\] @ \(0+944 <[^>]+>\)
+0+940 <[^>]+> 4801 ldr r0, \[pc, #4\] @ \(0+948 <[^>]+>\)
+0+942 <[^>]+> 4801 ldr r0, \[pc, #4\] @ \(0+948 <[^>]+>\)
0+944 <[^>]+> 1c08 adds r0, r1, #0
-0+946 <[^>]+> 46c0 nop ; \(mov r8, r8\)
-0+948 <[^>]+> a001 add r0, pc, #4 ; \(adr r0, 00000950 <[^>]+>\)
-0+94a <[^>]+> a001 add r0, pc, #4 ; \(adr r0, 00000950 <[^>]+>\)
-0+94c <[^>]+> a000 add r0, pc, #0 ; \(adr r0, 00000950 <[^>]+>\)
-0+94e <[^>]+> 46c0 nop ; \(mov r8, r8\)
+0+946 <[^>]+> 46c0 nop @ \(mov r8, r8\)
+0+948 <[^>]+> a001 add r0, pc, #4 @ \(adr r0, 00000950 <[^>]+>\)
+0+94a <[^>]+> a001 add r0, pc, #4 @ \(adr r0, 00000950 <[^>]+>\)
+0+94c <[^>]+> a000 add r0, pc, #0 @ \(adr r0, 00000950 <[^>]+>\)
+0+94e <[^>]+> 46c0 nop @ \(mov r8, r8\)
#pass
.*: +file format .*arm.*
Disassembly of section \.text:
-0+000 <[^>]+> 46c0 nop ; \(mov r8, r8\)
-0+002 <[^>]+> 46c0 nop ; \(mov r8, r8\)
+0+000 <[^>]+> 46c0 nop @ \(mov r8, r8\)
+0+002 <[^>]+> 46c0 nop @ \(mov r8, r8\)
0+04a <[^>]+> 45f4 cmp ip, lr
0+04c <[^>]+> 4648 mov r0, r9
0+04e <[^>]+> 46a1 mov r9, r4
-0+050 <[^>]+> 46c0 nop ; \(mov r8, r8\)
+0+050 <[^>]+> 46c0 nop @ \(mov r8, r8\)
0+052 <[^>]+> 4738 bx r7
0+054 <[^>]+> 4740 bx r8
-0+056 <[^>]+> 46c0 nop ; \(mov r8, r8\)
+0+056 <[^>]+> 46c0 nop @ \(mov r8, r8\)
0+058 <[^>]+> 4778 bx pc
-0+05a <[^>]+> 4b20 ldr r3, \[pc, #128\] ; \(0+0dc <[^>]+>\)
-0+05c <[^>]+> 4c02 ldr r4, \[pc, #8\] ; \(0+068 <[^>]+>\)
+0+05a <[^>]+> 4b20 ldr r3, \[pc, #128\] @ \(0+0dc <[^>]+>\)
+0+05c <[^>]+> 4c02 ldr r4, \[pc, #8\] @ \(0+068 <[^>]+>\)
0+05e <[^>]+> 5088 str r0, \[r1, r2\]
0+060 <[^>]+> 5511 strb r1, \[r2, r4\]
0+062 <[^>]+> 59f5 ldr r5, \[r6, r7\]
0+064 <[^>]+> 5d62 ldrb r2, \[r4, r5\]
-0+066 <[^>]+> 46c0 nop ; \(mov r8, r8\)
+0+066 <[^>]+> 46c0 nop @ \(mov r8, r8\)
0+068 <[^>]+> 52d1 strh r1, \[r2, r3\]
0+06a <[^>]+> 5a23 ldrh r3, \[r4, r0\]
0+06c <[^>]+> 57f1 ldrsb r1, \[r6, r7\]
0+082 <[^>]+> 93ff str r3, \[sp, #1020\].*
0+084 <[^>]+> 990b ldr r1, \[sp, #44\].*
0+086 <[^>]+> 9a00 ldr r2, \[sp, #0\]
-0+088 <[^>]+> a7ff add r7, pc, #1020 ; \(adr r7, 0+488 <[^>]+>\)
+0+088 <[^>]+> a7ff add r7, pc, #1020 @ \(adr r7, 0+488 <[^>]+>\)
0+08a <[^>]+> ac80 add r4, sp, #512.*
0+08c <[^>]+> b043 add sp, #268.*
0+08e <[^>]+> b09a sub sp, #104.*
0+0ca <[^>]+> b07f add sp, #508.*
0+0cc <[^>]+> b0ff sub sp, #508.*
0+0ce <[^>]+> a8ff add r0, sp, #1020.*
-0+0d0 <[^>]+> a0ff add r0, pc, #1020 ; \(adr r0, 0+4d0 <[^>]+>\)
+0+0d0 <[^>]+> a0ff add r0, pc, #1020 @ \(adr r0, 0+4d0 <[^>]+>\)
0+0d2 <[^>]+> b01a add sp, #104.*
0+0d4 <[^>]+> b09a sub sp, #104.*
0+0d6 <[^>]+> a81a add r0, sp, #104.*
-0+0d8 <[^>]+> a01a add r0, pc, #104 ; \(adr r0, 0+144 <[^>]+>\)
+0+0d8 <[^>]+> a01a add r0, pc, #104 @ \(adr r0, 0+144 <[^>]+>\)
0+0da <[^>]+> 3168 adds r1, #104.*
0+0dc <[^>]+> 2668 movs r6, #104.*
0+0de <[^>]+> 2f68 cmp r7, #104.*
-0+0e0 <[^>]+> 46c0 nop ; \(mov r8, r8\)
-0+0e2 <[^>]+> 46c0 nop ; \(mov r8, r8\)
+0+0e0 <[^>]+> 46c0 nop @ \(mov r8, r8\)
+0+0e2 <[^>]+> 46c0 nop @ \(mov r8, r8\)
0+0e4 <[^>]+> eafffffe b 0+0e4 <[^>]+>
0+0e8 <[^>]+> ea000011 b 0+134 <[^>]+>
0+0ec <[^>]+> ebfffffc bl 0+0e4 <[^>]+>
0+0f0 <[^>]+> eb00000f bl 0+134 <[^>]+>
0+0f4 <[^>]+> e12fff10 bx r0
0+0f8 <[^>]+> ef123456 (swi|svc) 0x00123456
-0+0fc <[^>]+> a004 add r0, pc, #16 ; \(adr r0, 0+110 <[^>]+>\)
+0+0fc <[^>]+> a004 add r0, pc, #16 @ \(adr r0, 0+110 <[^>]+>\)
0+0fe <[^>]+> e77f b.n 0+000 <[^>]+>
0+100 <[^>]+> e018 b.n 0+134 <[^>]+>
0+102 <[^>]+> f7ff ff7d bl 0+000 <[^>]+>
0+106 <[^>]+> f000 f815 bl 0+134 <[^>]+>
0+10a <[^>]+> 4700 bx r0
0+10c <[^>]+> dfff (swi|svc) 255.*
-0+10e <[^>]+> 46c0 nop ; \(mov r8, r8\)
+0+10e <[^>]+> 46c0 nop @ \(mov r8, r8\)
0+110 <[^>]+> d010 beq.n 0+134 <[^>]+>
0+112 <[^>]+> d10f bne.n 0+134 <[^>]+>
0+114 <[^>]+> d20e bcs.n 0+134 <[^>]+>
0+134 <[^>]+> f000 fc00 bl 0+938 <[^>]+>
\.\.\.
0+938 <[^>]+> f7ff fbfc bl 0+134 <[^>]+>
-0+93c <[^>]+> 4801 ldr r0, \[pc, #4\] ; \(0+944 <[^>]+>\)
-0+93e <[^>]+> 4801 ldr r0, \[pc, #4\] ; \(0+944 <[^>]+>\)
-0+940 <[^>]+> 4801 ldr r0, \[pc, #4\] ; \(0+948 <[^>]+>\)
-0+942 <[^>]+> 4801 ldr r0, \[pc, #4\] ; \(0+948 <[^>]+>\)
+0+93c <[^>]+> 4801 ldr r0, \[pc, #4\] @ \(0+944 <[^>]+>\)
+0+93e <[^>]+> 4801 ldr r0, \[pc, #4\] @ \(0+944 <[^>]+>\)
+0+940 <[^>]+> 4801 ldr r0, \[pc, #4\] @ \(0+948 <[^>]+>\)
+0+942 <[^>]+> 4801 ldr r0, \[pc, #4\] @ \(0+948 <[^>]+>\)
0+944 <[^>]+> 1c08 adds r0, r1, #0
-0+946 <[^>]+> 46c0 nop ; \(mov r8, r8\)
-0+948 <[^>]+> a001 add r0, pc, #4 ; \(adr r0, 00000950 <[^>]+>\)
-0+94a <[^>]+> a001 add r0, pc, #4 ; \(adr r0, 00000950 <[^>]+>\)
-0+94c <[^>]+> a000 add r0, pc, #0 ; \(adr r0, 00000950 <[^>]+>\)
-0+94e <[^>]+> 46c0 nop ; \(mov r8, r8\)
+0+946 <[^>]+> 46c0 nop @ \(mov r8, r8\)
+0+948 <[^>]+> a001 add r0, pc, #4 @ \(adr r0, 00000950 <[^>]+>\)
+0+94a <[^>]+> a001 add r0, pc, #4 @ \(adr r0, 00000950 <[^>]+>\)
+0+94c <[^>]+> a000 add r0, pc, #0 @ \(adr r0, 00000950 <[^>]+>\)
+0+94e <[^>]+> 46c0 nop @ \(mov r8, r8\)
#pass
0[0-9a-f]+ <[^>]+> 3364 adds r3, #100.*
0[0-9a-f]+ <[^>]+> 3c83 subs r4, #131.*
0[0-9a-f]+ <[^>]+> 2d27 cmp r5, #39.*
-0[0-9a-f]+ <[^>]+> a103 add r1, pc, #12 ; \(adr [^)]*\)
-0[0-9a-f]+ <[^>]+> 4a03 ldr r2, \[pc, #12\] ; \([^)]*\)
+0[0-9a-f]+ <[^>]+> a103 add r1, pc, #12 @ \(adr [^)]*\)
+0[0-9a-f]+ <[^>]+> 4a03 ldr r2, \[pc, #12\] @ \([^)]*\)
0[0-9a-f]+ <[^>]+> 6863 ldr r3, \[r4, #4\]
0[0-9a-f]+ <[^>]+> 9d01 ldr r5, \[sp, #4\]
0[0-9a-f]+ <[^>]+> b001 add sp, #4
.*: +file format .*arm.*
Disassembly of section .text:
-0+000 <[^>]+> f60f 0000 addw r0, pc, #2048 ; 0x800
+0+000 <[^>]+> f60f 0000 addw r0, pc, #2048 @ 0x800
0+004 <[^>]+> f20f 0900 addw r9, pc, #0
-0+008 <[^>]+> f20f 4900 addw r9, pc, #1024 ; 0x400
-0+00c <[^>]+> f509 6880 add.w r8, r9, #1024 ; 0x400
-0+010 <[^>]+> f209 1801 addw r8, r9, #257 ; 0x101
-0+014 <[^>]+> f201 1301 addw r3, r1, #257 ; 0x101
-0+018 <[^>]+> f6af 0000 subw r0, pc, #2048 ; 0x800
+0+008 <[^>]+> f20f 4900 addw r9, pc, #1024 @ 0x400
+0+00c <[^>]+> f509 6880 add.w r8, r9, #1024 @ 0x400
+0+010 <[^>]+> f209 1801 addw r8, r9, #257 @ 0x101
+0+014 <[^>]+> f201 1301 addw r3, r1, #257 @ 0x101
+0+018 <[^>]+> f6af 0000 subw r0, pc, #2048 @ 0x800
0+01c <[^>]+> f2af 0900 subw r9, pc, #0
-0+020 <[^>]+> f2af 4900 subw r9, pc, #1024 ; 0x400
-0+024 <[^>]+> f5a9 6880 sub.w r8, r9, #1024 ; 0x400
-0+028 <[^>]+> f2a9 1801 subw r8, r9, #257 ; 0x101
-0+02c <[^>]+> f2a1 1301 subw r3, r1, #257 ; 0x101
+0+020 <[^>]+> f2af 4900 subw r9, pc, #1024 @ 0x400
+0+024 <[^>]+> f5a9 6880 sub.w r8, r9, #1024 @ 0x400
+0+028 <[^>]+> f2a9 1801 subw r8, r9, #257 @ 0x101
+0+02c <[^>]+> f2a1 1301 subw r3, r1, #257 @ 0x101
0+030 <[^>]+> f103 0301 add.w r3, r3, #1
0+034 <[^>]+> f1a3 0301 sub.w r3, r3, #1
-0+038 <[^>]+> b0c0 sub sp, #256 ; 0x100
-0+03a <[^>]+> f5ad 7d00 sub.w sp, sp, #512 ; 0x200
-0+03e <[^>]+> f2ad 1d01 subw sp, sp, #257 ; 0x101
-0+042 <[^>]+> b040 add sp, #256 ; 0x100
-0+044 <[^>]+> f50d 7d00 add.w sp, sp, #512 ; 0x200
-0+048 <[^>]+> f20d 1d01 addw sp, sp, #257 ; 0x101
-0+04c <[^>]+> a840 add r0, sp, #256 ; 0x100
-0+04e <[^>]+> f50d 6580 add.w r5, sp, #1024 ; 0x400
-0+052 <[^>]+> f20d 1901 addw r9, sp, #257 ; 0x101
+0+038 <[^>]+> b0c0 sub sp, #256 @ 0x100
+0+03a <[^>]+> f5ad 7d00 sub.w sp, sp, #512 @ 0x200
+0+03e <[^>]+> f2ad 1d01 subw sp, sp, #257 @ 0x101
+0+042 <[^>]+> b040 add sp, #256 @ 0x100
+0+044 <[^>]+> f50d 7d00 add.w sp, sp, #512 @ 0x200
+0+048 <[^>]+> f20d 1d01 addw sp, sp, #257 @ 0x101
+0+04c <[^>]+> a840 add r0, sp, #256 @ 0x100
+0+04e <[^>]+> f50d 6580 add.w r5, sp, #1024 @ 0x400
+0+052 <[^>]+> f20d 1901 addw r9, sp, #257 @ 0x101
0+056 <[^>]+> 4271 negs r1, r6
.*: +file format .*arm.*
Disassembly of section .text:
-0+000 <[^>]+> f517 0f80 cmn.w r7, #4194304 ; 0x400000
-0+004 <[^>]+> f5b8 0f80 cmp.w r8, #4194304 ; 0x400000
-0+008 <[^>]+> f5a4 0980 sub.w r9, r4, #4194304 ; 0x400000
-0+00c <[^>]+> f506 0380 add.w r3, r6, #4194304 ; 0x400000
-0+010 <[^>]+> f160 4500 sbc.w r5, r0, #2147483648 ; 0x80000000
-0+014 <[^>]+> f147 4400 adc.w r4, r7, #2147483648 ; 0x80000000
-0+018 <[^>]+> f022 4600 bic.w r6, r2, #2147483648 ; 0x80000000
-0+01c <[^>]+> f002 4800 and.w r8, r2, #2147483648 ; 0x80000000
-0+020 <[^>]+> f06f 4300 mvn.w r3, #2147483648 ; 0x80000000
-0+024 <[^>]+> f04f 4100 mov.w r1, #2147483648 ; 0x80000000
-0+028 <[^>]+> f062 4600 orn r6, r2, #2147483648 ; 0x80000000
-0+02c <[^>]+> f042 4800 orr.w r8, r2, #2147483648 ; 0x80000000
+0+000 <[^>]+> f517 0f80 cmn.w r7, #4194304 @ 0x400000
+0+004 <[^>]+> f5b8 0f80 cmp.w r8, #4194304 @ 0x400000
+0+008 <[^>]+> f5a4 0980 sub.w r9, r4, #4194304 @ 0x400000
+0+00c <[^>]+> f506 0380 add.w r3, r6, #4194304 @ 0x400000
+0+010 <[^>]+> f160 4500 sbc.w r5, r0, #2147483648 @ 0x80000000
+0+014 <[^>]+> f147 4400 adc.w r4, r7, #2147483648 @ 0x80000000
+0+018 <[^>]+> f022 4600 bic.w r6, r2, #2147483648 @ 0x80000000
+0+01c <[^>]+> f002 4800 and.w r8, r2, #2147483648 @ 0x80000000
+0+020 <[^>]+> f06f 4300 mvn.w r3, #2147483648 @ 0x80000000
+0+024 <[^>]+> f04f 4100 mov.w r1, #2147483648 @ 0x80000000
+0+028 <[^>]+> f062 4600 orn r6, r2, #2147483648 @ 0x80000000
+0+02c <[^>]+> f042 4800 orr.w r8, r2, #2147483648 @ 0x80000000
.*: +file format .*arm.*
Disassembly of section .text:
-0+000 <[^>]+> 4e04 ldr r6, \[pc, #16\] ; \(00+14 <[^>]+>\)
-0+002 <[^>]+> 4904 ldr r1, \[pc, #16\] ; \(00+14 <[^>]+>\)
-0+004 <[^>]+> f8df 600c ldr\.w r6, \[pc, #12\] ; 00+14 <[^>]+>
-0+008 <[^>]+> f8df 9008 ldr\.w r9, \[pc, #8\] ; 00+14 <[^>]+>
+0+000 <[^>]+> 4e04 ldr r6, \[pc, #16\] @ \(00+14 <[^>]+>\)
+0+002 <[^>]+> 4904 ldr r1, \[pc, #16\] @ \(00+14 <[^>]+>\)
+0+004 <[^>]+> f8df 600c ldr\.w r6, \[pc, #12\] @ 00+14 <[^>]+>
+0+008 <[^>]+> f8df 9008 ldr\.w r9, \[pc, #8\] @ 00+14 <[^>]+>
0+00c <[^>]+> bf00 nop
-0+00e <[^>]+> f8df 5004 ldr\.w r5, \[pc, #4\] ; 00+14 <[^>]+>
-0+012 <[^>]+> 4900 ldr r1, \[pc, #0\] ; \(00+14 <[^>]+>\)
+0+00e <[^>]+> f8df 5004 ldr\.w r5, \[pc, #4\] @ 00+14 <[^>]+>
+0+012 <[^>]+> 4900 ldr r1, \[pc, #0\] @ \(00+14 <[^>]+>\)
0+014 <[^>]+> 12345678 ? .word 0x12345678
-0+018 <[^>]+> 4907 ldr r1, \[pc, #28\] ; \(00000038 <[^>]+>\)
-0+01a <[^>]+> 4c07 ldr r4, \[pc, #28\] ; \(00000038 <[^>]+>\)
-0+01c <[^>]+> f8df 9018 ldr.w r9, \[pc, #24\] ; 00000038 <[^>]+>
-0+020 <[^>]+> f8df c014 ldr.w ip, \[pc, #20\] ; 00000038 <[^>]+>
-0+024 <[^>]+> f8df d010 ldr.w sp, \[pc, #16\] ; 00000038 <[^>]+>
-0+028 <[^>]+> 4904 ldr r1, \[pc, #16\] ; \(0000003c <[^>]+>\)
-0+02a <[^>]+> 4c04 ldr r4, \[pc, #16\] ; \(0000003c <[^>]+>\)
-0+02c <[^>]+> f8df 900c ldr.w r9, \[pc, #12\] ; 0000003c <[^>]+>
-0+030 <[^>]+> f8df c008 ldr.w ip, \[pc, #8\] ; 0000003c <[^>]+>
-0+034 <[^>]+> f8df d004 ldr.w sp, \[pc, #4\] ; 0000003c <[^>]+>
+0+018 <[^>]+> 4907 ldr r1, \[pc, #28\] @ \(00000038 <[^>]+>\)
+0+01a <[^>]+> 4c07 ldr r4, \[pc, #28\] @ \(00000038 <[^>]+>\)
+0+01c <[^>]+> f8df 9018 ldr.w r9, \[pc, #24\] @ 00000038 <[^>]+>
+0+020 <[^>]+> f8df c014 ldr.w ip, \[pc, #20\] @ 00000038 <[^>]+>
+0+024 <[^>]+> f8df d010 ldr.w sp, \[pc, #16\] @ 00000038 <[^>]+>
+0+028 <[^>]+> 4904 ldr r1, \[pc, #16\] @ \(0000003c <[^>]+>\)
+0+02a <[^>]+> 4c04 ldr r4, \[pc, #16\] @ \(0000003c <[^>]+>\)
+0+02c <[^>]+> f8df 900c ldr.w r9, \[pc, #12\] @ 0000003c <[^>]+>
+0+030 <[^>]+> f8df c008 ldr.w ip, \[pc, #8\] @ 0000003c <[^>]+>
+0+034 <[^>]+> f8df d004 ldr.w sp, \[pc, #4\] @ 0000003c <[^>]+>
0+038 <[^>]+> 00000000 .word 0x00000000
38: R_ARM_ABS32 ext_symbol
0+03c <[^>]+> 00001000 .word 0x00001000
0+01c <[^>]+> f815 1d1f ldrb.w r1, \[r5, #-31\]!
0+020 <[^>]+> 5d29 ldrb r1, \[r5, r4\]
0+022 <[^>]+> f819 100c ldrb.w r1, \[r9, ip\]
-0+026 <[^>]+> f89f 1014 ldrb.w r1, \[pc, #20\] ; 0+03c <[^>]+>
-0+02a <[^>]+> f89f 1010 ldrb.w r1, \[pc, #16\] ; 0+03c <[^>]+>
-0+02e <[^>]+> f89f 800c ldrb.w r8, \[pc, #12\] ; 0+03c <[^>]+>
-0+032 <[^>]+> f89f 100a ldrb.w r1, \[pc, #10\] ; 0+03e <[^>]+>
-0+036 <[^>]+> f81f 1038 ldrb.w r1, \[pc, #-56\] ; 0+000 <[^>]+>
+0+026 <[^>]+> f89f 1014 ldrb.w r1, \[pc, #20\] @ 0+03c <[^>]+>
+0+02a <[^>]+> f89f 1010 ldrb.w r1, \[pc, #16\] @ 0+03c <[^>]+>
+0+02e <[^>]+> f89f 800c ldrb.w r8, \[pc, #12\] @ 0+03c <[^>]+>
+0+032 <[^>]+> f89f 100a ldrb.w r1, \[pc, #10\] @ 0+03e <[^>]+>
+0+036 <[^>]+> f81f 1038 ldrb.w r1, \[pc, #-56\] @ 0+000 <[^>]+>
0+03a <[^>]+> bf00 nop
0+03c <[^>]+> bf00 nop
0+03e <[^>]+> f995 1000 ldrsb.w r1, \[r5\]
0+05e <[^>]+> f915 1d1f ldrsb.w r1, \[r5, #-31\]!
0+062 <[^>]+> 5729 ldrsb r1, \[r5, r4\]
0+064 <[^>]+> f919 100c ldrsb.w r1, \[r9, ip\]
-0+068 <[^>]+> f99f 1010 ldrsb.w r1, \[pc, #16\] ; 0+07c <[^>]+>
-0+06c <[^>]+> f99f 100c ldrsb.w r1, \[pc, #12\] ; 0+07c <[^>]+>
-0+070 <[^>]+> f99f 8008 ldrsb.w r8, \[pc, #8\] ; 0+07c <[^>]+>
-0+074 <[^>]+> f99f 1006 ldrsb.w r1, \[pc, #6\] ; 0+07e <[^>]+>
-0+078 <[^>]+> f91f 103e ldrsb.w r1, \[pc, #-62\] ; 0+03e <[^>]+>
+0+068 <[^>]+> f99f 1010 ldrsb.w r1, \[pc, #16\] @ 0+07c <[^>]+>
+0+06c <[^>]+> f99f 100c ldrsb.w r1, \[pc, #12\] @ 0+07c <[^>]+>
+0+070 <[^>]+> f99f 8008 ldrsb.w r8, \[pc, #8\] @ 0+07c <[^>]+>
+0+074 <[^>]+> f99f 1006 ldrsb.w r1, \[pc, #6\] @ 0+07e <[^>]+>
+0+078 <[^>]+> f91f 103e ldrsb.w r1, \[pc, #-62\] @ 0+03e <[^>]+>
0+07c <[^>]+> bf00 nop
0+07e <[^>]+> 8829 ldrh r1, \[r5, #0\]
0+080 <[^>]+> f8b5 1042 ldrh.w r1, \[r5, #66\].*
0+09a <[^>]+> f835 1d3e ldrh.w r1, \[r5, #-62\]!.*
0+09e <[^>]+> 5b29 ldrh r1, \[r5, r4\]
0+0a0 <[^>]+> f839 100c ldrh.w r1, \[r9, ip\]
-0+0a4 <[^>]+> f8bf 1010 ldrh.w r1, \[pc, #16\] ; 0+0b8 <[^>]+>
-0+0a8 <[^>]+> f8bf 100c ldrh.w r1, \[pc, #12\] ; 0+0b8 <[^>]+>
-0+0ac <[^>]+> f8bf 8008 ldrh.w r8, \[pc, #8\] ; 0+0b8 <[^>]+>
-0+0b0 <[^>]+> f8bf 1006 ldrh.w r1, \[pc, #6\] ; 0+0ba <[^>]+>
-0+0b4 <[^>]+> f83f 103a ldrh.w r1, \[pc, #-58\] ; 0+07e <[^>]+>
+0+0a4 <[^>]+> f8bf 1010 ldrh.w r1, \[pc, #16\] @ 0+0b8 <[^>]+>
+0+0a8 <[^>]+> f8bf 100c ldrh.w r1, \[pc, #12\] @ 0+0b8 <[^>]+>
+0+0ac <[^>]+> f8bf 8008 ldrh.w r8, \[pc, #8\] @ 0+0b8 <[^>]+>
+0+0b0 <[^>]+> f8bf 1006 ldrh.w r1, \[pc, #6\] @ 0+0ba <[^>]+>
+0+0b4 <[^>]+> f83f 103a ldrh.w r1, \[pc, #-58\] @ 0+07e <[^>]+>
0+0b8 <[^>]+> bf00 nop
0+0ba <[^>]+> f9b5 1000 ldrsh.w r1, \[r5\]
0+0be <[^>]+> f9b5 1042 ldrsh.w r1, \[r5, #66\].*
0+0da <[^>]+> f935 1d3e ldrsh.w r1, \[r5, #-62\]!.*
0+0de <[^>]+> 5f29 ldrsh r1, \[r5, r4\]
0+0e0 <[^>]+> f939 100c ldrsh.w r1, \[r9, ip\]
-0+0e4 <[^>]+> f9bf 1010 ldrsh.w r1, \[pc, #16\] ; 0+0f8 <[^>]+>
-0+0e8 <[^>]+> f9bf 100c ldrsh.w r1, \[pc, #12\] ; 0+0f8 <[^>]+>
-0+0ec <[^>]+> f9bf 8008 ldrsh.w r8, \[pc, #8\] ; 0+0f8 <[^>]+>
-0+0f0 <[^>]+> f9bf 1006 ldrsh.w r1, \[pc, #6\] ; 0+0fa <[^>]+>
-0+0f4 <[^>]+> f93f 103e ldrsh.w r1, \[pc, #-62\] ; 0+0ba <[^>]+>
+0+0e4 <[^>]+> f9bf 1010 ldrsh.w r1, \[pc, #16\] @ 0+0f8 <[^>]+>
+0+0e8 <[^>]+> f9bf 100c ldrsh.w r1, \[pc, #12\] @ 0+0f8 <[^>]+>
+0+0ec <[^>]+> f9bf 8008 ldrsh.w r8, \[pc, #8\] @ 0+0f8 <[^>]+>
+0+0f0 <[^>]+> f9bf 1006 ldrsh.w r1, \[pc, #6\] @ 0+0fa <[^>]+>
+0+0f4 <[^>]+> f93f 103e ldrsh.w r1, \[pc, #-62\] @ 0+0ba <[^>]+>
0+0f8 <[^>]+> bf00 nop
0+0fa <[^>]+> 6829 ldr r1, \[r5, #0\]
0+0fc <[^>]+> f8d5 1080 ldr.w r1, \[r5, #128\].*
0+116 <[^>]+> f855 1d7c ldr.w r1, \[r5, #-124\]!.*
0+11a <[^>]+> 5929 ldr r1, \[r5, r4\]
0+11c <[^>]+> f859 100c ldr.w r1, \[r9, ip\]
-0+120 <[^>]+> 4904 ldr r1, \[pc, #16\] ; \(0+134 <[^>]+>\)
-0+122 <[^>]+> f8df 1010 ldr.w r1, \[pc, #16\] ; 0+134 <[^>]+>
-0+126 <[^>]+> f8df 800c ldr.w r8, \[pc, #12\] ; 0+134 <[^>]+>
-0+12a <[^>]+> f8df 100a ldr.w r1, \[pc, #10\] ; 0+136 <[^>]+>
-0+12e <[^>]+> f85f 1036 ldr.w r1, \[pc, #-54\] ; 0+0fa <[^>]+>
+0+120 <[^>]+> 4904 ldr r1, \[pc, #16\] @ \(0+134 <[^>]+>\)
+0+122 <[^>]+> f8df 1010 ldr.w r1, \[pc, #16\] @ 0+134 <[^>]+>
+0+126 <[^>]+> f8df 800c ldr.w r8, \[pc, #12\] @ 0+134 <[^>]+>
+0+12a <[^>]+> f8df 100a ldr.w r1, \[pc, #10\] @ 0+136 <[^>]+>
+0+12e <[^>]+> f85f 1036 ldr.w r1, \[pc, #-54\] @ 0+0fa <[^>]+>
0+132 <[^>]+> bf00 nop
0+134 <[^>]+> bf00 nop
-0+136 <[^>]+> a104 add r1, pc, #16 ; \(adr r1, 0+148 <[^>]+>\)
+0+136 <[^>]+> a104 add r1, pc, #16 @ \(adr r1, 0+148 <[^>]+>\)
0+138 <[^>]+> f20f 010c addw r1, pc, #12
0+13c <[^>]+> f20f 0808 addw r8, pc, #8
0+140 <[^>]+> f20f 0106 addw r1, pc, #6
.*: +file format .*arm.*
Disassembly of section .text:
-00000000 <thumb2_ldr> ed9f 0a0f vldr s0, \[pc, #60\] ; 00000040 <thumb2_ldr\+0x40>
-00000004 <thumb2_ldr\+0x4> ed9f 7a0e vldr s14, \[pc, #56\] ; 00000040 <thumb2_ldr\+0x40>
-00000008 <thumb2_ldr\+0x8> ed9f ea0d vldr s28, \[pc, #52\] ; 00000040 <thumb2_ldr\+0x40>
-0000000c <thumb2_ldr\+0xc> eddf fa0c vldr s31, \[pc, #48\] ; 00000040 <thumb2_ldr\+0x40>
-00000010 <thumb2_ldr\+0x10> ed9f 0a0c vldr s0, \[pc, #48\] ; 00000044 <thumb2_ldr\+0x44>
-00000014 <thumb2_ldr\+0x14> ed9f 7a0b vldr s14, \[pc, #44\] ; 00000044 <thumb2_ldr\+0x44>
-00000018 <thumb2_ldr\+0x18> ed9f ea0a vldr s28, \[pc, #40\] ; 00000044 <thumb2_ldr\+0x44>
-0000001c <thumb2_ldr\+0x1c> eddf fa09 vldr s31, \[pc, #36\] ; 00000044 <thumb2_ldr\+0x44>
-00000020 <thumb2_ldr\+0x20> ed9f 0a09 vldr s0, \[pc, #36\] ; 00000048 <thumb2_ldr\+0x48>
-00000024 <thumb2_ldr\+0x24> ed9f 7a08 vldr s14, \[pc, #32\] ; 00000048 <thumb2_ldr\+0x48>
-00000028 <thumb2_ldr\+0x28> ed9f ea07 vldr s28, \[pc, #28\] ; 00000048 <thumb2_ldr\+0x48>
-0000002c <thumb2_ldr\+0x2c> eddf fa06 vldr s31, \[pc, #24\] ; 00000048 <thumb2_ldr\+0x48>
-00000030 <thumb2_ldr\+0x30> ed9f 0a06 vldr s0, \[pc, #24\] ; 0000004c <thumb2_ldr\+0x4c>
-00000034 <thumb2_ldr\+0x34> ed9f 7a05 vldr s14, \[pc, #20\] ; 0000004c <thumb2_ldr\+0x4c>
-00000038 <thumb2_ldr\+0x38> ed9f ea04 vldr s28, \[pc, #16\] ; 0000004c <thumb2_ldr\+0x4c>
-0000003c <thumb2_ldr\+0x3c> eddf fa03 vldr s31, \[pc, #12\] ; 0000004c <thumb2_ldr\+0x4c>
+00000000 <thumb2_ldr> ed9f 0a0f vldr s0, \[pc, #60\] @ 00000040 <thumb2_ldr\+0x40>
+00000004 <thumb2_ldr\+0x4> ed9f 7a0e vldr s14, \[pc, #56\] @ 00000040 <thumb2_ldr\+0x40>
+00000008 <thumb2_ldr\+0x8> ed9f ea0d vldr s28, \[pc, #52\] @ 00000040 <thumb2_ldr\+0x40>
+0000000c <thumb2_ldr\+0xc> eddf fa0c vldr s31, \[pc, #48\] @ 00000040 <thumb2_ldr\+0x40>
+00000010 <thumb2_ldr\+0x10> ed9f 0a0c vldr s0, \[pc, #48\] @ 00000044 <thumb2_ldr\+0x44>
+00000014 <thumb2_ldr\+0x14> ed9f 7a0b vldr s14, \[pc, #44\] @ 00000044 <thumb2_ldr\+0x44>
+00000018 <thumb2_ldr\+0x18> ed9f ea0a vldr s28, \[pc, #40\] @ 00000044 <thumb2_ldr\+0x44>
+0000001c <thumb2_ldr\+0x1c> eddf fa09 vldr s31, \[pc, #36\] @ 00000044 <thumb2_ldr\+0x44>
+00000020 <thumb2_ldr\+0x20> ed9f 0a09 vldr s0, \[pc, #36\] @ 00000048 <thumb2_ldr\+0x48>
+00000024 <thumb2_ldr\+0x24> ed9f 7a08 vldr s14, \[pc, #32\] @ 00000048 <thumb2_ldr\+0x48>
+00000028 <thumb2_ldr\+0x28> ed9f ea07 vldr s28, \[pc, #28\] @ 00000048 <thumb2_ldr\+0x48>
+0000002c <thumb2_ldr\+0x2c> eddf fa06 vldr s31, \[pc, #24\] @ 00000048 <thumb2_ldr\+0x48>
+00000030 <thumb2_ldr\+0x30> ed9f 0a06 vldr s0, \[pc, #24\] @ 0000004c <thumb2_ldr\+0x4c>
+00000034 <thumb2_ldr\+0x34> ed9f 7a05 vldr s14, \[pc, #20\] @ 0000004c <thumb2_ldr\+0x4c>
+00000038 <thumb2_ldr\+0x38> ed9f ea04 vldr s28, \[pc, #16\] @ 0000004c <thumb2_ldr\+0x4c>
+0000003c <thumb2_ldr\+0x3c> eddf fa03 vldr s31, \[pc, #12\] @ 0000004c <thumb2_ldr\+0x4c>
00000040 <thumb2_ldr\+0x40> 00000000 .word 0x00000000
00000044 <thumb2_ldr\+0x44> ff000000 .word 0xff000000
00000048 <thumb2_ldr\+0x48> ffffffff .word 0xffffffff
0000004c <thumb2_ldr\+0x4c> 0fff0000 .word 0x0fff0000
-00000050 <thumb2_ldr\+0x50> ed9f 0a0f vldr s0, \[pc, #60\] ; 00000090 <thumb2_ldr\+0x90>
-00000054 <thumb2_ldr\+0x54> ed9f 7a0e vldr s14, \[pc, #56\] ; 00000090 <thumb2_ldr\+0x90>
-00000058 <thumb2_ldr\+0x58> ed9f ea0d vldr s28, \[pc, #52\] ; 00000090 <thumb2_ldr\+0x90>
-0000005c <thumb2_ldr\+0x5c> eddf fa0c vldr s31, \[pc, #48\] ; 00000090 <thumb2_ldr\+0x90>
-00000060 <thumb2_ldr\+0x60> ed9f 0a0c vldr s0, \[pc, #48\] ; 00000094 <thumb2_ldr\+0x94>
-00000064 <thumb2_ldr\+0x64> ed9f 7a0b vldr s14, \[pc, #44\] ; 00000094 <thumb2_ldr\+0x94>
-00000068 <thumb2_ldr\+0x68> ed9f ea0a vldr s28, \[pc, #40\] ; 00000094 <thumb2_ldr\+0x94>
-0000006c <thumb2_ldr\+0x6c> eddf fa09 vldr s31, \[pc, #36\] ; 00000094 <thumb2_ldr\+0x94>
-00000070 <thumb2_ldr\+0x70> ed9f 0a09 vldr s0, \[pc, #36\] ; 00000098 <thumb2_ldr\+0x98>
-00000074 <thumb2_ldr\+0x74> ed9f 7a08 vldr s14, \[pc, #32\] ; 00000098 <thumb2_ldr\+0x98>
-00000078 <thumb2_ldr\+0x78> ed9f ea07 vldr s28, \[pc, #28\] ; 00000098 <thumb2_ldr\+0x98>
-0000007c <thumb2_ldr\+0x7c> eddf fa06 vldr s31, \[pc, #24\] ; 00000098 <thumb2_ldr\+0x98>
-00000080 <thumb2_ldr\+0x80> ed9f 0a06 vldr s0, \[pc, #24\] ; 0000009c <thumb2_ldr\+0x9c>
-00000084 <thumb2_ldr\+0x84> ed9f 7a05 vldr s14, \[pc, #20\] ; 0000009c <thumb2_ldr\+0x9c>
-00000088 <thumb2_ldr\+0x88> ed9f ea04 vldr s28, \[pc, #16\] ; 0000009c <thumb2_ldr\+0x9c>
-0000008c <thumb2_ldr\+0x8c> eddf fa03 vldr s31, \[pc, #12\] ; 0000009c <thumb2_ldr\+0x9c>
+00000050 <thumb2_ldr\+0x50> ed9f 0a0f vldr s0, \[pc, #60\] @ 00000090 <thumb2_ldr\+0x90>
+00000054 <thumb2_ldr\+0x54> ed9f 7a0e vldr s14, \[pc, #56\] @ 00000090 <thumb2_ldr\+0x90>
+00000058 <thumb2_ldr\+0x58> ed9f ea0d vldr s28, \[pc, #52\] @ 00000090 <thumb2_ldr\+0x90>
+0000005c <thumb2_ldr\+0x5c> eddf fa0c vldr s31, \[pc, #48\] @ 00000090 <thumb2_ldr\+0x90>
+00000060 <thumb2_ldr\+0x60> ed9f 0a0c vldr s0, \[pc, #48\] @ 00000094 <thumb2_ldr\+0x94>
+00000064 <thumb2_ldr\+0x64> ed9f 7a0b vldr s14, \[pc, #44\] @ 00000094 <thumb2_ldr\+0x94>
+00000068 <thumb2_ldr\+0x68> ed9f ea0a vldr s28, \[pc, #40\] @ 00000094 <thumb2_ldr\+0x94>
+0000006c <thumb2_ldr\+0x6c> eddf fa09 vldr s31, \[pc, #36\] @ 00000094 <thumb2_ldr\+0x94>
+00000070 <thumb2_ldr\+0x70> ed9f 0a09 vldr s0, \[pc, #36\] @ 00000098 <thumb2_ldr\+0x98>
+00000074 <thumb2_ldr\+0x74> ed9f 7a08 vldr s14, \[pc, #32\] @ 00000098 <thumb2_ldr\+0x98>
+00000078 <thumb2_ldr\+0x78> ed9f ea07 vldr s28, \[pc, #28\] @ 00000098 <thumb2_ldr\+0x98>
+0000007c <thumb2_ldr\+0x7c> eddf fa06 vldr s31, \[pc, #24\] @ 00000098 <thumb2_ldr\+0x98>
+00000080 <thumb2_ldr\+0x80> ed9f 0a06 vldr s0, \[pc, #24\] @ 0000009c <thumb2_ldr\+0x9c>
+00000084 <thumb2_ldr\+0x84> ed9f 7a05 vldr s14, \[pc, #20\] @ 0000009c <thumb2_ldr\+0x9c>
+00000088 <thumb2_ldr\+0x88> ed9f ea04 vldr s28, \[pc, #16\] @ 0000009c <thumb2_ldr\+0x9c>
+0000008c <thumb2_ldr\+0x8c> eddf fa03 vldr s31, \[pc, #12\] @ 0000009c <thumb2_ldr\+0x9c>
00000090 <thumb2_ldr\+0x90> 00000000 .word 0x00000000
00000094 <thumb2_ldr\+0x94> 00ff0000 .word 0x00ff0000
00000098 <thumb2_ldr\+0x98> ff00ffff .word 0xff00ffff
000000a4 <thumb2_ldr\+0xa4> ef80 ee30 vmov.i64 d14, #0x0000000000000000
000000a8 <thumb2_ldr\+0xa8> efc0 ce30 vmov.i64 d28, #0x0000000000000000
000000ac <thumb2_ldr\+0xac> efc0 fe30 vmov.i64 d31, #0x0000000000000000
-000000b0 <thumb2_ldr\+0xb0> ed9f 0b0b vldr d0, \[pc, #44\] ; 000000e0 <thumb2_ldr\+0xe0>
-000000b4 <thumb2_ldr\+0xb4> ed9f eb0a vldr d14, \[pc, #40\] ; 000000e0 <thumb2_ldr\+0xe0>
-000000b8 <thumb2_ldr\+0xb8> eddf cb09 vldr d28, \[pc, #36\] ; 000000e0 <thumb2_ldr\+0xe0>
-000000bc <thumb2_ldr\+0xbc> eddf fb08 vldr d31, \[pc, #32\] ; 000000e0 <thumb2_ldr\+0xe0>
+000000b0 <thumb2_ldr\+0xb0> ed9f 0b0b vldr d0, \[pc, #44\] @ 000000e0 <thumb2_ldr\+0xe0>
+000000b4 <thumb2_ldr\+0xb4> ed9f eb0a vldr d14, \[pc, #40\] @ 000000e0 <thumb2_ldr\+0xe0>
+000000b8 <thumb2_ldr\+0xb8> eddf cb09 vldr d28, \[pc, #36\] @ 000000e0 <thumb2_ldr\+0xe0>
+000000bc <thumb2_ldr\+0xbc> eddf fb08 vldr d31, \[pc, #32\] @ 000000e0 <thumb2_ldr\+0xe0>
000000c0 <thumb2_ldr\+0xc0> ff87 0e3f vmov.i64 d0, #0xffffffffffffffff
000000c4 <thumb2_ldr\+0xc4> ff87 ee3f vmov.i64 d14, #0xffffffffffffffff
000000c8 <thumb2_ldr\+0xc8> ffc7 ce3f vmov.i64 d28, #0xffffffffffffffff
000000cc <thumb2_ldr\+0xcc> ffc7 fe3f vmov.i64 d31, #0xffffffffffffffff
-000000d0 <thumb2_ldr\+0xd0> ed9f 0b05 vldr d0, \[pc, #20\] ; 000000e8 <thumb2_ldr\+0xe8>
-000000d4 <thumb2_ldr\+0xd4> ed9f eb04 vldr d14, \[pc, #16\] ; 000000e8 <thumb2_ldr\+0xe8>
-000000d8 <thumb2_ldr\+0xd8> eddf cb03 vldr d28, \[pc, #12\] ; 000000e8 <thumb2_ldr\+0xe8>
-000000dc <thumb2_ldr\+0xdc> eddf fb02 vldr d31, \[pc, #8\] ; 000000e8 <thumb2_ldr\+0xe8>
+000000d0 <thumb2_ldr\+0xd0> ed9f 0b05 vldr d0, \[pc, #20\] @ 000000e8 <thumb2_ldr\+0xe8>
+000000d4 <thumb2_ldr\+0xd4> ed9f eb04 vldr d14, \[pc, #16\] @ 000000e8 <thumb2_ldr\+0xe8>
+000000d8 <thumb2_ldr\+0xd8> eddf cb03 vldr d28, \[pc, #12\] @ 000000e8 <thumb2_ldr\+0xe8>
+000000dc <thumb2_ldr\+0xdc> eddf fb02 vldr d31, \[pc, #8\] @ 000000e8 <thumb2_ldr\+0xe8>
000000e0 <thumb2_ldr\+0xe0> ca000000 .word 0xca000000
000000e4 <thumb2_ldr\+0xe4> 00000000 .word 0x00000000
000000e8 <thumb2_ldr\+0xe8> 0fff0000 .word 0x0fff0000
00000114 <thumb2_ldr\+0x114> ef80 ee39 vmov.i64 d14, #0x00000000ff0000ff
00000118 <thumb2_ldr\+0x118> efc0 ce39 vmov.i64 d28, #0x00000000ff0000ff
0000011c <thumb2_ldr\+0x11c> efc0 fe39 vmov.i64 d31, #0x00000000ff0000ff
-00000120 <thumb2_ldr\+0x120> ed9f 0b03 vldr d0, \[pc, #12\] ; 00000130 <thumb2_ldr\+0x130>
-00000124 <thumb2_ldr\+0x124> ed9f eb02 vldr d14, \[pc, #8\] ; 00000130 <thumb2_ldr\+0x130>
-00000128 <thumb2_ldr\+0x128> eddf cb01 vldr d28, \[pc, #4\] ; 00000130 <thumb2_ldr\+0x130>
-0000012c <thumb2_ldr\+0x12c> eddf fb00 vldr d31, \[pc\] ; 00000130 <thumb2_ldr\+0x130>
+00000120 <thumb2_ldr\+0x120> ed9f 0b03 vldr d0, \[pc, #12\] @ 00000130 <thumb2_ldr\+0x130>
+00000124 <thumb2_ldr\+0x124> ed9f eb02 vldr d14, \[pc, #8\] @ 00000130 <thumb2_ldr\+0x130>
+00000128 <thumb2_ldr\+0x128> eddf cb01 vldr d28, \[pc, #4\] @ 00000130 <thumb2_ldr\+0x130>
+0000012c <thumb2_ldr\+0x12c> eddf fb00 vldr d31, \[pc\] @ 00000130 <thumb2_ldr\+0x130>
00000130 <thumb2_ldr\+0x130> 00fff000 .word 0x00fff000
00000134 <thumb2_ldr\+0x134> 00000000 .word 0x00000000
00000138 <thumb2_ldr\+0x138> ef80 0e30 vmov.i64 d0, #0x0000000000000000
0000015c <thumb2_ldr\+0x15c> ff87 ee3f vmov.i64 d14, #0xffffffffffffffff
00000160 <thumb2_ldr\+0x160> ffc7 ce3f vmov.i64 d28, #0xffffffffffffffff
00000164 <thumb2_ldr\+0x164> ffc7 fe3f vmov.i64 d31, #0xffffffffffffffff
-00000168 <thumb2_ldr\+0x168> ed9f 0b03 vldr d0, \[pc, #12\] ; 00000178 <thumb2_ldr\+0x178>
-0000016c <thumb2_ldr\+0x16c> ed9f eb02 vldr d14, \[pc, #8\] ; 00000178 <thumb2_ldr\+0x178>
-00000170 <thumb2_ldr\+0x170> eddf cb01 vldr d28, \[pc, #4\] ; 00000178 <thumb2_ldr\+0x178>
-00000174 <thumb2_ldr\+0x174> eddf fb00 vldr d31, \[pc\] ; 00000178 <thumb2_ldr\+0x178>
+00000168 <thumb2_ldr\+0x168> ed9f 0b03 vldr d0, \[pc, #12\] @ 00000178 <thumb2_ldr\+0x178>
+0000016c <thumb2_ldr\+0x16c> ed9f eb02 vldr d14, \[pc, #8\] @ 00000178 <thumb2_ldr\+0x178>
+00000170 <thumb2_ldr\+0x170> eddf cb01 vldr d28, \[pc, #4\] @ 00000178 <thumb2_ldr\+0x178>
+00000174 <thumb2_ldr\+0x174> eddf fb00 vldr d31, \[pc\] @ 00000178 <thumb2_ldr\+0x178>
00000178 <thumb2_ldr\+0x178> 00000000 .word 0x00000000
0000017c <thumb2_ldr\+0x17c> 0fff0000 .word 0x0fff0000
00000180 <thumb2_ldr\+0x180> ef80 0e30 vmov.i64 d0, #0x0000000000000000
00000184 <thumb2_ldr\+0x184> ef80 ee30 vmov.i64 d14, #0x0000000000000000
00000188 <thumb2_ldr\+0x188> efc0 ce30 vmov.i64 d28, #0x0000000000000000
0000018c <thumb2_ldr\+0x18c> efc0 fe30 vmov.i64 d31, #0x0000000000000000
-00000190 <thumb2_ldr\+0x190> ed9f 0b0b vldr d0, \[pc, #44\] ; 000001c0 <thumb2_ldr\+0x1c0>
-00000194 <thumb2_ldr\+0x194> ed9f eb0a vldr d14, \[pc, #40\] ; 000001c0 <thumb2_ldr\+0x1c0>
-00000198 <thumb2_ldr\+0x198> eddf cb09 vldr d28, \[pc, #36\] ; 000001c0 <thumb2_ldr\+0x1c0>
-0000019c <thumb2_ldr\+0x19c> eddf fb08 vldr d31, \[pc, #32\] ; 000001c0 <thumb2_ldr\+0x1c0>
-000001a0 <thumb2_ldr\+0x1a0> ed9f 0b09 vldr d0, \[pc, #36\] ; 000001c8 <thumb2_ldr\+0x1c8>
-000001a4 <thumb2_ldr\+0x1a4> ed9f eb08 vldr d14, \[pc, #32\] ; 000001c8 <thumb2_ldr\+0x1c8>
-000001a8 <thumb2_ldr\+0x1a8> eddf cb07 vldr d28, \[pc, #28\] ; 000001c8 <thumb2_ldr\+0x1c8>
-000001ac <thumb2_ldr\+0x1ac> eddf fb06 vldr d31, \[pc, #24\] ; 000001c8 <thumb2_ldr\+0x1c8>
-000001b0 <thumb2_ldr\+0x1b0> ed9f 0b05 vldr d0, \[pc, #20\] ; 000001c8 <thumb2_ldr\+0x1c8>
-000001b4 <thumb2_ldr\+0x1b4> ed9f eb04 vldr d14, \[pc, #16\] ; 000001c8 <thumb2_ldr\+0x1c8>
-000001b8 <thumb2_ldr\+0x1b8> eddf cb03 vldr d28, \[pc, #12\] ; 000001c8 <thumb2_ldr\+0x1c8>
-000001bc <thumb2_ldr\+0x1bc> eddf fb02 vldr d31, \[pc, #8\] ; 000001c8 <thumb2_ldr\+0x1c8>
+00000190 <thumb2_ldr\+0x190> ed9f 0b0b vldr d0, \[pc, #44\] @ 000001c0 <thumb2_ldr\+0x1c0>
+00000194 <thumb2_ldr\+0x194> ed9f eb0a vldr d14, \[pc, #40\] @ 000001c0 <thumb2_ldr\+0x1c0>
+00000198 <thumb2_ldr\+0x198> eddf cb09 vldr d28, \[pc, #36\] @ 000001c0 <thumb2_ldr\+0x1c0>
+0000019c <thumb2_ldr\+0x19c> eddf fb08 vldr d31, \[pc, #32\] @ 000001c0 <thumb2_ldr\+0x1c0>
+000001a0 <thumb2_ldr\+0x1a0> ed9f 0b09 vldr d0, \[pc, #36\] @ 000001c8 <thumb2_ldr\+0x1c8>
+000001a4 <thumb2_ldr\+0x1a4> ed9f eb08 vldr d14, \[pc, #32\] @ 000001c8 <thumb2_ldr\+0x1c8>
+000001a8 <thumb2_ldr\+0x1a8> eddf cb07 vldr d28, \[pc, #28\] @ 000001c8 <thumb2_ldr\+0x1c8>
+000001ac <thumb2_ldr\+0x1ac> eddf fb06 vldr d31, \[pc, #24\] @ 000001c8 <thumb2_ldr\+0x1c8>
+000001b0 <thumb2_ldr\+0x1b0> ed9f 0b05 vldr d0, \[pc, #20\] @ 000001c8 <thumb2_ldr\+0x1c8>
+000001b4 <thumb2_ldr\+0x1b4> ed9f eb04 vldr d14, \[pc, #16\] @ 000001c8 <thumb2_ldr\+0x1c8>
+000001b8 <thumb2_ldr\+0x1b8> eddf cb03 vldr d28, \[pc, #12\] @ 000001c8 <thumb2_ldr\+0x1c8>
+000001bc <thumb2_ldr\+0x1bc> eddf fb02 vldr d31, \[pc, #8\] @ 000001c8 <thumb2_ldr\+0x1c8>
000001c0 <thumb2_ldr\+0x1c0> 00000000 .word 0x00000000
000001c4 <thumb2_ldr\+0x1c4> 000ff000 .word 0x000ff000
000001c8 <thumb2_ldr\+0x1c8> f0000000 .word 0xf0000000
000001cc <thumb2_ldr\+0x1cc> 0ff00fff .word 0x0ff00fff
-000001d0 <thumb2_ldr\+0x1d0> ed9f 1b01 vldr d1, \[pc, #4\] ; 000001d8 <thumb2_ldr\+0x1d8>
+000001d0 <thumb2_ldr\+0x1d0> ed9f 1b01 vldr d1, \[pc, #4\] @ 000001d8 <thumb2_ldr\+0x1d8>
\.\.\.
000001dc <thumb2_ldr\+0x1dc> 0000fff0 .word 0x0000fff0
000001e0 <thumb2_ldr\+0x1e0> f101 0000 add.w r0, r1, #0
-000001e4 <thumb2_ldr\+0x1e4> ed9f 1b00 vldr d1, \[pc\] ; 000001e8 <thumb2_ldr\+0x1e8>
+000001e4 <thumb2_ldr\+0x1e4> ed9f 1b00 vldr d1, \[pc\] @ 000001e8 <thumb2_ldr\+0x1e8>
000001e8 <thumb2_ldr\+0x1e8> 00000000 .word 0x00000000
000001ec <thumb2_ldr\+0x1ec> 0000fff0 .word 0x0000fff0
-000001f0 <thumb2_ldr\+0x1f0> ed9f 1b11 vldr d1, \[pc, #68\] ; 00000238 <thumb2_ldr\+0x238>
-000001f4 <thumb2_ldr\+0x1f4> ed9f 1a12 vldr s2, \[pc, #72\] ; 00000240 <thumb2_ldr\+0x240>
-000001f8 <thumb2_ldr\+0x1f8> ed9f 3b13 vldr d3, \[pc, #76\] ; 00000248 <thumb2_ldr\+0x248>
-000001fc <thumb2_ldr\+0x1fc> ed9f 2a11 vldr s4, \[pc, #68\] ; 00000244 <thumb2_ldr\+0x244>
-00000200 <thumb2_ldr\+0x200> ed9f 5b11 vldr d5, \[pc, #68\] ; 00000248 <thumb2_ldr\+0x248>
-00000204 <thumb2_ldr\+0x204> ed9f 6b12 vldr d6, \[pc, #72\] ; 00000250 <thumb2_ldr\+0x250>
-00000208 <thumb2_ldr\+0x208> ed9f 7b13 vldr d7, \[pc, #76\] ; 00000258 <thumb2_ldr\+0x258>
-0000020c <thumb2_ldr\+0x20c> ed9f 4a14 vldr s8, \[pc, #80\] ; 00000260 <thumb2_ldr\+0x260>
-00000210 <thumb2_ldr\+0x210> ed9f 9b15 vldr d9, \[pc, #84\] ; 00000268 <thumb2_ldr\+0x268>
-00000214 <thumb2_ldr\+0x214> ed9f 5a13 vldr s10, \[pc, #76\] ; 00000264 <thumb2_ldr\+0x264>
-00000218 <thumb2_ldr\+0x218> ed9f bb15 vldr d11, \[pc, #84\] ; 00000270 <thumb2_ldr\+0x270>
-0000021c <thumb2_ldr\+0x21c> ed9f 6a16 vldr s12, \[pc, #88\] ; 00000278 <thumb2_ldr\+0x278>
-00000220 <thumb2_ldr\+0x220> eddf 6a16 vldr s13, \[pc, #88\] ; 0000027c <thumb2_ldr\+0x27c>
-00000224 <thumb2_ldr\+0x224> ed9f 7a07 vldr s14, \[pc, #28\] ; 00000244 <thumb2_ldr\+0x244>
-00000228 <thumb2_ldr\+0x228> eddf 7a04 vldr s15, \[pc, #16\] ; 0000023c <thumb2_ldr\+0x23c>
-0000022c <thumb2_ldr\+0x22c> eddf 0b12 vldr d16, \[pc, #72\] ; 00000278 <thumb2_ldr\+0x278>
-00000230 <thumb2_ldr\+0x230> eddf 1b13 vldr d17, \[pc, #76\] ; 00000280 <thumb2_ldr\+0x280>
+000001f0 <thumb2_ldr\+0x1f0> ed9f 1b11 vldr d1, \[pc, #68\] @ 00000238 <thumb2_ldr\+0x238>
+000001f4 <thumb2_ldr\+0x1f4> ed9f 1a12 vldr s2, \[pc, #72\] @ 00000240 <thumb2_ldr\+0x240>
+000001f8 <thumb2_ldr\+0x1f8> ed9f 3b13 vldr d3, \[pc, #76\] @ 00000248 <thumb2_ldr\+0x248>
+000001fc <thumb2_ldr\+0x1fc> ed9f 2a11 vldr s4, \[pc, #68\] @ 00000244 <thumb2_ldr\+0x244>
+00000200 <thumb2_ldr\+0x200> ed9f 5b11 vldr d5, \[pc, #68\] @ 00000248 <thumb2_ldr\+0x248>
+00000204 <thumb2_ldr\+0x204> ed9f 6b12 vldr d6, \[pc, #72\] @ 00000250 <thumb2_ldr\+0x250>
+00000208 <thumb2_ldr\+0x208> ed9f 7b13 vldr d7, \[pc, #76\] @ 00000258 <thumb2_ldr\+0x258>
+0000020c <thumb2_ldr\+0x20c> ed9f 4a14 vldr s8, \[pc, #80\] @ 00000260 <thumb2_ldr\+0x260>
+00000210 <thumb2_ldr\+0x210> ed9f 9b15 vldr d9, \[pc, #84\] @ 00000268 <thumb2_ldr\+0x268>
+00000214 <thumb2_ldr\+0x214> ed9f 5a13 vldr s10, \[pc, #76\] @ 00000264 <thumb2_ldr\+0x264>
+00000218 <thumb2_ldr\+0x218> ed9f bb15 vldr d11, \[pc, #84\] @ 00000270 <thumb2_ldr\+0x270>
+0000021c <thumb2_ldr\+0x21c> ed9f 6a16 vldr s12, \[pc, #88\] @ 00000278 <thumb2_ldr\+0x278>
+00000220 <thumb2_ldr\+0x220> eddf 6a16 vldr s13, \[pc, #88\] @ 0000027c <thumb2_ldr\+0x27c>
+00000224 <thumb2_ldr\+0x224> ed9f 7a07 vldr s14, \[pc, #28\] @ 00000244 <thumb2_ldr\+0x244>
+00000228 <thumb2_ldr\+0x228> eddf 7a04 vldr s15, \[pc, #16\] @ 0000023c <thumb2_ldr\+0x23c>
+0000022c <thumb2_ldr\+0x22c> eddf 0b12 vldr d16, \[pc, #72\] @ 00000278 <thumb2_ldr\+0x278>
+00000230 <thumb2_ldr\+0x230> eddf 1b13 vldr d17, \[pc, #76\] @ 00000280 <thumb2_ldr\+0x280>
\.\.\.
0000023c <thumb2_ldr\+0x23c> 0000fff0 .word 0x0000fff0
00000240 <thumb2_ldr\+0x240> ff000000 .word 0xff000000
.*: +file format .*arm.*
Disassembly of section .text:
-00000000 <thumb2_ldr> ed9f 0a0f vldr s0, \[pc, #60\] ; 00000040 <thumb2_ldr\+0x40>
-00000004 <thumb2_ldr\+0x4> ed9f 7a0e vldr s14, \[pc, #56\] ; 00000040 <thumb2_ldr\+0x40>
-00000008 <thumb2_ldr\+0x8> ed9f ea0d vldr s28, \[pc, #52\] ; 00000040 <thumb2_ldr\+0x40>
-0000000c <thumb2_ldr\+0xc> eddf fa0c vldr s31, \[pc, #48\] ; 00000040 <thumb2_ldr\+0x40>
-00000010 <thumb2_ldr\+0x10> ed9f 0a0c vldr s0, \[pc, #48\] ; 00000044 <thumb2_ldr\+0x44>
-00000014 <thumb2_ldr\+0x14> ed9f 7a0b vldr s14, \[pc, #44\] ; 00000044 <thumb2_ldr\+0x44>
-00000018 <thumb2_ldr\+0x18> ed9f ea0a vldr s28, \[pc, #40\] ; 00000044 <thumb2_ldr\+0x44>
-0000001c <thumb2_ldr\+0x1c> eddf fa09 vldr s31, \[pc, #36\] ; 00000044 <thumb2_ldr\+0x44>
-00000020 <thumb2_ldr\+0x20> ed9f 0a09 vldr s0, \[pc, #36\] ; 00000048 <thumb2_ldr\+0x48>
-00000024 <thumb2_ldr\+0x24> ed9f 7a08 vldr s14, \[pc, #32\] ; 00000048 <thumb2_ldr\+0x48>
-00000028 <thumb2_ldr\+0x28> ed9f ea07 vldr s28, \[pc, #28\] ; 00000048 <thumb2_ldr\+0x48>
-0000002c <thumb2_ldr\+0x2c> eddf fa06 vldr s31, \[pc, #24\] ; 00000048 <thumb2_ldr\+0x48>
-00000030 <thumb2_ldr\+0x30> ed9f 0a06 vldr s0, \[pc, #24\] ; 0000004c <thumb2_ldr\+0x4c>
-00000034 <thumb2_ldr\+0x34> ed9f 7a05 vldr s14, \[pc, #20\] ; 0000004c <thumb2_ldr\+0x4c>
-00000038 <thumb2_ldr\+0x38> ed9f ea04 vldr s28, \[pc, #16\] ; 0000004c <thumb2_ldr\+0x4c>
-0000003c <thumb2_ldr\+0x3c> eddf fa03 vldr s31, \[pc, #12\] ; 0000004c <thumb2_ldr\+0x4c>
+00000000 <thumb2_ldr> ed9f 0a0f vldr s0, \[pc, #60\] @ 00000040 <thumb2_ldr\+0x40>
+00000004 <thumb2_ldr\+0x4> ed9f 7a0e vldr s14, \[pc, #56\] @ 00000040 <thumb2_ldr\+0x40>
+00000008 <thumb2_ldr\+0x8> ed9f ea0d vldr s28, \[pc, #52\] @ 00000040 <thumb2_ldr\+0x40>
+0000000c <thumb2_ldr\+0xc> eddf fa0c vldr s31, \[pc, #48\] @ 00000040 <thumb2_ldr\+0x40>
+00000010 <thumb2_ldr\+0x10> ed9f 0a0c vldr s0, \[pc, #48\] @ 00000044 <thumb2_ldr\+0x44>
+00000014 <thumb2_ldr\+0x14> ed9f 7a0b vldr s14, \[pc, #44\] @ 00000044 <thumb2_ldr\+0x44>
+00000018 <thumb2_ldr\+0x18> ed9f ea0a vldr s28, \[pc, #40\] @ 00000044 <thumb2_ldr\+0x44>
+0000001c <thumb2_ldr\+0x1c> eddf fa09 vldr s31, \[pc, #36\] @ 00000044 <thumb2_ldr\+0x44>
+00000020 <thumb2_ldr\+0x20> ed9f 0a09 vldr s0, \[pc, #36\] @ 00000048 <thumb2_ldr\+0x48>
+00000024 <thumb2_ldr\+0x24> ed9f 7a08 vldr s14, \[pc, #32\] @ 00000048 <thumb2_ldr\+0x48>
+00000028 <thumb2_ldr\+0x28> ed9f ea07 vldr s28, \[pc, #28\] @ 00000048 <thumb2_ldr\+0x48>
+0000002c <thumb2_ldr\+0x2c> eddf fa06 vldr s31, \[pc, #24\] @ 00000048 <thumb2_ldr\+0x48>
+00000030 <thumb2_ldr\+0x30> ed9f 0a06 vldr s0, \[pc, #24\] @ 0000004c <thumb2_ldr\+0x4c>
+00000034 <thumb2_ldr\+0x34> ed9f 7a05 vldr s14, \[pc, #20\] @ 0000004c <thumb2_ldr\+0x4c>
+00000038 <thumb2_ldr\+0x38> ed9f ea04 vldr s28, \[pc, #16\] @ 0000004c <thumb2_ldr\+0x4c>
+0000003c <thumb2_ldr\+0x3c> eddf fa03 vldr s31, \[pc, #12\] @ 0000004c <thumb2_ldr\+0x4c>
00000040 <thumb2_ldr\+0x40> 00000000 .word 0x00000000
00000044 <thumb2_ldr\+0x44> ff000000 .word 0xff000000
00000048 <thumb2_ldr\+0x48> ffffffff .word 0xffffffff
0000004c <thumb2_ldr\+0x4c> 0fff0000 .word 0x0fff0000
-00000050 <thumb2_ldr\+0x50> ed9f 0a0f vldr s0, \[pc, #60\] ; 00000090 <thumb2_ldr\+0x90>
-00000054 <thumb2_ldr\+0x54> ed9f 7a0e vldr s14, \[pc, #56\] ; 00000090 <thumb2_ldr\+0x90>
-00000058 <thumb2_ldr\+0x58> ed9f ea0d vldr s28, \[pc, #52\] ; 00000090 <thumb2_ldr\+0x90>
-0000005c <thumb2_ldr\+0x5c> eddf fa0c vldr s31, \[pc, #48\] ; 00000090 <thumb2_ldr\+0x90>
-00000060 <thumb2_ldr\+0x60> ed9f 0a0c vldr s0, \[pc, #48\] ; 00000094 <thumb2_ldr\+0x94>
-00000064 <thumb2_ldr\+0x64> ed9f 7a0b vldr s14, \[pc, #44\] ; 00000094 <thumb2_ldr\+0x94>
-00000068 <thumb2_ldr\+0x68> ed9f ea0a vldr s28, \[pc, #40\] ; 00000094 <thumb2_ldr\+0x94>
-0000006c <thumb2_ldr\+0x6c> eddf fa09 vldr s31, \[pc, #36\] ; 00000094 <thumb2_ldr\+0x94>
-00000070 <thumb2_ldr\+0x70> ed9f 0a09 vldr s0, \[pc, #36\] ; 00000098 <thumb2_ldr\+0x98>
-00000074 <thumb2_ldr\+0x74> ed9f 7a08 vldr s14, \[pc, #32\] ; 00000098 <thumb2_ldr\+0x98>
-00000078 <thumb2_ldr\+0x78> ed9f ea07 vldr s28, \[pc, #28\] ; 00000098 <thumb2_ldr\+0x98>
-0000007c <thumb2_ldr\+0x7c> eddf fa06 vldr s31, \[pc, #24\] ; 00000098 <thumb2_ldr\+0x98>
-00000080 <thumb2_ldr\+0x80> ed9f 0a06 vldr s0, \[pc, #24\] ; 0000009c <thumb2_ldr\+0x9c>
-00000084 <thumb2_ldr\+0x84> ed9f 7a05 vldr s14, \[pc, #20\] ; 0000009c <thumb2_ldr\+0x9c>
-00000088 <thumb2_ldr\+0x88> ed9f ea04 vldr s28, \[pc, #16\] ; 0000009c <thumb2_ldr\+0x9c>
-0000008c <thumb2_ldr\+0x8c> eddf fa03 vldr s31, \[pc, #12\] ; 0000009c <thumb2_ldr\+0x9c>
+00000050 <thumb2_ldr\+0x50> ed9f 0a0f vldr s0, \[pc, #60\] @ 00000090 <thumb2_ldr\+0x90>
+00000054 <thumb2_ldr\+0x54> ed9f 7a0e vldr s14, \[pc, #56\] @ 00000090 <thumb2_ldr\+0x90>
+00000058 <thumb2_ldr\+0x58> ed9f ea0d vldr s28, \[pc, #52\] @ 00000090 <thumb2_ldr\+0x90>
+0000005c <thumb2_ldr\+0x5c> eddf fa0c vldr s31, \[pc, #48\] @ 00000090 <thumb2_ldr\+0x90>
+00000060 <thumb2_ldr\+0x60> ed9f 0a0c vldr s0, \[pc, #48\] @ 00000094 <thumb2_ldr\+0x94>
+00000064 <thumb2_ldr\+0x64> ed9f 7a0b vldr s14, \[pc, #44\] @ 00000094 <thumb2_ldr\+0x94>
+00000068 <thumb2_ldr\+0x68> ed9f ea0a vldr s28, \[pc, #40\] @ 00000094 <thumb2_ldr\+0x94>
+0000006c <thumb2_ldr\+0x6c> eddf fa09 vldr s31, \[pc, #36\] @ 00000094 <thumb2_ldr\+0x94>
+00000070 <thumb2_ldr\+0x70> ed9f 0a09 vldr s0, \[pc, #36\] @ 00000098 <thumb2_ldr\+0x98>
+00000074 <thumb2_ldr\+0x74> ed9f 7a08 vldr s14, \[pc, #32\] @ 00000098 <thumb2_ldr\+0x98>
+00000078 <thumb2_ldr\+0x78> ed9f ea07 vldr s28, \[pc, #28\] @ 00000098 <thumb2_ldr\+0x98>
+0000007c <thumb2_ldr\+0x7c> eddf fa06 vldr s31, \[pc, #24\] @ 00000098 <thumb2_ldr\+0x98>
+00000080 <thumb2_ldr\+0x80> ed9f 0a06 vldr s0, \[pc, #24\] @ 0000009c <thumb2_ldr\+0x9c>
+00000084 <thumb2_ldr\+0x84> ed9f 7a05 vldr s14, \[pc, #20\] @ 0000009c <thumb2_ldr\+0x9c>
+00000088 <thumb2_ldr\+0x88> ed9f ea04 vldr s28, \[pc, #16\] @ 0000009c <thumb2_ldr\+0x9c>
+0000008c <thumb2_ldr\+0x8c> eddf fa03 vldr s31, \[pc, #12\] @ 0000009c <thumb2_ldr\+0x9c>
00000090 <thumb2_ldr\+0x90> 00000000 .word 0x00000000
00000094 <thumb2_ldr\+0x94> 00ff0000 .word 0x00ff0000
00000098 <thumb2_ldr\+0x98> ff00ffff .word 0xff00ffff
000000a4 <thumb2_ldr\+0xa4> ef80 ee30 vmov.i64 d14, #0x0000000000000000
000000a8 <thumb2_ldr\+0xa8> efc0 ce30 vmov.i64 d28, #0x0000000000000000
000000ac <thumb2_ldr\+0xac> efc0 fe30 vmov.i64 d31, #0x0000000000000000
-000000b0 <thumb2_ldr\+0xb0> ed9f 0b0b vldr d0, \[pc, #44\] ; 000000e0 <thumb2_ldr\+0xe0>
-000000b4 <thumb2_ldr\+0xb4> ed9f eb0a vldr d14, \[pc, #40\] ; 000000e0 <thumb2_ldr\+0xe0>
-000000b8 <thumb2_ldr\+0xb8> eddf cb09 vldr d28, \[pc, #36\] ; 000000e0 <thumb2_ldr\+0xe0>
-000000bc <thumb2_ldr\+0xbc> eddf fb08 vldr d31, \[pc, #32\] ; 000000e0 <thumb2_ldr\+0xe0>
+000000b0 <thumb2_ldr\+0xb0> ed9f 0b0b vldr d0, \[pc, #44\] @ 000000e0 <thumb2_ldr\+0xe0>
+000000b4 <thumb2_ldr\+0xb4> ed9f eb0a vldr d14, \[pc, #40\] @ 000000e0 <thumb2_ldr\+0xe0>
+000000b8 <thumb2_ldr\+0xb8> eddf cb09 vldr d28, \[pc, #36\] @ 000000e0 <thumb2_ldr\+0xe0>
+000000bc <thumb2_ldr\+0xbc> eddf fb08 vldr d31, \[pc, #32\] @ 000000e0 <thumb2_ldr\+0xe0>
000000c0 <thumb2_ldr\+0xc0> ff87 0e3f vmov.i64 d0, #0xffffffffffffffff
000000c4 <thumb2_ldr\+0xc4> ff87 ee3f vmov.i64 d14, #0xffffffffffffffff
000000c8 <thumb2_ldr\+0xc8> ffc7 ce3f vmov.i64 d28, #0xffffffffffffffff
000000cc <thumb2_ldr\+0xcc> ffc7 fe3f vmov.i64 d31, #0xffffffffffffffff
-000000d0 <thumb2_ldr\+0xd0> ed9f 0b05 vldr d0, \[pc, #20\] ; 000000e8 <thumb2_ldr\+0xe8>
-000000d4 <thumb2_ldr\+0xd4> ed9f eb04 vldr d14, \[pc, #16\] ; 000000e8 <thumb2_ldr\+0xe8>
-000000d8 <thumb2_ldr\+0xd8> eddf cb03 vldr d28, \[pc, #12\] ; 000000e8 <thumb2_ldr\+0xe8>
-000000dc <thumb2_ldr\+0xdc> eddf fb02 vldr d31, \[pc, #8\] ; 000000e8 <thumb2_ldr\+0xe8>
+000000d0 <thumb2_ldr\+0xd0> ed9f 0b05 vldr d0, \[pc, #20\] @ 000000e8 <thumb2_ldr\+0xe8>
+000000d4 <thumb2_ldr\+0xd4> ed9f eb04 vldr d14, \[pc, #16\] @ 000000e8 <thumb2_ldr\+0xe8>
+000000d8 <thumb2_ldr\+0xd8> eddf cb03 vldr d28, \[pc, #12\] @ 000000e8 <thumb2_ldr\+0xe8>
+000000dc <thumb2_ldr\+0xdc> eddf fb02 vldr d31, \[pc, #8\] @ 000000e8 <thumb2_ldr\+0xe8>
000000e0 <thumb2_ldr\+0xe0> 00000000 .word 0x00000000
000000e4 <thumb2_ldr\+0xe4> ca000000 .word 0xca000000
000000e8 <thumb2_ldr\+0xe8> 00000000 .word 0x00000000
00000114 <thumb2_ldr\+0x114> ef80 ee39 vmov.i64 d14, #0x00000000ff0000ff
00000118 <thumb2_ldr\+0x118> efc0 ce39 vmov.i64 d28, #0x00000000ff0000ff
0000011c <thumb2_ldr\+0x11c> efc0 fe39 vmov.i64 d31, #0x00000000ff0000ff
-00000120 <thumb2_ldr\+0x120> ed9f 0b03 vldr d0, \[pc, #12\] ; 00000130 <thumb2_ldr\+0x130>
-00000124 <thumb2_ldr\+0x124> ed9f eb02 vldr d14, \[pc, #8\] ; 00000130 <thumb2_ldr\+0x130>
-00000128 <thumb2_ldr\+0x128> eddf cb01 vldr d28, \[pc, #4\] ; 00000130 <thumb2_ldr\+0x130>
-0000012c <thumb2_ldr\+0x12c> eddf fb00 vldr d31, \[pc\] ; 00000130 <thumb2_ldr\+0x130>
+00000120 <thumb2_ldr\+0x120> ed9f 0b03 vldr d0, \[pc, #12\] @ 00000130 <thumb2_ldr\+0x130>
+00000124 <thumb2_ldr\+0x124> ed9f eb02 vldr d14, \[pc, #8\] @ 00000130 <thumb2_ldr\+0x130>
+00000128 <thumb2_ldr\+0x128> eddf cb01 vldr d28, \[pc, #4\] @ 00000130 <thumb2_ldr\+0x130>
+0000012c <thumb2_ldr\+0x12c> eddf fb00 vldr d31, \[pc\] @ 00000130 <thumb2_ldr\+0x130>
00000130 <thumb2_ldr\+0x130> 00000000 .word 0x00000000
00000134 <thumb2_ldr\+0x134> 00fff000 .word 0x00fff000
00000138 <thumb2_ldr\+0x138> ef80 0e30 vmov.i64 d0, #0x0000000000000000
0000015c <thumb2_ldr\+0x15c> ff87 ee3f vmov.i64 d14, #0xffffffffffffffff
00000160 <thumb2_ldr\+0x160> ffc7 ce3f vmov.i64 d28, #0xffffffffffffffff
00000164 <thumb2_ldr\+0x164> ffc7 fe3f vmov.i64 d31, #0xffffffffffffffff
-00000168 <thumb2_ldr\+0x168> ed9f 0b03 vldr d0, \[pc, #12\] ; 00000178 <thumb2_ldr\+0x178>
-0000016c <thumb2_ldr\+0x16c> ed9f eb02 vldr d14, \[pc, #8\] ; 00000178 <thumb2_ldr\+0x178>
-00000170 <thumb2_ldr\+0x170> eddf cb01 vldr d28, \[pc, #4\] ; 00000178 <thumb2_ldr\+0x178>
-00000174 <thumb2_ldr\+0x174> eddf fb00 vldr d31, \[pc\] ; 00000178 <thumb2_ldr\+0x178>
+00000168 <thumb2_ldr\+0x168> ed9f 0b03 vldr d0, \[pc, #12\] @ 00000178 <thumb2_ldr\+0x178>
+0000016c <thumb2_ldr\+0x16c> ed9f eb02 vldr d14, \[pc, #8\] @ 00000178 <thumb2_ldr\+0x178>
+00000170 <thumb2_ldr\+0x170> eddf cb01 vldr d28, \[pc, #4\] @ 00000178 <thumb2_ldr\+0x178>
+00000174 <thumb2_ldr\+0x174> eddf fb00 vldr d31, \[pc\] @ 00000178 <thumb2_ldr\+0x178>
00000178 <thumb2_ldr\+0x178> 0fff0000 .word 0x0fff0000
0000017c <thumb2_ldr\+0x17c> 00000000 .word 0x00000000
00000180 <thumb2_ldr\+0x180> ef80 0e30 vmov.i64 d0, #0x0000000000000000
00000184 <thumb2_ldr\+0x184> ef80 ee30 vmov.i64 d14, #0x0000000000000000
00000188 <thumb2_ldr\+0x188> efc0 ce30 vmov.i64 d28, #0x0000000000000000
0000018c <thumb2_ldr\+0x18c> efc0 fe30 vmov.i64 d31, #0x0000000000000000
-00000190 <thumb2_ldr\+0x190> ed9f 0b0b vldr d0, \[pc, #44\] ; 000001c0 <thumb2_ldr\+0x1c0>
-00000194 <thumb2_ldr\+0x194> ed9f eb0a vldr d14, \[pc, #40\] ; 000001c0 <thumb2_ldr\+0x1c0>
-00000198 <thumb2_ldr\+0x198> eddf cb09 vldr d28, \[pc, #36\] ; 000001c0 <thumb2_ldr\+0x1c0>
-0000019c <thumb2_ldr\+0x19c> eddf fb08 vldr d31, \[pc, #32\] ; 000001c0 <thumb2_ldr\+0x1c0>
-000001a0 <thumb2_ldr\+0x1a0> ed9f 0b09 vldr d0, \[pc, #36\] ; 000001c8 <thumb2_ldr\+0x1c8>
-000001a4 <thumb2_ldr\+0x1a4> ed9f eb08 vldr d14, \[pc, #32\] ; 000001c8 <thumb2_ldr\+0x1c8>
-000001a8 <thumb2_ldr\+0x1a8> eddf cb07 vldr d28, \[pc, #28\] ; 000001c8 <thumb2_ldr\+0x1c8>
-000001ac <thumb2_ldr\+0x1ac> eddf fb06 vldr d31, \[pc, #24\] ; 000001c8 <thumb2_ldr\+0x1c8>
-000001b0 <thumb2_ldr\+0x1b0> ed9f 0b05 vldr d0, \[pc, #20\] ; 000001c8 <thumb2_ldr\+0x1c8>
-000001b4 <thumb2_ldr\+0x1b4> ed9f eb04 vldr d14, \[pc, #16\] ; 000001c8 <thumb2_ldr\+0x1c8>
-000001b8 <thumb2_ldr\+0x1b8> eddf cb03 vldr d28, \[pc, #12\] ; 000001c8 <thumb2_ldr\+0x1c8>
-000001bc <thumb2_ldr\+0x1bc> eddf fb02 vldr d31, \[pc, #8\] ; 000001c8 <thumb2_ldr\+0x1c8>
+00000190 <thumb2_ldr\+0x190> ed9f 0b0b vldr d0, \[pc, #44\] @ 000001c0 <thumb2_ldr\+0x1c0>
+00000194 <thumb2_ldr\+0x194> ed9f eb0a vldr d14, \[pc, #40\] @ 000001c0 <thumb2_ldr\+0x1c0>
+00000198 <thumb2_ldr\+0x198> eddf cb09 vldr d28, \[pc, #36\] @ 000001c0 <thumb2_ldr\+0x1c0>
+0000019c <thumb2_ldr\+0x19c> eddf fb08 vldr d31, \[pc, #32\] @ 000001c0 <thumb2_ldr\+0x1c0>
+000001a0 <thumb2_ldr\+0x1a0> ed9f 0b09 vldr d0, \[pc, #36\] @ 000001c8 <thumb2_ldr\+0x1c8>
+000001a4 <thumb2_ldr\+0x1a4> ed9f eb08 vldr d14, \[pc, #32\] @ 000001c8 <thumb2_ldr\+0x1c8>
+000001a8 <thumb2_ldr\+0x1a8> eddf cb07 vldr d28, \[pc, #28\] @ 000001c8 <thumb2_ldr\+0x1c8>
+000001ac <thumb2_ldr\+0x1ac> eddf fb06 vldr d31, \[pc, #24\] @ 000001c8 <thumb2_ldr\+0x1c8>
+000001b0 <thumb2_ldr\+0x1b0> ed9f 0b05 vldr d0, \[pc, #20\] @ 000001c8 <thumb2_ldr\+0x1c8>
+000001b4 <thumb2_ldr\+0x1b4> ed9f eb04 vldr d14, \[pc, #16\] @ 000001c8 <thumb2_ldr\+0x1c8>
+000001b8 <thumb2_ldr\+0x1b8> eddf cb03 vldr d28, \[pc, #12\] @ 000001c8 <thumb2_ldr\+0x1c8>
+000001bc <thumb2_ldr\+0x1bc> eddf fb02 vldr d31, \[pc, #8\] @ 000001c8 <thumb2_ldr\+0x1c8>
000001c0 <thumb2_ldr\+0x1c0> 000ff000 .word 0x000ff000
000001c4 <thumb2_ldr\+0x1c4> 00000000 .word 0x00000000
000001c8 <thumb2_ldr\+0x1c8> 0ff00fff .word 0x0ff00fff
000001cc <thumb2_ldr\+0x1cc> f0000000 .word 0xf0000000
-000001d0 <thumb2_ldr\+0x1d0> ed9f 1b01 vldr d1, \[pc, #4\] ; 000001d8 <thumb2_ldr\+0x1d8>
+000001d0 <thumb2_ldr\+0x1d0> ed9f 1b01 vldr d1, \[pc, #4\] @ 000001d8 <thumb2_ldr\+0x1d8>
000001d4 <thumb2_ldr\+0x1d4> 00000000 .word 0x00000000
000001d8 <thumb2_ldr\+0x1d8> 0000fff0 .word 0x0000fff0
000001dc <thumb2_ldr\+0x1dc> 00000000 .word 0x00000000
000001e0 <thumb2_ldr\+0x1e0> f101 0000 add.w r0, r1, #0
-000001e4 <thumb2_ldr\+0x1e4> ed9f 1b00 vldr d1, \[pc\] ; 000001e8 <thumb2_ldr\+0x1e8>
+000001e4 <thumb2_ldr\+0x1e4> ed9f 1b00 vldr d1, \[pc\] @ 000001e8 <thumb2_ldr\+0x1e8>
000001e8 <thumb2_ldr\+0x1e8> 0000fff0 .word 0x0000fff0
000001ec <thumb2_ldr\+0x1ec> 00000000 .word 0x00000000
-000001f0 <thumb2_ldr\+0x1f0> ed9f 1b11 vldr d1, \[pc, #68\] ; 00000238 <thumb2_ldr\+0x238>
-000001f4 <thumb2_ldr\+0x1f4> ed9f 1a12 vldr s2, \[pc, #72\] ; 00000240 <thumb2_ldr\+0x240>
-000001f8 <thumb2_ldr\+0x1f8> ed9f 3b13 vldr d3, \[pc, #76\] ; 00000248 <thumb2_ldr\+0x248>
-000001fc <thumb2_ldr\+0x1fc> ed9f 2a11 vldr s4, \[pc, #68\] ; 00000244 <thumb2_ldr\+0x244>
-00000200 <thumb2_ldr\+0x200> ed9f 5b11 vldr d5, \[pc, #68\] ; 00000248 <thumb2_ldr\+0x248>
-00000204 <thumb2_ldr\+0x204> ed9f 6b12 vldr d6, \[pc, #72\] ; 00000250 <thumb2_ldr\+0x250>
-00000208 <thumb2_ldr\+0x208> ed9f 7b13 vldr d7, \[pc, #76\] ; 00000258 <thumb2_ldr\+0x258>
-0000020c <thumb2_ldr\+0x20c> ed9f 4a14 vldr s8, \[pc, #80\] ; 00000260 <thumb2_ldr\+0x260>
-00000210 <thumb2_ldr\+0x210> ed9f 9b15 vldr d9, \[pc, #84\] ; 00000268 <thumb2_ldr\+0x268>
-00000214 <thumb2_ldr\+0x214> ed9f 5a13 vldr s10, \[pc, #76\] ; 00000264 <thumb2_ldr\+0x264>
-00000218 <thumb2_ldr\+0x218> ed9f bb15 vldr d11, \[pc, #84\] ; 00000270 <thumb2_ldr\+0x270>
-0000021c <thumb2_ldr\+0x21c> ed9f 6a16 vldr s12, \[pc, #88\] ; 00000278 <thumb2_ldr\+0x278>
-00000220 <thumb2_ldr\+0x220> eddf 6a16 vldr s13, \[pc, #88\] ; 0000027c <thumb2_ldr\+0x27c>
-00000224 <thumb2_ldr\+0x224> ed9f 7a07 vldr s14, \[pc, #28\] ; 00000244 <thumb2_ldr\+0x244>
-00000228 <thumb2_ldr\+0x228> eddf 7a03 vldr s15, \[pc, #12\] ; 00000238 <thumb2_ldr\+0x238>
-0000022c <thumb2_ldr\+0x22c> eddf 0b14 vldr d16, \[pc, #80\] ; 00000280 <thumb2_ldr\+0x280>
-00000230 <thumb2_ldr\+0x230> eddf 1b15 vldr d17, \[pc, #84\] ; 00000288 <thumb2_ldr\+0x288>
+000001f0 <thumb2_ldr\+0x1f0> ed9f 1b11 vldr d1, \[pc, #68\] @ 00000238 <thumb2_ldr\+0x238>
+000001f4 <thumb2_ldr\+0x1f4> ed9f 1a12 vldr s2, \[pc, #72\] @ 00000240 <thumb2_ldr\+0x240>
+000001f8 <thumb2_ldr\+0x1f8> ed9f 3b13 vldr d3, \[pc, #76\] @ 00000248 <thumb2_ldr\+0x248>
+000001fc <thumb2_ldr\+0x1fc> ed9f 2a11 vldr s4, \[pc, #68\] @ 00000244 <thumb2_ldr\+0x244>
+00000200 <thumb2_ldr\+0x200> ed9f 5b11 vldr d5, \[pc, #68\] @ 00000248 <thumb2_ldr\+0x248>
+00000204 <thumb2_ldr\+0x204> ed9f 6b12 vldr d6, \[pc, #72\] @ 00000250 <thumb2_ldr\+0x250>
+00000208 <thumb2_ldr\+0x208> ed9f 7b13 vldr d7, \[pc, #76\] @ 00000258 <thumb2_ldr\+0x258>
+0000020c <thumb2_ldr\+0x20c> ed9f 4a14 vldr s8, \[pc, #80\] @ 00000260 <thumb2_ldr\+0x260>
+00000210 <thumb2_ldr\+0x210> ed9f 9b15 vldr d9, \[pc, #84\] @ 00000268 <thumb2_ldr\+0x268>
+00000214 <thumb2_ldr\+0x214> ed9f 5a13 vldr s10, \[pc, #76\] @ 00000264 <thumb2_ldr\+0x264>
+00000218 <thumb2_ldr\+0x218> ed9f bb15 vldr d11, \[pc, #84\] @ 00000270 <thumb2_ldr\+0x270>
+0000021c <thumb2_ldr\+0x21c> ed9f 6a16 vldr s12, \[pc, #88\] @ 00000278 <thumb2_ldr\+0x278>
+00000220 <thumb2_ldr\+0x220> eddf 6a16 vldr s13, \[pc, #88\] @ 0000027c <thumb2_ldr\+0x27c>
+00000224 <thumb2_ldr\+0x224> ed9f 7a07 vldr s14, \[pc, #28\] @ 00000244 <thumb2_ldr\+0x244>
+00000228 <thumb2_ldr\+0x228> eddf 7a03 vldr s15, \[pc, #12\] @ 00000238 <thumb2_ldr\+0x238>
+0000022c <thumb2_ldr\+0x22c> eddf 0b14 vldr d16, \[pc, #80\] @ 00000280 <thumb2_ldr\+0x280>
+00000230 <thumb2_ldr\+0x230> eddf 1b15 vldr d17, \[pc, #84\] @ 00000288 <thumb2_ldr\+0x288>
00000234 <thumb2_ldr\+0x234> 00000000 .word 0x00000000
00000238 <thumb2_ldr\+0x238> 0000fff0 .word 0x0000fff0
0000023c <thumb2_ldr\+0x23c> 00000000 .word 0x00000000
Disassembly of section .text:
0[0-9a-f]+ <[^>]+> f041 0000 orr\.w r0, r1, #0
-0[0-9a-f]+ <[^>]+> f041 00a5 orr\.w r0, r1, #165 ; 0xa5
-0[0-9a-f]+ <[^>]+> f041 10a5 orr\.w r0, r1, #10813605 ; 0xa500a5
-0[0-9a-f]+ <[^>]+> f041 20a5 orr\.w r0, r1, #2768282880 ; 0xa500a500
-0[0-9a-f]+ <[^>]+> f041 30a5 orr\.w r0, r1, #2779096485 ; 0xa5a5a5a5
-0[0-9a-f]+ <[^>]+> f041 4000 orr\.w r0, r1, #2147483648 ; 0x80000000
-0[0-9a-f]+ <[^>]+> f041 4080 orr\.w r0, r1, #1073741824 ; 0x40000000
-0[0-9a-f]+ <[^>]+> f041 4020 orr\.w r0, r1, #2684354560 ; 0xa0000000
-0[0-9a-f]+ <[^>]+> f041 40a0 orr\.w r0, r1, #1342177280 ; 0x50000000
-0[0-9a-f]+ <[^>]+> f041 5020 orr\.w r0, r1, #671088640 ; 0x28000000
-0[0-9a-f]+ <[^>]+> f041 4014 orr\.w r0, r1, #2483027968 ; 0x94000000
-0[0-9a-f]+ <[^>]+> f041 4094 orr\.w r0, r1, #1241513984 ; 0x4a000000
-0[0-9a-f]+ <[^>]+> f041 4025 orr\.w r0, r1, #2768240640 ; 0xa5000000
-0[0-9a-f]+ <[^>]+> f041 40a5 orr\.w r0, r1, #1384120320 ; 0x52800000
-0[0-9a-f]+ <[^>]+> f041 5025 orr\.w r0, r1, #692060160 ; 0x29400000
-0[0-9a-f]+ <[^>]+> f041 50a5 orr\.w r0, r1, #346030080 ; 0x14a00000
-0[0-9a-f]+ <[^>]+> f041 6025 orr\.w r0, r1, #173015040 ; 0xa500000
-0[0-9a-f]+ <[^>]+> f041 60a5 orr\.w r0, r1, #86507520 ; 0x5280000
-0[0-9a-f]+ <[^>]+> f041 7025 orr\.w r0, r1, #43253760 ; 0x2940000
-0[0-9a-f]+ <[^>]+> f041 70a5 orr\.w r0, r1, #21626880 ; 0x14a0000
-0[0-9a-f]+ <[^>]+> f441 0025 orr\.w r0, r1, #10813440 ; 0xa50000
-0[0-9a-f]+ <[^>]+> f441 00a5 orr\.w r0, r1, #5406720 ; 0x528000
-0[0-9a-f]+ <[^>]+> f441 1025 orr\.w r0, r1, #2703360 ; 0x294000
-0[0-9a-f]+ <[^>]+> f441 10a5 orr\.w r0, r1, #1351680 ; 0x14a000
-0[0-9a-f]+ <[^>]+> f441 2025 orr\.w r0, r1, #675840 ; 0xa5000
-0[0-9a-f]+ <[^>]+> f441 20a5 orr\.w r0, r1, #337920 ; 0x52800
-0[0-9a-f]+ <[^>]+> f441 3025 orr\.w r0, r1, #168960 ; 0x29400
-0[0-9a-f]+ <[^>]+> f441 30a5 orr\.w r0, r1, #84480 ; 0x14a00
-0[0-9a-f]+ <[^>]+> f441 4025 orr\.w r0, r1, #42240 ; 0xa500
-0[0-9a-f]+ <[^>]+> f441 40a5 orr\.w r0, r1, #21120 ; 0x5280
-0[0-9a-f]+ <[^>]+> f441 5025 orr\.w r0, r1, #10560 ; 0x2940
-0[0-9a-f]+ <[^>]+> f441 50a5 orr\.w r0, r1, #5280 ; 0x14a0
-0[0-9a-f]+ <[^>]+> f441 6025 orr\.w r0, r1, #2640 ; 0xa50
-0[0-9a-f]+ <[^>]+> f441 60a5 orr\.w r0, r1, #1320 ; 0x528
-0[0-9a-f]+ <[^>]+> f441 7025 orr\.w r0, r1, #660 ; 0x294
-0[0-9a-f]+ <[^>]+> f441 70a5 orr\.w r0, r1, #330 ; 0x14a
+0[0-9a-f]+ <[^>]+> f041 00a5 orr\.w r0, r1, #165 @ 0xa5
+0[0-9a-f]+ <[^>]+> f041 10a5 orr\.w r0, r1, #10813605 @ 0xa500a5
+0[0-9a-f]+ <[^>]+> f041 20a5 orr\.w r0, r1, #2768282880 @ 0xa500a500
+0[0-9a-f]+ <[^>]+> f041 30a5 orr\.w r0, r1, #2779096485 @ 0xa5a5a5a5
+0[0-9a-f]+ <[^>]+> f041 4000 orr\.w r0, r1, #2147483648 @ 0x80000000
+0[0-9a-f]+ <[^>]+> f041 4080 orr\.w r0, r1, #1073741824 @ 0x40000000
+0[0-9a-f]+ <[^>]+> f041 4020 orr\.w r0, r1, #2684354560 @ 0xa0000000
+0[0-9a-f]+ <[^>]+> f041 40a0 orr\.w r0, r1, #1342177280 @ 0x50000000
+0[0-9a-f]+ <[^>]+> f041 5020 orr\.w r0, r1, #671088640 @ 0x28000000
+0[0-9a-f]+ <[^>]+> f041 4014 orr\.w r0, r1, #2483027968 @ 0x94000000
+0[0-9a-f]+ <[^>]+> f041 4094 orr\.w r0, r1, #1241513984 @ 0x4a000000
+0[0-9a-f]+ <[^>]+> f041 4025 orr\.w r0, r1, #2768240640 @ 0xa5000000
+0[0-9a-f]+ <[^>]+> f041 40a5 orr\.w r0, r1, #1384120320 @ 0x52800000
+0[0-9a-f]+ <[^>]+> f041 5025 orr\.w r0, r1, #692060160 @ 0x29400000
+0[0-9a-f]+ <[^>]+> f041 50a5 orr\.w r0, r1, #346030080 @ 0x14a00000
+0[0-9a-f]+ <[^>]+> f041 6025 orr\.w r0, r1, #173015040 @ 0xa500000
+0[0-9a-f]+ <[^>]+> f041 60a5 orr\.w r0, r1, #86507520 @ 0x5280000
+0[0-9a-f]+ <[^>]+> f041 7025 orr\.w r0, r1, #43253760 @ 0x2940000
+0[0-9a-f]+ <[^>]+> f041 70a5 orr\.w r0, r1, #21626880 @ 0x14a0000
+0[0-9a-f]+ <[^>]+> f441 0025 orr\.w r0, r1, #10813440 @ 0xa50000
+0[0-9a-f]+ <[^>]+> f441 00a5 orr\.w r0, r1, #5406720 @ 0x528000
+0[0-9a-f]+ <[^>]+> f441 1025 orr\.w r0, r1, #2703360 @ 0x294000
+0[0-9a-f]+ <[^>]+> f441 10a5 orr\.w r0, r1, #1351680 @ 0x14a000
+0[0-9a-f]+ <[^>]+> f441 2025 orr\.w r0, r1, #675840 @ 0xa5000
+0[0-9a-f]+ <[^>]+> f441 20a5 orr\.w r0, r1, #337920 @ 0x52800
+0[0-9a-f]+ <[^>]+> f441 3025 orr\.w r0, r1, #168960 @ 0x29400
+0[0-9a-f]+ <[^>]+> f441 30a5 orr\.w r0, r1, #84480 @ 0x14a00
+0[0-9a-f]+ <[^>]+> f441 4025 orr\.w r0, r1, #42240 @ 0xa500
+0[0-9a-f]+ <[^>]+> f441 40a5 orr\.w r0, r1, #21120 @ 0x5280
+0[0-9a-f]+ <[^>]+> f441 5025 orr\.w r0, r1, #10560 @ 0x2940
+0[0-9a-f]+ <[^>]+> f441 50a5 orr\.w r0, r1, #5280 @ 0x14a0
+0[0-9a-f]+ <[^>]+> f441 6025 orr\.w r0, r1, #2640 @ 0xa50
+0[0-9a-f]+ <[^>]+> f441 60a5 orr\.w r0, r1, #1320 @ 0x528
+0[0-9a-f]+ <[^>]+> f441 7025 orr\.w r0, r1, #660 @ 0x294
+0[0-9a-f]+ <[^>]+> f441 70a5 orr\.w r0, r1, #330 @ 0x14a
0[0-9a-f]+ <[^>]+> 3000 adds r0, #0
0[0-9a-f]+ <[^>]+> 1c05 adds r5, r0, #0
0[0-9a-f]+ <[^>]+> 1c28 adds r0, r5, #0
0[0-9a-f]+ <[^>]+> eb00 0800 add\.w r8, r0, r0
0[0-9a-f]+ <[^>]+> 4401 add r1, r0
0[0-9a-f]+ <[^>]+> 4408 add r0, r1
-0[0-9a-f]+ <[^>]+> a000 add r0, pc, #0 ; \(adr r0, [0-9a-f]+ <[^>]+>\)
-0[0-9a-f]+ <[^>]+> a500 add r5, pc, #0 ; \(adr r5, [0-9a-f]+ <[^>]+>\)
-0[0-9a-f]+ <[^>]+> a081 add r0, pc, #516 ; \(adr r0, [0-9a-f]+ <[^>]+>\)
+0[0-9a-f]+ <[^>]+> a000 add r0, pc, #0 @ \(adr r0, [0-9a-f]+ <[^>]+>\)
+0[0-9a-f]+ <[^>]+> a500 add r5, pc, #0 @ \(adr r5, [0-9a-f]+ <[^>]+>\)
+0[0-9a-f]+ <[^>]+> a081 add r0, pc, #516 @ \(adr r0, [0-9a-f]+ <[^>]+>\)
0[0-9a-f]+ <[^>]+> a800 add r0, sp, #0
0[0-9a-f]+ <[^>]+> ad00 add r5, sp, #0
0[0-9a-f]+ <[^>]+> a881 add r0, sp, #516.*
0[0-9a-f]+ <[^>]+> f110 0000 adds\.w r0, r0, #0
0[0-9a-f]+ <[^>]+> f100 0900 add\.w r9, r0, #0
0[0-9a-f]+ <[^>]+> f109 0000 add\.w r0, r9, #0
-0[0-9a-f]+ <[^>]+> f100 0081 add\.w r0, r0, #129 ; 0x81
-0[0-9a-f]+ <[^>]+> f513 3580 adds\.w r5, r3, #65536 ; 0x10000
+0[0-9a-f]+ <[^>]+> f100 0081 add\.w r0, r0, #129 @ 0x81
+0[0-9a-f]+ <[^>]+> f513 3580 adds\.w r5, r3, #65536 @ 0x10000
0[0-9a-f]+ <[^>]+> f10d 0001 add\.w r0, sp, #1
0[0-9a-f]+ <[^>]+> f10d 0900 add\.w r9, sp, #0
0[0-9a-f]+ <[^>]+> f10d 0d04 add\.w sp, sp, #4
0[0-9a-f]+ <[^>]+> b0c1 sub sp, #260.*
0[0-9a-f]+ <[^>]+> ebb8 0800 subs\.w r8, r8, r0
0[0-9a-f]+ <[^>]+> ebb0 0008 subs\.w r0, r0, r8
-0[0-9a-f]+ <[^>]+> f5b0 7082 subs\.w r0, r0, #260 ; 0x104
+0[0-9a-f]+ <[^>]+> f5b0 7082 subs\.w r0, r0, #260 @ 0x104
0[0-9a-f]+ <[^>]+> f1b2 0104 subs\.w r1, r2, #4
-0[0-9a-f]+ <[^>]+> f5b3 3580 subs\.w r5, r3, #65536 ; 0x10000
+0[0-9a-f]+ <[^>]+> f5b3 3580 subs\.w r5, r3, #65536 @ 0x10000
0[0-9a-f]+ <[^>]+> f1ad 0104 sub\.w r1, sp, #4
0[0-9a-f]+ <[^>]+> f1ad 0900 sub\.w r9, sp, #0
0[0-9a-f]+ <[^>]+> f1ad 0d04 sub\.w sp, sp, #4
0[0-9a-f]+ <[^>]+> eb40 0009 adc\.w r0, r0, r9
0[0-9a-f]+ <[^>]+> eb50 0000 adcs\.w r0, r0, r0
0[0-9a-f]+ <[^>]+> eb41 4062 adc\.w r0, r1, r2, asr #17
-0[0-9a-f]+ <[^>]+> f141 0081 adc\.w r0, r1, #129 ; 0x81
+0[0-9a-f]+ <[^>]+> f141 0081 adc\.w r0, r1, #129 @ 0x81
0[0-9a-f]+ <[^>]+> 4000 ands r0, r0
0[0-9a-f]+ <[^>]+> 4005 ands r5, r0
0[0-9a-f]+ <[^>]+> 4028 ands r0, r5
0[0-9a-f]+ <[^>]+> ea00 0009 and\.w r0, r0, r9
0[0-9a-f]+ <[^>]+> ea10 0000 ands\.w r0, r0, r0
0[0-9a-f]+ <[^>]+> ea01 4062 and\.w r0, r1, r2, asr #17
-0[0-9a-f]+ <[^>]+> f001 0081 and\.w r0, r1, #129 ; 0x81
+0[0-9a-f]+ <[^>]+> f001 0081 and\.w r0, r1, #129 @ 0x81
0[0-9a-f]+ <[^>]+> 4380 bics r0, r0
0[0-9a-f]+ <[^>]+> 4385 bics r5, r0
0[0-9a-f]+ <[^>]+> 43a8 bics r0, r5
0[0-9a-f]+ <[^>]+> ea20 0009 bic\.w r0, r0, r9
0[0-9a-f]+ <[^>]+> ea30 0000 bics\.w r0, r0, r0
0[0-9a-f]+ <[^>]+> ea21 4062 bic\.w r0, r1, r2, asr #17
-0[0-9a-f]+ <[^>]+> f021 0081 bic\.w r0, r1, #129 ; 0x81
+0[0-9a-f]+ <[^>]+> f021 0081 bic\.w r0, r1, #129 @ 0x81
0[0-9a-f]+ <[^>]+> 4040 eors r0, r0
0[0-9a-f]+ <[^>]+> 4045 eors r5, r0
0[0-9a-f]+ <[^>]+> 4068 eors r0, r5
0[0-9a-f]+ <[^>]+> ea80 0009 eor\.w r0, r0, r9
0[0-9a-f]+ <[^>]+> ea90 0000 eors\.w r0, r0, r0
0[0-9a-f]+ <[^>]+> ea81 4062 eor\.w r0, r1, r2, asr #17
-0[0-9a-f]+ <[^>]+> f081 0081 eor\.w r0, r1, #129 ; 0x81
+0[0-9a-f]+ <[^>]+> f081 0081 eor\.w r0, r1, #129 @ 0x81
0[0-9a-f]+ <[^>]+> 4300 orrs r0, r0
0[0-9a-f]+ <[^>]+> 4305 orrs r5, r0
0[0-9a-f]+ <[^>]+> 4328 orrs r0, r5
0[0-9a-f]+ <[^>]+> ea40 0009 orr\.w r0, r0, r9
0[0-9a-f]+ <[^>]+> ea50 0000 orrs\.w r0, r0, r0
0[0-9a-f]+ <[^>]+> ea41 4062 orr\.w r0, r1, r2, asr #17
-0[0-9a-f]+ <[^>]+> f041 0081 orr\.w r0, r1, #129 ; 0x81
+0[0-9a-f]+ <[^>]+> f041 0081 orr\.w r0, r1, #129 @ 0x81
0[0-9a-f]+ <[^>]+> ebd0 0000 rsbs r0, r0, r0
0[0-9a-f]+ <[^>]+> ebd5 0500 rsbs r5, r5, r0
0[0-9a-f]+ <[^>]+> ebd0 0005 rsbs r0, r0, r5
0[0-9a-f]+ <[^>]+> ebc0 0009 rsb r0, r0, r9
0[0-9a-f]+ <[^>]+> ebd0 0000 rsbs r0, r0, r0
0[0-9a-f]+ <[^>]+> ebc1 4062 rsb r0, r1, r2, asr #17
-0[0-9a-f]+ <[^>]+> f1c1 0081 rsb r0, r1, #129 ; 0x81
+0[0-9a-f]+ <[^>]+> f1c1 0081 rsb r0, r1, #129 @ 0x81
0[0-9a-f]+ <[^>]+> 4180 sbcs r0, r0
0[0-9a-f]+ <[^>]+> 4185 sbcs r5, r0
0[0-9a-f]+ <[^>]+> 41a8 sbcs r0, r5
0[0-9a-f]+ <[^>]+> eb60 0009 sbc\.w r0, r0, r9
0[0-9a-f]+ <[^>]+> eb70 0000 sbcs\.w r0, r0, r0
0[0-9a-f]+ <[^>]+> eb61 4062 sbc\.w r0, r1, r2, asr #17
-0[0-9a-f]+ <[^>]+> f161 0081 sbc\.w r0, r1, #129 ; 0x81
+0[0-9a-f]+ <[^>]+> f161 0081 sbc\.w r0, r1, #129 @ 0x81
0[0-9a-f]+ <[^>]+> ea70 0000 orns r0, r0, r0
0[0-9a-f]+ <[^>]+> ea75 0500 orns r5, r5, r0
0[0-9a-f]+ <[^>]+> ea70 0005 orns r0, r0, r5
0[0-9a-f]+ <[^>]+> ea60 0009 orn r0, r0, r9
0[0-9a-f]+ <[^>]+> ea70 0000 orns r0, r0, r0
0[0-9a-f]+ <[^>]+> ea61 4062 orn r0, r1, r2, asr #17
-0[0-9a-f]+ <[^>]+> f061 0081 orn r0, r1, #129 ; 0x81
+0[0-9a-f]+ <[^>]+> f061 0081 orn r0, r1, #129 @ 0x81
0[0-9a-f]+ <[^>]+> f36f 0000 bfc r0, #0, #1
0[0-9a-f]+ <[^>]+> f36f 0900 bfc r9, #0, #1
0[0-9a-f]+ <[^>]+> f36f 0900 bfc r9, #0, #1
0[0-9a-f]+ <[^>]+> f815 fd30 pld \[r5, #-48\]!.*
0[0-9a-f]+ <[^>]+> f815 f004 pld \[r5, r4\]
0[0-9a-f]+ <[^>]+> f819 f00c pld \[r9, ip\]
-0[0-9a-f]+ <[^>]+> f89f f006 pld \[pc, #6\] ; 0+5ee <[^>]+>
-0[0-9a-f]+ <[^>]+> f81f f02a pld \[pc, #-42\] ; 0+5c2 <[^>]+>
+0[0-9a-f]+ <[^>]+> f89f f006 pld \[pc, #6\] @ 0+5ee <[^>]+>
+0[0-9a-f]+ <[^>]+> f81f f02a pld \[pc, #-42\] @ 0+5c2 <[^>]+>
0[0-9a-f]+ <[^>]+> bf00 nop
0[0-9a-f]+ <[^>]+> e9d5 2300 ldrd r2, r3, \[r5\]
0[0-9a-f]+ <[^>]+> e9d5 230c ldrd r2, r3, \[r5, #48\].*
0[0-9a-f]+ <[^>]+> e955 230c ldrd r2, r3, \[r5, #-48\].*
-0[0-9a-f]+ <[^>]+> e95f 4504 ldrd r4, r5, \[pc, #-16\] ; 000005f0 <here>
+0[0-9a-f]+ <[^>]+> e95f 4504 ldrd r4, r5, \[pc, #-16\] @ 000005f0 <here>
0[0-9a-f]+ <[^>]+> e9c5 2300 strd r2, r3, \[r5\]
0[0-9a-f]+ <[^>]+> e9c5 230c strd r2, r3, \[r5, #48\].*
0[0-9a-f]+ <[^>]+> e945 230c strd r2, r3, \[r5, #-48\].*
0[0-9a-f]+ <[^>]+> ea10 0f00 tst\.w r0, r0
0[0-9a-f]+ <[^>]+> ea19 0f00 tst\.w r9, r0
0[0-9a-f]+ <[^>]+> ea10 0f09 tst\.w r0, r9
-0[0-9a-f]+ <[^>]+> f010 0f81 tst\.w r0, #129 ; 0x81
-0[0-9a-f]+ <[^>]+> f015 0f81 tst\.w r5, #129 ; 0x81
+0[0-9a-f]+ <[^>]+> f010 0f81 tst\.w r0, #129 @ 0x81
+0[0-9a-f]+ <[^>]+> f015 0f81 tst\.w r5, #129 @ 0x81
0[0-9a-f]+ <[^>]+> ea90 0f00 teq r0, r0
0[0-9a-f]+ <[^>]+> ea90 0f00 teq r0, r0
0[0-9a-f]+ <[^>]+> ea95 0f00 teq r5, r0
0[0-9a-f]+ <[^>]+> ea90 0f00 teq r0, r0
0[0-9a-f]+ <[^>]+> ea99 0f00 teq r9, r0
0[0-9a-f]+ <[^>]+> ea90 0f09 teq r0, r9
-0[0-9a-f]+ <[^>]+> f090 0f81 teq r0, #129 ; 0x81
-0[0-9a-f]+ <[^>]+> f095 0f81 teq r5, #129 ; 0x81
+0[0-9a-f]+ <[^>]+> f090 0f81 teq r0, #129 @ 0x81
+0[0-9a-f]+ <[^>]+> f095 0f81 teq r5, #129 @ 0x81
0[0-9a-f]+ <[^>]+> 4280 cmp r0, r0
0[0-9a-f]+ <[^>]+> 4280 cmp r0, r0
0[0-9a-f]+ <[^>]+> 4285 cmp r5, r0
0[0-9a-f]+ <[^>]+> ebb0 0f00 cmp\.w r0, r0
0[0-9a-f]+ <[^>]+> 4581 cmp r9, r0
0[0-9a-f]+ <[^>]+> ebb0 0f09 cmp\.w r0, r9
-0[0-9a-f]+ <[^>]+> f1b0 0f81 cmp\.w r0, #129 ; 0x81
-0[0-9a-f]+ <[^>]+> f1b5 0f81 cmp\.w r5, #129 ; 0x81
+0[0-9a-f]+ <[^>]+> f1b0 0f81 cmp\.w r0, #129 @ 0x81
+0[0-9a-f]+ <[^>]+> f1b5 0f81 cmp\.w r5, #129 @ 0x81
0[0-9a-f]+ <[^>]+> 42c0 cmn r0, r0
0[0-9a-f]+ <[^>]+> 42c0 cmn r0, r0
0[0-9a-f]+ <[^>]+> 42c5 cmn r5, r0
0[0-9a-f]+ <[^>]+> eb10 0f00 cmn\.w r0, r0
0[0-9a-f]+ <[^>]+> eb19 0f00 cmn\.w r9, r0
0[0-9a-f]+ <[^>]+> eb10 0f09 cmn\.w r0, r9
-0[0-9a-f]+ <[^>]+> f110 0f81 cmn\.w r0, #129 ; 0x81
-0[0-9a-f]+ <[^>]+> f115 0f81 cmn\.w r5, #129 ; 0x81
+0[0-9a-f]+ <[^>]+> f110 0f81 cmn\.w r0, #129 @ 0x81
+0[0-9a-f]+ <[^>]+> f115 0f81 cmn\.w r5, #129 @ 0x81
0[0-9a-f]+ <[^>]+> 0000 movs r0, r0
0[0-9a-f]+ <[^>]+> 4600 mov r0, r0
0[0-9a-f]+ <[^>]+> 0005 movs r5, r0
0[0-9a-f]+ <[^>]+> ea4f 0000 mov\.w r0, r0
0[0-9a-f]+ <[^>]+> ea5f 0900 movs\.w r9, r0
0[0-9a-f]+ <[^>]+> ea5f 0009 movs\.w r0, r9
-0[0-9a-f]+ <[^>]+> f04f 0081 mov\.w r0, #129 ; 0x81
-0[0-9a-f]+ <[^>]+> f04f 0581 mov\.w r5, #129 ; 0x81
+0[0-9a-f]+ <[^>]+> f04f 0081 mov\.w r0, #129 @ 0x81
+0[0-9a-f]+ <[^>]+> f04f 0581 mov\.w r5, #129 @ 0x81
0[0-9a-f]+ <[^>]+> 43c0 mvns r0, r0
0[0-9a-f]+ <[^>]+> ea6f 0000 mvn\.w r0, r0
0[0-9a-f]+ <[^>]+> 43c5 mvns r5, r0
0[0-9a-f]+ <[^>]+> ea6f 0000 mvn\.w r0, r0
0[0-9a-f]+ <[^>]+> ea7f 0900 mvns\.w r9, r0
0[0-9a-f]+ <[^>]+> ea7f 0009 mvns\.w r0, r9
-0[0-9a-f]+ <[^>]+> f06f 0081 mvn\.w r0, #129 ; 0x81
-0[0-9a-f]+ <[^>]+> f06f 0581 mvn\.w r5, #129 ; 0x81
+0[0-9a-f]+ <[^>]+> f06f 0081 mvn\.w r0, #129 @ 0x81
+0[0-9a-f]+ <[^>]+> f06f 0581 mvn\.w r5, #129 @ 0x81
0[0-9a-f]+ <[^>]+> f240 0000 movw r0, #0
0[0-9a-f]+ <[^>]+> f2c0 0000 movt r0, #0
0[0-9a-f]+ <[^>]+> f240 0900 movw r9, #0
-0[0-9a-f]+ <[^>]+> f249 0000 movw r0, #36864 ; 0x9000
-0[0-9a-f]+ <[^>]+> f640 0000 movw r0, #2048 ; 0x800
-0[0-9a-f]+ <[^>]+> f240 5000 movw r0, #1280 ; 0x500
-0[0-9a-f]+ <[^>]+> f240 0081 movw r0, #129 ; 0x81
-0[0-9a-f]+ <[^>]+> f64f 70ff movw r0, #65535 ; 0xffff
+0[0-9a-f]+ <[^>]+> f249 0000 movw r0, #36864 @ 0x9000
+0[0-9a-f]+ <[^>]+> f640 0000 movw r0, #2048 @ 0x800
+0[0-9a-f]+ <[^>]+> f240 5000 movw r0, #1280 @ 0x500
+0[0-9a-f]+ <[^>]+> f240 0081 movw r0, #129 @ 0x81
+0[0-9a-f]+ <[^>]+> f64f 70ff movw r0, #65535 @ 0xffff
0[0-9a-f]+ <[^>]+> f3ef 8000 mrs r0, CPSR
0[0-9a-f]+ <[^>]+> f3ff 8000 mrs r0, SPSR
0[0-9a-f]+ <[^>]+> f3ef 8900 mrs r9, CPSR
0[0-9a-f]+ <[^>]+> fa52 f183 uxtab r1, r2, r3
0[0-9a-f]+ <[^>]+> fa32 f183 uxtab16 r1, r2, r3
0[0-9a-f]+ <[^>]+> fa12 f183 uxtah r1, r2, r3
-0[0-9a-f]+ <[^>]+> f89f 12aa ldrb\.w r1, \[pc, #682\] ; 0+e86 <[^>]+>
-0[0-9a-f]+ <[^>]+> f89f 1155 ldrb\.w r1, \[pc, #341\] ; 0+d35 <[^>]+>
-0[0-9a-f]+ <[^>]+> f81f 12aa ldrb\.w r1, \[pc, #-682\] ; 0+93a <[^>]+>
-0[0-9a-f]+ <[^>]+> f81f 1155 ldrb\.w r1, \[pc, #-341\] ; 0+a93 <[^>]+>
-0[0-9a-f]+ <[^>]+> f99f 12aa ldrsb\.w r1, \[pc, #682\] ; 0+e96 <[^>]+>
-0[0-9a-f]+ <[^>]+> f99f 1155 ldrsb\.w r1, \[pc, #341\] ; 0+d45 <[^>]+>
-0[0-9a-f]+ <[^>]+> f91f 12aa ldrsb\.w r1, \[pc, #-682\] ; 0+94a <[^>]+>
-0[0-9a-f]+ <[^>]+> f91f 1155 ldrsb\.w r1, \[pc, #-341\] ; 0+aa3 <[^>]+>
-0[0-9a-f]+ <[^>]+> f8bf 12aa ldrh\.w r1, \[pc, #682\] ; 0+ea6 <[^>]+>
-0[0-9a-f]+ <[^>]+> f8bf 1155 ldrh\.w r1, \[pc, #341\] ; 0+d55 <[^>]+>
-0[0-9a-f]+ <[^>]+> f83f 12aa ldrh\.w r1, \[pc, #-682\] ; 0+95a <[^>]+>
-0[0-9a-f]+ <[^>]+> f83f 1155 ldrh\.w r1, \[pc, #-341\] ; 0+ab3 <[^>]+>
-0[0-9a-f]+ <[^>]+> f9bf 12aa ldrsh\.w r1, \[pc, #682\] ; 0+eb6 <[^>]+>
-0[0-9a-f]+ <[^>]+> f9bf 1155 ldrsh\.w r1, \[pc, #341\] ; 0+d65 <[^>]+>
-0[0-9a-f]+ <[^>]+> f93f 12aa ldrsh\.w r1, \[pc, #-682\] ; 0+96a <[^>]+>
-0[0-9a-f]+ <[^>]+> f93f 1155 ldrsh\.w r1, \[pc, #-341\] ; 0+ac3 <[^>]+>
-0[0-9a-f]+ <[^>]+> f8df 12aa ldr\.w r1, \[pc, #682\] ; 0+ec6 <[^>]+>
-0[0-9a-f]+ <[^>]+> f8df 1155 ldr\.w r1, \[pc, #341\] ; 0+d75 <[^>]+>
-0[0-9a-f]+ <[^>]+> f85f 12aa ldr\.w r1, \[pc, #-682\] ; 0+97a <[^>]+>
-0[0-9a-f]+ <[^>]+> f85f 1155 ldr\.w r1, \[pc, #-341\] ; 0+ad3 <[^>]+>
+0[0-9a-f]+ <[^>]+> f89f 12aa ldrb\.w r1, \[pc, #682\] @ 0+e86 <[^>]+>
+0[0-9a-f]+ <[^>]+> f89f 1155 ldrb\.w r1, \[pc, #341\] @ 0+d35 <[^>]+>
+0[0-9a-f]+ <[^>]+> f81f 12aa ldrb\.w r1, \[pc, #-682\] @ 0+93a <[^>]+>
+0[0-9a-f]+ <[^>]+> f81f 1155 ldrb\.w r1, \[pc, #-341\] @ 0+a93 <[^>]+>
+0[0-9a-f]+ <[^>]+> f99f 12aa ldrsb\.w r1, \[pc, #682\] @ 0+e96 <[^>]+>
+0[0-9a-f]+ <[^>]+> f99f 1155 ldrsb\.w r1, \[pc, #341\] @ 0+d45 <[^>]+>
+0[0-9a-f]+ <[^>]+> f91f 12aa ldrsb\.w r1, \[pc, #-682\] @ 0+94a <[^>]+>
+0[0-9a-f]+ <[^>]+> f91f 1155 ldrsb\.w r1, \[pc, #-341\] @ 0+aa3 <[^>]+>
+0[0-9a-f]+ <[^>]+> f8bf 12aa ldrh\.w r1, \[pc, #682\] @ 0+ea6 <[^>]+>
+0[0-9a-f]+ <[^>]+> f8bf 1155 ldrh\.w r1, \[pc, #341\] @ 0+d55 <[^>]+>
+0[0-9a-f]+ <[^>]+> f83f 12aa ldrh\.w r1, \[pc, #-682\] @ 0+95a <[^>]+>
+0[0-9a-f]+ <[^>]+> f83f 1155 ldrh\.w r1, \[pc, #-341\] @ 0+ab3 <[^>]+>
+0[0-9a-f]+ <[^>]+> f9bf 12aa ldrsh\.w r1, \[pc, #682\] @ 0+eb6 <[^>]+>
+0[0-9a-f]+ <[^>]+> f9bf 1155 ldrsh\.w r1, \[pc, #341\] @ 0+d65 <[^>]+>
+0[0-9a-f]+ <[^>]+> f93f 12aa ldrsh\.w r1, \[pc, #-682\] @ 0+96a <[^>]+>
+0[0-9a-f]+ <[^>]+> f93f 1155 ldrsh\.w r1, \[pc, #-341\] @ 0+ac3 <[^>]+>
+0[0-9a-f]+ <[^>]+> f8df 12aa ldr\.w r1, \[pc, #682\] @ 0+ec6 <[^>]+>
+0[0-9a-f]+ <[^>]+> f8df 1155 ldr\.w r1, \[pc, #341\] @ 0+d75 <[^>]+>
+0[0-9a-f]+ <[^>]+> f85f 12aa ldr\.w r1, \[pc, #-682\] @ 0+97a <[^>]+>
+0[0-9a-f]+ <[^>]+> f85f 1155 ldr\.w r1, \[pc, #-341\] @ 0+ad3 <[^>]+>
0[0-9a-f]+ <[^>]+> f200 0900 addw r9, r0, #0
-0[0-9a-f]+ <[^>]+> f60f 76ff addw r6, pc, #4095 ; 0xfff
-0[0-9a-f]+ <[^>]+> f6a9 2685 subw r6, r9, #2693 ; 0xa85
-0[0-9a-f]+ <[^>]+> f2a9 567a subw r6, r9, #1402 ; 0x57a
+0[0-9a-f]+ <[^>]+> f60f 76ff addw r6, pc, #4095 @ 0xfff
+0[0-9a-f]+ <[^>]+> f6a9 2685 subw r6, r9, #2693 @ 0xa85
+0[0-9a-f]+ <[^>]+> f2a9 567a subw r6, r9, #1402 @ 0x57a
0[0-9a-f]+ <[^>]+> e8df f006 tbb \[pc, r6\]
0[0-9a-f]+ <[^>]+> e8d0 f009 tbb \[r0, r9\]
0[0-9a-f]+ <[^>]+> e8df f017 tbh \[pc, r7, lsl #1\]
0+012 <[^>]*> b251 * sxtb r1, r2
0+014 <[^>]*> b2a3 * uxth r3, r4
0+016 <[^>]*> b2f5 * uxtb r5, r6
-0+018 <[^>]*> 46c0 * nop[ ]+; \(mov r8, r8\)
-0+01a <[^>]*> 46c0 * nop[ ]+; \(mov r8, r8\)
-0+01c <[^>]*> 46c0 * nop[ ]+; \(mov r8, r8\)
-0+01e <[^>]*> 46c0 * nop[ ]+; \(mov r8, r8\)
+0+018 <[^>]*> 46c0 * nop[ ]+@ \(mov r8, r8\)
+0+01a <[^>]*> 46c0 * nop[ ]+@ \(mov r8, r8\)
+0+01c <[^>]*> 46c0 * nop[ ]+@ \(mov r8, r8\)
+0+01e <[^>]*> 46c0 * nop[ ]+@ \(mov r8, r8\)
0+002 <[^>]*> bf20 * wfe
0+004 <[^>]*> bf30 * wfi
0+006 <[^>]*> bf40 * sev
-0+008 <[^>]*> 46c0 * nop[ \t]+; \(mov r8, r8\)
-0+00a <[^>]*> 46c0 * nop[ \t]+; \(mov r8, r8\)
-0+00c <[^>]*> 46c0 * nop[ \t]+; \(mov r8, r8\)
-0+00e <[^>]*> 46c0 * nop[ \t]+; \(mov r8, r8\)
+0+008 <[^>]*> 46c0 * nop[ \t]+@ \(mov r8, r8\)
+0+00a <[^>]*> 46c0 * nop[ \t]+@ \(mov r8, r8\)
+0+00c <[^>]*> 46c0 * nop[ \t]+@ \(mov r8, r8\)
+0+00e <[^>]*> 46c0 * nop[ \t]+@ \(mov r8, r8\)
Disassembly of section .text:
0+00 <arm_fn>:
- 0: e1a00000 nop ; .*
+ 0: e1a00000 nop @ .*
0: R_ARM_TLS_DESCSEQ af
- 4: e59f0014 ldr r0, \[pc, #20\] ; 20 .*
+ 4: e59f0014 ldr r0, \[pc, #20\] @ 20 .*
8: fa000000 blx 8 <ae.*>
8: R_ARM_TLS_CALL ae
- c: e1a00000 nop ; .*
+ c: e1a00000 nop @ .*
0+10 <.arm_pool>:
10: 00000008 .word 0x00000008
10: R_ARM_TLS_GD32 aa
20: 00000018 .word 0x00000018
20: R_ARM_TLS_GOTDESC ae
0+24 <thumb_fn>:
- 24: 46c0 nop ; .*
- 26: 46c0 nop ; .*
+ 24: 46c0 nop @ .*
+ 26: 46c0 nop @ .*
26: R_ARM_THM_TLS_DESCSEQ tf
- 28: 4805 ldr r0, \[pc, #20\] ; \(40 .*\)
+ 28: 4805 ldr r0, \[pc, #20\] @ \(40 .*\)
2a: f000 e800 blx 4 <te.*>
2a: R_ARM_THM_TLS_CALL te
- 2e: 46c0 nop ; .*
+ 2e: 46c0 nop @ .*
30: 00000002 .word 0x00000002
30: R_ARM_TLS_GD32 ta
34: 00000006 .word 0x00000006
Disassembly of section .text:
00+0 <arm_fn>:
- 0: e1a00000 nop \; \(mov r0, r0\)
+ 0: e1a00000 nop \@ \(mov r0, r0\)
0: R_ARM_TLS_DESCSEQ af
- 4: e59f0014 ldr r0, \[pc, \#20\] ; 20 <\.arm_pool\+0x10>
+ 4: e59f0014 ldr r0, \[pc, \#20\] @ 20 <\.arm_pool\+0x10>
8: fa000000 blx 8 <ae\+0x8>
8: R_ARM_TLS_CALL ae
# ??? The addend is appearing in both the RELA field and the
# contents. Shouldn't it be just one? bfd_install_relocation
# appears to write the addend into the contents unconditionally,
# yet somehow this does not happen for the majority of relocations.
- c: e1a00000 nop \; \(mov r0, r0\)
+ c: e1a00000 nop \@ \(mov r0, r0\)
00000010 <.arm_pool>:
10: 00000008 .word 0x00000008
10: R_ARM_TLS_GD32 aa\+0x8
Disassembly of section \.text:
[^<]*<arm> e7f000f0 udf #0
-[^<]*<arm\+0x4> e7fabcfd udf #43981 ; 0xabcd
-[^<]*<thumb> deab udf #171 ; 0xab
-[^<]*<thumb\+0x2> decd udf #205 ; 0xcd
+[^<]*<arm\+0x4> e7fabcfd udf #43981 @ 0xabcd
+[^<]*<thumb> deab udf #171 @ 0xab
+[^<]*<thumb\+0x2> decd udf #205 @ 0xcd
[^<]*<thumb\+0x4> de00 udf #0
[^<]*<thumb\+0x6> bf00 nop
[^<]*<thumb\+0x8> f7f0 a000 udf.w #0
-[^<]*<thumb\+0xc> f7f1 a234 udf.w #4660 ; 0x1234
-[^<]*<thumb\+0x10> f7fc acdd udf.w #52445 ; 0xccdd
+[^<]*<thumb\+0xc> f7f1 a234 udf.w #4660 @ 0x1234
+[^<]*<thumb\+0x10> f7fc acdd udf.w #52445 @ 0xccdd
[^<]*<thumb\+0x14> bf08 it eq
[^<]*<thumb\+0x16> de12 udfeq #18
-[^<]*<thumb\+0x18> de23 udf #35 ; 0x23
-[^<]*<thumb\+0x1a> de34 udf #52 ; 0x34
-[^<]*<thumb\+0x1c> de56 udf #86 ; 0x56
+[^<]*<thumb\+0x18> de23 udf #35 @ 0x23
+[^<]*<thumb\+0x1a> de34 udf #52 @ 0x34
+[^<]*<thumb\+0x1c> de56 udf #86 @ 0x56
[^<]*<thumb\+0x1e> bf18 it ne
-[^<]*<thumb\+0x20> f7f1 a234 udfne.w #4660 ; 0x1234
-[^<]*<thumb\+0x24> f7f2 a345 udf.w #9029 ; 0x2345
-[^<]*<thumb\+0x28> f7f3 a456 udf.w #13398 ; 0x3456
-[^<]*<thumb\+0x2c> f7f5 a678 udf.w #22136 ; 0x5678
+[^<]*<thumb\+0x20> f7f1 a234 udfne.w #4660 @ 0x1234
+[^<]*<thumb\+0x24> f7f2 a345 udf.w #9029 @ 0x2345
+[^<]*<thumb\+0x28> f7f3 a456 udf.w #13398 @ 0x3456
+[^<]*<thumb\+0x2c> f7f5 a678 udf.w #22136 @ 0x5678
0+0fc <[^>]+> [^<]+<UNPREDICTABLE>
0+100 <[^>]+> [^<]+<UNPREDICTABLE>
0+104 <[^>]+> [^<]+<UNPREDICTABLE>
-0+108 <[^>]+> e1a00000[ ]+nop[ ]+; \(mov r0, r0\)
+0+108 <[^>]+> e1a00000[ ]+nop[ ]+@ \(mov r0, r0\)
#pass
.*: +file format .*arm.*
Disassembly of section .text:
-0[0-9a-f]+ <[^>]+> 4ef2da06 vmovmi.f32 s27, #38 ; 0x41300000 11.0
-0[0-9a-f]+ <[^>]+> 4ef2da06 vmovmi.f32 s27, #38 ; 0x41300000 11.0
-0[0-9a-f]+ <[^>]+> 4ef7da00 vmovmi.f32 s27, #112 ; 0x3f800000 1.0
-0[0-9a-f]+ <[^>]+> 4ef7da00 vmovmi.f32 s27, #112 ; 0x3f800000 1.0
-0[0-9a-f]+ <[^>]+> cebb1b04 vmovgt.f64 d1, #180 ; 0xc1a00000 -20.0
-0[0-9a-f]+ <[^>]+> ceb81b00 vmovgt.f64 d1, #128 ; 0xc0000000 -2.0
-0[0-9a-f]+ <[^>]+> eef0aa00 vmov.f32 s21, #0 ; 0x40000000 2.0
-0[0-9a-f]+ <[^>]+> eef97a07 vmov.f32 s15, #151 ; 0xc0b80000 -5.750
-0[0-9a-f]+ <[^>]+> eefc4a05 vmov.f32 s9, #197 ; 0xbe280000 -0.1640625
+0[0-9a-f]+ <[^>]+> 4ef2da06 vmovmi.f32 s27, #38 @ 0x41300000 11.0
+0[0-9a-f]+ <[^>]+> 4ef2da06 vmovmi.f32 s27, #38 @ 0x41300000 11.0
+0[0-9a-f]+ <[^>]+> 4ef7da00 vmovmi.f32 s27, #112 @ 0x3f800000 1.0
+0[0-9a-f]+ <[^>]+> 4ef7da00 vmovmi.f32 s27, #112 @ 0x3f800000 1.0
+0[0-9a-f]+ <[^>]+> cebb1b04 vmovgt.f64 d1, #180 @ 0xc1a00000 -20.0
+0[0-9a-f]+ <[^>]+> ceb81b00 vmovgt.f64 d1, #128 @ 0xc0000000 -2.0
+0[0-9a-f]+ <[^>]+> eef0aa00 vmov.f32 s21, #0 @ 0x40000000 2.0
+0[0-9a-f]+ <[^>]+> eef97a07 vmov.f32 s15, #151 @ 0xc0b80000 -5.750
+0[0-9a-f]+ <[^>]+> eefc4a05 vmov.f32 s9, #197 @ 0xbe280000 -0.1640625
0[0-9a-f]+ <[^>]+> ec410b10 vmov d0, r0, r1
0[0-9a-f]+ <[^>]+> ec510b10 vmov r0, r1, d0
0[0-9a-f]+ <[^>]+> ec510b10 vmov r0, r1, d0
-0[0-9a-f]+ <[^>]+> ec900b09 fldmiax r0, {d0-d3}( ;@ Deprecated|)
-0[0-9a-f]+ <[^>]+> ed300b09 fldmdbx r0!, {d0-d3}( ;@ Deprecated|)
-0[0-9a-f]+ <[^>]+> ec800b09 fstmiax r0, {d0-d3}( ;@ Deprecated|)
-0[0-9a-f]+ <[^>]+> ed200b09 fstmdbx r0!, {d0-d3}( ;@ Deprecated|)
+0[0-9a-f]+ <[^>]+> ec900b09 fldmiax r0, {d0-d3}( @ Deprecated|)
+0[0-9a-f]+ <[^>]+> ed300b09 fldmdbx r0!, {d0-d3}( @ Deprecated|)
+0[0-9a-f]+ <[^>]+> ec800b09 fstmiax r0, {d0-d3}( @ Deprecated|)
+0[0-9a-f]+ <[^>]+> ed200b09 fstmdbx r0!, {d0-d3}( @ Deprecated|)
0[0-9a-f]+ <[^>]+> ed900b00 vldr d0, \[r0\]
0[0-9a-f]+ <[^>]+> ed900b00 vldr d0, \[r0\]
0[0-9a-f]+ <[^>]+> ed800b00 vstr d0, \[r0\]
0+2c8 <[^>]*> 0e1f7b10 vmoveq\.32 r7, d15\[0\]
0+2cc <[^>]*> 0e21fb10 vmoveq\.32 d1\[1\], pc
0+2d0 <[^>]*> 0e0f1b10 vmoveq\.32 d15\[0\], r1
-0+2d4 <[^>]*> e1a00000 ? nop[ ]+; \(mov r0, r0\)
-0+2d8 <[^>]*> e1a00000 ? nop[ ]+; \(mov r0, r0\)
-0+2dc <[^>]*> e1a00000 ? nop[ ]+; \(mov r0, r0\)
+0+2d4 <[^>]*> e1a00000 ? nop[ ]+@ \(mov r0, r0\)
+0+2d8 <[^>]*> e1a00000 ? nop[ ]+@ \(mov r0, r0\)
+0+2dc <[^>]*> e1a00000 ? nop[ ]+@ \(mov r0, r0\)
0+05c <[^>]*> ecb00a01 (vldmia|fldmias) r0!, {s0}
0+060 <[^>]*> ed300a01 (vldmdb|fldmdbs) r0!, {s0}
0+064 <[^>]*> ed300a01 (vldmdb|fldmdbs) r0!, {s0}
-0+068 <[^>]*> ec900b03 fldmiax r0, {d0}( ;@ Deprecated|)
-0+06c <[^>]*> ec900b03 fldmiax r0, {d0}( ;@ Deprecated|)
-0+070 <[^>]*> ecb00b03 fldmiax r0!, {d0}( ;@ Deprecated|)
-0+074 <[^>]*> ecb00b03 fldmiax r0!, {d0}( ;@ Deprecated|)
-0+078 <[^>]*> ed300b03 fldmdbx r0!, {d0}( ;@ Deprecated|)
-0+07c <[^>]*> ed300b03 fldmdbx r0!, {d0}( ;@ Deprecated|)
+0+068 <[^>]*> ec900b03 fldmiax r0, {d0}( @ Deprecated|)
+0+06c <[^>]*> ec900b03 fldmiax r0, {d0}( @ Deprecated|)
+0+070 <[^>]*> ecb00b03 fldmiax r0!, {d0}( @ Deprecated|)
+0+074 <[^>]*> ecb00b03 fldmiax r0!, {d0}( @ Deprecated|)
+0+078 <[^>]*> ed300b03 fldmdbx r0!, {d0}( @ Deprecated|)
+0+07c <[^>]*> ed300b03 fldmdbx r0!, {d0}( @ Deprecated|)
0+080 <[^>]*> ec800a01 (vstmia|fstmias) r0, {s0}
0+084 <[^>]*> ec800a01 (vstmia|fstmias) r0, {s0}
0+088 <[^>]*> eca00a01 (vstmia|fstmias) r0!, {s0}
0+08c <[^>]*> eca00a01 (vstmia|fstmias) r0!, {s0}
0+090 <[^>]*> ed200a01 (vstmdb|fstmdbs) r0!, {s0}
0+094 <[^>]*> ed200a01 (vstmdb|fstmdbs) r0!, {s0}
-0+098 <[^>]*> ec800b03 fstmiax r0, {d0}( ;@ Deprecated|)
-0+09c <[^>]*> ec800b03 fstmiax r0, {d0}( ;@ Deprecated|)
-0+0a0 <[^>]*> eca00b03 fstmiax r0!, {d0}( ;@ Deprecated|)
-0+0a4 <[^>]*> eca00b03 fstmiax r0!, {d0}( ;@ Deprecated|)
-0+0a8 <[^>]*> ed200b03 fstmdbx r0!, {d0}( ;@ Deprecated|)
-0+0ac <[^>]*> ed200b03 fstmdbx r0!, {d0}( ;@ Deprecated|)
+0+098 <[^>]*> ec800b03 fstmiax r0, {d0}( @ Deprecated|)
+0+09c <[^>]*> ec800b03 fstmiax r0, {d0}( @ Deprecated|)
+0+0a0 <[^>]*> eca00b03 fstmiax r0!, {d0}( @ Deprecated|)
+0+0a4 <[^>]*> eca00b03 fstmiax r0!, {d0}( @ Deprecated|)
+0+0a8 <[^>]*> ed200b03 fstmdbx r0!, {d0}( @ Deprecated|)
+0+0ac <[^>]*> ed200b03 fstmdbx r0!, {d0}( @ Deprecated|)
0+0b0 <[^>]*> eeb80ac0 (vcvt\.f32\.s32|fsitos) s0, s0
0+0b4 <[^>]*> eeb80a40 (vcvt\.f32\.u32|fuitos) s0, s0
0+0b8 <[^>]*> eebd0a40 (vcvtr\.s32\.f32|ftosis) s0, s0
0+210 <[^>]*> ec90fa02 (vldmia|fldmias) r0, {s30-s31}
0+214 <[^>]*> ec910a01 (vldmia|fldmias) r1, {s0}
0+218 <[^>]*> ec9e0a01 (vldmia|fldmias) lr, {s0}
-0+21c <[^>]*> ec801b03 fstmiax r0, {d1}( ;@ Deprecated|)
-0+220 <[^>]*> ec802b03 fstmiax r0, {d2}( ;@ Deprecated|)
-0+224 <[^>]*> ec80fb03 fstmiax r0, {d15}( ;@ Deprecated|)
-0+228 <[^>]*> ec800b05 fstmiax r0, {d0-d1}( ;@ Deprecated|)
-0+22c <[^>]*> ec800b07 fstmiax r0, {d0-d2}( ;@ Deprecated|)
-0+230 <[^>]*> ec800b21 fstmiax r0, {d0-d15}( ;@ Deprecated|)
-0+234 <[^>]*> ec801b1f fstmiax r0, {d1-d15}( ;@ Deprecated|)
-0+238 <[^>]*> ec802b1d fstmiax r0, {d2-d15}( ;@ Deprecated|)
-0+23c <[^>]*> ec80eb05 fstmiax r0, {d14-d15}( ;@ Deprecated|)
-0+240 <[^>]*> ec810b03 fstmiax r1, {d0}( ;@ Deprecated|)
-0+244 <[^>]*> ec8e0b03 fstmiax lr, {d0}( ;@ Deprecated|)
+0+21c <[^>]*> ec801b03 fstmiax r0, {d1}( @ Deprecated|)
+0+220 <[^>]*> ec802b03 fstmiax r0, {d2}( @ Deprecated|)
+0+224 <[^>]*> ec80fb03 fstmiax r0, {d15}( @ Deprecated|)
+0+228 <[^>]*> ec800b05 fstmiax r0, {d0-d1}( @ Deprecated|)
+0+22c <[^>]*> ec800b07 fstmiax r0, {d0-d2}( @ Deprecated|)
+0+230 <[^>]*> ec800b21 fstmiax r0, {d0-d15}( @ Deprecated|)
+0+234 <[^>]*> ec801b1f fstmiax r0, {d1-d15}( @ Deprecated|)
+0+238 <[^>]*> ec802b1d fstmiax r0, {d2-d15}( @ Deprecated|)
+0+23c <[^>]*> ec80eb05 fstmiax r0, {d14-d15}( @ Deprecated|)
+0+240 <[^>]*> ec810b03 fstmiax r1, {d0}( @ Deprecated|)
+0+244 <[^>]*> ec8e0b03 fstmiax lr, {d0}( @ Deprecated|)
0+248 <[^>]*> eeb50a40 (vcmp\.f32 s0, #0.0|fcmpzs s0)
0+24c <[^>]*> eef50a40 (vcmp\.f32 s1, #0.0|fcmpzs s1)
0+250 <[^>]*> eeb51a40 (vcmp\.f32 s2, #0.0|fcmpzs s2)
0+324 <[^>]*> 0cf42a01 (vldmiaeq|fldmiaseq) r4!, {s5}
0+328 <[^>]*> 0d352a01 (vldmdbeq|fldmdbseq) r5!, {s4}
0+32c <[^>]*> 0d761a01 (vldmdbeq|fldmdbseq) r6!, {s3}
-0+330 <[^>]*> 0c971b03 fldmiaxeq r7, {d1}( ;@ Deprecated|)
-0+334 <[^>]*> 0c982b03 fldmiaxeq r8, {d2}( ;@ Deprecated|)
-0+338 <[^>]*> 0cb93b03 fldmiaxeq r9!, {d3}( ;@ Deprecated|)
-0+33c <[^>]*> 0cba4b03 fldmiaxeq sl!, {d4}( ;@ Deprecated|)
-0+340 <[^>]*> 0d3b5b03 fldmdbxeq fp!, {d5}( ;@ Deprecated|)
-0+344 <[^>]*> 0d3c6b03 fldmdbxeq ip!, {d6}( ;@ Deprecated|)
+0+330 <[^>]*> 0c971b03 fldmiaxeq r7, {d1}( @ Deprecated|)
+0+334 <[^>]*> 0c982b03 fldmiaxeq r8, {d2}( @ Deprecated|)
+0+338 <[^>]*> 0cb93b03 fldmiaxeq r9!, {d3}( @ Deprecated|)
+0+33c <[^>]*> 0cba4b03 fldmiaxeq sl!, {d4}( @ Deprecated|)
+0+340 <[^>]*> 0d3b5b03 fldmdbxeq fp!, {d5}( @ Deprecated|)
+0+344 <[^>]*> 0d3c6b03 fldmdbxeq ip!, {d6}( @ Deprecated|)
0+348 <[^>]*> 0c8d1a01 (vstmiaeq|fstmiaseq) sp, {s2}
0+34c <[^>]*> 0cce0a01 (vstmiaeq|fstmiaseq) lr, {s1}
0+350 <[^>]*> 0ce1fa01 (vstmiaeq|fstmiaseq) r1!, {s31}
0+354 <[^>]*> 0ca2fa01 (vstmiaeq|fstmiaseq) r2!, {s30}
0+358 <[^>]*> 0d63ea01 (vstmdbeq|fstmdbseq) r3!, {s29}
0+35c <[^>]*> 0d24ea01 (vstmdbeq|fstmdbseq) r4!, {s28}
-0+360 <[^>]*> 0c857b03 fstmiaxeq r5, {d7}( ;@ Deprecated|)
-0+364 <[^>]*> 0c868b03 fstmiaxeq r6, {d8}( ;@ Deprecated|)
-0+368 <[^>]*> 0ca79b03 fstmiaxeq r7!, {d9}( ;@ Deprecated|)
-0+36c <[^>]*> 0ca8ab03 fstmiaxeq r8!, {d10}( ;@ Deprecated|)
-0+370 <[^>]*> 0d29bb03 fstmdbxeq r9!, {d11}( ;@ Deprecated|)
-0+374 <[^>]*> 0d2acb03 fstmdbxeq sl!, {d12}( ;@ Deprecated|)
+0+360 <[^>]*> 0c857b03 fstmiaxeq r5, {d7}( @ Deprecated|)
+0+364 <[^>]*> 0c868b03 fstmiaxeq r6, {d8}( @ Deprecated|)
+0+368 <[^>]*> 0ca79b03 fstmiaxeq r7!, {d9}( @ Deprecated|)
+0+36c <[^>]*> 0ca8ab03 fstmiaxeq r8!, {d10}( @ Deprecated|)
+0+370 <[^>]*> 0d29bb03 fstmdbxeq r9!, {d11}( @ Deprecated|)
+0+374 <[^>]*> 0d2acb03 fstmdbxeq sl!, {d12}( @ Deprecated|)
0+378 <[^>]*> 0ef8dac3 (vcvteq\.f32\.s32|fsitoseq) s27, s6
0+37c <[^>]*> 0efdca62 (vcvtreq\.s32\.f32|ftosiseq) s25, s5
0+380 <[^>]*> 0efdbac2 (vcvteq\.s32\.f32|ftosizseq) s23, s4
0+460 <[^>]*> eef97a10 vmrs r7, fpinst @ Impl def
0+464 <[^>]*> eefa8a10 vmrs r8, fpinst2 @ Impl def
0+468 <[^>]*> eeff9a10 vmrs r9, (c15|<impl def 0xf>|fpcxt_s)
-0+46c <[^>]*> e1a00000 nop ; \(mov r0, r0\)
-0+470 <[^>]*> e1a00000 nop ; \(mov r0, r0\)
-0+474 <[^>]*> e1a00000 nop ; \(mov r0, r0\)
+0+46c <[^>]*> e1a00000 nop @ \(mov r0, r0\)
+0+470 <[^>]*> e1a00000 nop @ \(mov r0, r0\)
+0+474 <[^>]*> e1a00000 nop @ \(mov r0, r0\)
0+05c <[^>]*> ecb0 0a01 (vldmia|fldmias) r0!, {s0}
0+060 <[^>]*> ed30 0a01 (vldmdb|fldmdbs) r0!, {s0}
0+064 <[^>]*> ed30 0a01 (vldmdb|fldmdbs) r0!, {s0}
-0+068 <[^>]*> ec90 0b03 fldmiax r0, {d0}( ;@ Deprecated|)
-0+06c <[^>]*> ec90 0b03 fldmiax r0, {d0}( ;@ Deprecated|)
-0+070 <[^>]*> ecb0 0b03 fldmiax r0!, {d0}( ;@ Deprecated|)
-0+074 <[^>]*> ecb0 0b03 fldmiax r0!, {d0}( ;@ Deprecated|)
-0+078 <[^>]*> ed30 0b03 fldmdbx r0!, {d0}( ;@ Deprecated|)
-0+07c <[^>]*> ed30 0b03 fldmdbx r0!, {d0}( ;@ Deprecated|)
+0+068 <[^>]*> ec90 0b03 fldmiax r0, {d0}( @ Deprecated|)
+0+06c <[^>]*> ec90 0b03 fldmiax r0, {d0}( @ Deprecated|)
+0+070 <[^>]*> ecb0 0b03 fldmiax r0!, {d0}( @ Deprecated|)
+0+074 <[^>]*> ecb0 0b03 fldmiax r0!, {d0}( @ Deprecated|)
+0+078 <[^>]*> ed30 0b03 fldmdbx r0!, {d0}( @ Deprecated|)
+0+07c <[^>]*> ed30 0b03 fldmdbx r0!, {d0}( @ Deprecated|)
0+080 <[^>]*> ec80 0a01 (vstmia|fstmias) r0, {s0}
0+084 <[^>]*> ec80 0a01 (vstmia|fstmias) r0, {s0}
0+088 <[^>]*> eca0 0a01 (vstmia|fstmias) r0!, {s0}
0+08c <[^>]*> eca0 0a01 (vstmia|fstmias) r0!, {s0}
0+090 <[^>]*> ed20 0a01 (vstmdb|fstmdbs) r0!, {s0}
0+094 <[^>]*> ed20 0a01 (vstmdb|fstmdbs) r0!, {s0}
-0+098 <[^>]*> ec80 0b03 fstmiax r0, {d0}( ;@ Deprecated|)
-0+09c <[^>]*> ec80 0b03 fstmiax r0, {d0}( ;@ Deprecated|)
-0+0a0 <[^>]*> eca0 0b03 fstmiax r0!, {d0}( ;@ Deprecated|)
-0+0a4 <[^>]*> eca0 0b03 fstmiax r0!, {d0}( ;@ Deprecated|)
-0+0a8 <[^>]*> ed20 0b03 fstmdbx r0!, {d0}( ;@ Deprecated|)
-0+0ac <[^>]*> ed20 0b03 fstmdbx r0!, {d0}( ;@ Deprecated|)
+0+098 <[^>]*> ec80 0b03 fstmiax r0, {d0}( @ Deprecated|)
+0+09c <[^>]*> ec80 0b03 fstmiax r0, {d0}( @ Deprecated|)
+0+0a0 <[^>]*> eca0 0b03 fstmiax r0!, {d0}( @ Deprecated|)
+0+0a4 <[^>]*> eca0 0b03 fstmiax r0!, {d0}( @ Deprecated|)
+0+0a8 <[^>]*> ed20 0b03 fstmdbx r0!, {d0}( @ Deprecated|)
+0+0ac <[^>]*> ed20 0b03 fstmdbx r0!, {d0}( @ Deprecated|)
0+0b0 <[^>]*> eeb8 0ac0 (vcvt\.f32\.s32|fsitos) s0, s0
0+0b4 <[^>]*> eeb8 0a40 (vcvt\.f32\.u32|fuitos) s0, s0
0+0b8 <[^>]*> eebd 0a40 (vcvtr\.s32\.f32|ftosis) s0, s0
0+210 <[^>]*> ec90 fa02 (vldmia|fldmias) r0, {s30-s31}
0+214 <[^>]*> ec91 0a01 (vldmia|fldmias) r1, {s0}
0+218 <[^>]*> ec9e 0a01 (vldmia|fldmias) lr, {s0}
-0+21c <[^>]*> ec80 1b03 fstmiax r0, {d1}( ;@ Deprecated|)
-0+220 <[^>]*> ec80 2b03 fstmiax r0, {d2}( ;@ Deprecated|)
-0+224 <[^>]*> ec80 fb03 fstmiax r0, {d15}( ;@ Deprecated|)
-0+228 <[^>]*> ec80 0b05 fstmiax r0, {d0-d1}( ;@ Deprecated|)
-0+22c <[^>]*> ec80 0b07 fstmiax r0, {d0-d2}( ;@ Deprecated|)
-0+230 <[^>]*> ec80 0b21 fstmiax r0, {d0-d15}( ;@ Deprecated|)
-0+234 <[^>]*> ec80 1b1f fstmiax r0, {d1-d15}( ;@ Deprecated|)
-0+238 <[^>]*> ec80 2b1d fstmiax r0, {d2-d15}( ;@ Deprecated|)
-0+23c <[^>]*> ec80 eb05 fstmiax r0, {d14-d15}( ;@ Deprecated|)
-0+240 <[^>]*> ec81 0b03 fstmiax r1, {d0}( ;@ Deprecated|)
-0+244 <[^>]*> ec8e 0b03 fstmiax lr, {d0}( ;@ Deprecated|)
+0+21c <[^>]*> ec80 1b03 fstmiax r0, {d1}( @ Deprecated|)
+0+220 <[^>]*> ec80 2b03 fstmiax r0, {d2}( @ Deprecated|)
+0+224 <[^>]*> ec80 fb03 fstmiax r0, {d15}( @ Deprecated|)
+0+228 <[^>]*> ec80 0b05 fstmiax r0, {d0-d1}( @ Deprecated|)
+0+22c <[^>]*> ec80 0b07 fstmiax r0, {d0-d2}( @ Deprecated|)
+0+230 <[^>]*> ec80 0b21 fstmiax r0, {d0-d15}( @ Deprecated|)
+0+234 <[^>]*> ec80 1b1f fstmiax r0, {d1-d15}( @ Deprecated|)
+0+238 <[^>]*> ec80 2b1d fstmiax r0, {d2-d15}( @ Deprecated|)
+0+23c <[^>]*> ec80 eb05 fstmiax r0, {d14-d15}( @ Deprecated|)
+0+240 <[^>]*> ec81 0b03 fstmiax r1, {d0}( @ Deprecated|)
+0+244 <[^>]*> ec8e 0b03 fstmiax lr, {d0}( @ Deprecated|)
0+248 <[^>]*> eeb5 0a40 (vcmp\.f32 s0, #0.0|fcmpzs s0)
0+24c <[^>]*> eef5 0a40 (vcmp\.f32 s1, #0.0|fcmpzs s1)
0+250 <[^>]*> eeb5 1a40 (vcmp\.f32 s2, #0.0|fcmpzs s2)
0+334 <[^>]*> bf01 itttt eq
0+336 <[^>]*> ed35 2a01 (vldmdbeq|fldmdbseq) r5!, {s4}
0+33a <[^>]*> ed76 1a01 (vldmdbeq|fldmdbseq) r6!, {s3}
-0+33e <[^>]*> ec97 1b03 fldmiaxeq r7, {d1}( ;@ Deprecated|)
-0+342 <[^>]*> ec98 2b03 fldmiaxeq r8, {d2}( ;@ Deprecated|)
+0+33e <[^>]*> ec97 1b03 fldmiaxeq r7, {d1}( @ Deprecated|)
+0+342 <[^>]*> ec98 2b03 fldmiaxeq r8, {d2}( @ Deprecated|)
0+346 <[^>]*> bf01 itttt eq
-0+348 <[^>]*> ecb9 3b03 fldmiaxeq r9!, {d3}( ;@ Deprecated|)
-0+34c <[^>]*> ecba 4b03 fldmiaxeq sl!, {d4}( ;@ Deprecated|)
-0+350 <[^>]*> ed3b 5b03 fldmdbxeq fp!, {d5}( ;@ Deprecated|)
-0+354 <[^>]*> ed3c 6b03 fldmdbxeq ip!, {d6}( ;@ Deprecated|)
+0+348 <[^>]*> ecb9 3b03 fldmiaxeq r9!, {d3}( @ Deprecated|)
+0+34c <[^>]*> ecba 4b03 fldmiaxeq sl!, {d4}( @ Deprecated|)
+0+350 <[^>]*> ed3b 5b03 fldmdbxeq fp!, {d5}( @ Deprecated|)
+0+354 <[^>]*> ed3c 6b03 fldmdbxeq ip!, {d6}( @ Deprecated|)
0+358 <[^>]*> bf01 itttt eq
0+35a <[^>]*> ec8d 1a01 (vstmiaeq|fstmiaseq) sp, {s2}
0+35e <[^>]*> ecce 0a01 (vstmiaeq|fstmiaseq) lr, {s1}
0+36a <[^>]*> bf01 itttt eq
0+36c <[^>]*> ed63 ea01 (vstmdbeq|fstmdbseq) r3!, {s29}
0+370 <[^>]*> ed24 ea01 (vstmdbeq|fstmdbseq) r4!, {s28}
-0+374 <[^>]*> ec85 7b03 fstmiaxeq r5, {d7}( ;@ Deprecated|)
-0+378 <[^>]*> ec86 8b03 fstmiaxeq r6, {d8}( ;@ Deprecated|)
+0+374 <[^>]*> ec85 7b03 fstmiaxeq r5, {d7}( @ Deprecated|)
+0+378 <[^>]*> ec86 8b03 fstmiaxeq r6, {d8}( @ Deprecated|)
0+37c <[^>]*> bf01 itttt eq
-0+37e <[^>]*> eca7 9b03 fstmiaxeq r7!, {d9}( ;@ Deprecated|)
-0+382 <[^>]*> eca8 ab03 fstmiaxeq r8!, {d10}( ;@ Deprecated|)
-0+386 <[^>]*> ed29 bb03 fstmdbxeq r9!, {d11}( ;@ Deprecated|)
-0+38a <[^>]*> ed2a cb03 fstmdbxeq sl!, {d12}( ;@ Deprecated|)
+0+37e <[^>]*> eca7 9b03 fstmiaxeq r7!, {d9}( @ Deprecated|)
+0+382 <[^>]*> eca8 ab03 fstmiaxeq r8!, {d10}( @ Deprecated|)
+0+386 <[^>]*> ed29 bb03 fstmdbxeq r9!, {d11}( @ Deprecated|)
+0+38a <[^>]*> ed2a cb03 fstmdbxeq sl!, {d12}( @ Deprecated|)
0+38e <[^>]*> bf01 itttt eq
0+390 <[^>]*> eef8 dac3 (vcvteq\.f32\.s32|fsitoseq) s27, s6
0+394 <[^>]*> eefd ca62 (vcvtreq\.s32\.f32|ftosiseq) s25, s5
0[0-9a-f]+ <[^>]+> edca5b01 vstr d21, \[sl, #4\]
0[0-9a-f]+ <[^>]+> ecba5b04 vldmia sl!, {d5-d6}
0[0-9a-f]+ <[^>]+> ecfa2b06 vldmia sl!, {d18-d20}
-0[0-9a-f]+ <[^>]+> ecba5b05 fldmiax sl!, {d5-d6}( ;@ Deprecated|)
-0[0-9a-f]+ <[^>]+> ecfa2b07 fldmiax sl!, {d18-d20}( ;@ Deprecated|)
-0[0-9a-f]+ <[^>]+> ed7a2b05 fldmdbx sl!, {d18-d19}( ;@ Deprecated|)
+0[0-9a-f]+ <[^>]+> ecba5b05 fldmiax sl!, {d5-d6}( @ Deprecated|)
+0[0-9a-f]+ <[^>]+> ecfa2b07 fldmiax sl!, {d18-d20}( @ Deprecated|)
+0[0-9a-f]+ <[^>]+> ed7a2b05 fldmdbx sl!, {d18-d19}( @ Deprecated|)
0[0-9a-f]+ <[^>]+> ecc94b0a vstmia r9, {d20-d24}
0[0-9a-f]+ <[^>]+> eeb03bc5 (vabs\.f64|fabsd) d3, d5
0[0-9a-f]+ <[^>]+> eeb0cbe2 (vabs\.f64|fabsd) d12, d18
.*: +file format .*arm.*
Disassembly of section .text:
-00000000 <foo> ed9f0a0e vldr s0, \[pc, #56\] ; 00000040 <foo\+0x40>
-00000004 <foo\+0x4> ed9f7a0d vldr s14, \[pc, #52\] ; 00000040 <foo\+0x40>
-00000008 <foo\+0x8> ed9fea0c vldr s28, \[pc, #48\] ; 00000040 <foo\+0x40>
-0000000c <foo\+0xc> eddffa0b vldr s31, \[pc, #44\] ; 00000040 <foo\+0x40>
-00000010 <foo\+0x10> ed9f0a0b vldr s0, \[pc, #44\] ; 00000044 <foo\+0x44>
-00000014 <foo\+0x14> ed9f7a0a vldr s14, \[pc, #40\] ; 00000044 <foo\+0x44>
-00000018 <foo\+0x18> ed9fea09 vldr s28, \[pc, #36\] ; 00000044 <foo\+0x44>
-0000001c <foo\+0x1c> eddffa08 vldr s31, \[pc, #32\] ; 00000044 <foo\+0x44>
-00000020 <foo\+0x20> ed9f0a08 vldr s0, \[pc, #32\] ; 00000048 <foo\+0x48>
-00000024 <foo\+0x24> ed9f7a07 vldr s14, \[pc, #28\] ; 00000048 <foo\+0x48>
-00000028 <foo\+0x28> ed9fea06 vldr s28, \[pc, #24\] ; 00000048 <foo\+0x48>
-0000002c <foo\+0x2c> eddffa05 vldr s31, \[pc, #20\] ; 00000048 <foo\+0x48>
-00000030 <foo\+0x30> ed9f0a05 vldr s0, \[pc, #20\] ; 0000004c <foo\+0x4c>
-00000034 <foo\+0x34> ed9f7a04 vldr s14, \[pc, #16\] ; 0000004c <foo\+0x4c>
-00000038 <foo\+0x38> ed9fea03 vldr s28, \[pc, #12\] ; 0000004c <foo\+0x4c>
-0000003c <foo\+0x3c> eddffa02 vldr s31, \[pc, #8\] ; 0000004c <foo\+0x4c>
+00000000 <foo> ed9f0a0e vldr s0, \[pc, #56\] @ 00000040 <foo\+0x40>
+00000004 <foo\+0x4> ed9f7a0d vldr s14, \[pc, #52\] @ 00000040 <foo\+0x40>
+00000008 <foo\+0x8> ed9fea0c vldr s28, \[pc, #48\] @ 00000040 <foo\+0x40>
+0000000c <foo\+0xc> eddffa0b vldr s31, \[pc, #44\] @ 00000040 <foo\+0x40>
+00000010 <foo\+0x10> ed9f0a0b vldr s0, \[pc, #44\] @ 00000044 <foo\+0x44>
+00000014 <foo\+0x14> ed9f7a0a vldr s14, \[pc, #40\] @ 00000044 <foo\+0x44>
+00000018 <foo\+0x18> ed9fea09 vldr s28, \[pc, #36\] @ 00000044 <foo\+0x44>
+0000001c <foo\+0x1c> eddffa08 vldr s31, \[pc, #32\] @ 00000044 <foo\+0x44>
+00000020 <foo\+0x20> ed9f0a08 vldr s0, \[pc, #32\] @ 00000048 <foo\+0x48>
+00000024 <foo\+0x24> ed9f7a07 vldr s14, \[pc, #28\] @ 00000048 <foo\+0x48>
+00000028 <foo\+0x28> ed9fea06 vldr s28, \[pc, #24\] @ 00000048 <foo\+0x48>
+0000002c <foo\+0x2c> eddffa05 vldr s31, \[pc, #20\] @ 00000048 <foo\+0x48>
+00000030 <foo\+0x30> ed9f0a05 vldr s0, \[pc, #20\] @ 0000004c <foo\+0x4c>
+00000034 <foo\+0x34> ed9f7a04 vldr s14, \[pc, #16\] @ 0000004c <foo\+0x4c>
+00000038 <foo\+0x38> ed9fea03 vldr s28, \[pc, #12\] @ 0000004c <foo\+0x4c>
+0000003c <foo\+0x3c> eddffa02 vldr s31, \[pc, #8\] @ 0000004c <foo\+0x4c>
00000040 <foo\+0x40> 00000000 .word 0x00000000
00000044 <foo\+0x44> ff000000 .word 0xff000000
00000048 <foo\+0x48> ffffffff .word 0xffffffff
0000004c <foo\+0x4c> 0fff0000 .word 0x0fff0000
-00000050 <foo\+0x50> ed9f0a0e vldr s0, \[pc, #56\] ; 00000090 <foo\+0x90>
-00000054 <foo\+0x54> ed9f7a0d vldr s14, \[pc, #52\] ; 00000090 <foo\+0x90>
-00000058 <foo\+0x58> ed9fea0c vldr s28, \[pc, #48\] ; 00000090 <foo\+0x90>
-0000005c <foo\+0x5c> eddffa0b vldr s31, \[pc, #44\] ; 00000090 <foo\+0x90>
-00000060 <foo\+0x60> ed9f0a0b vldr s0, \[pc, #44\] ; 00000094 <foo\+0x94>
-00000064 <foo\+0x64> ed9f7a0a vldr s14, \[pc, #40\] ; 00000094 <foo\+0x94>
-00000068 <foo\+0x68> ed9fea09 vldr s28, \[pc, #36\] ; 00000094 <foo\+0x94>
-0000006c <foo\+0x6c> eddffa08 vldr s31, \[pc, #32\] ; 00000094 <foo\+0x94>
-00000070 <foo\+0x70> ed9f0a08 vldr s0, \[pc, #32\] ; 00000098 <foo\+0x98>
-00000074 <foo\+0x74> ed9f7a07 vldr s14, \[pc, #28\] ; 00000098 <foo\+0x98>
-00000078 <foo\+0x78> ed9fea06 vldr s28, \[pc, #24\] ; 00000098 <foo\+0x98>
-0000007c <foo\+0x7c> eddffa05 vldr s31, \[pc, #20\] ; 00000098 <foo\+0x98>
-00000080 <foo\+0x80> ed9f0a05 vldr s0, \[pc, #20\] ; 0000009c <foo\+0x9c>
-00000084 <foo\+0x84> ed9f7a04 vldr s14, \[pc, #16\] ; 0000009c <foo\+0x9c>
-00000088 <foo\+0x88> ed9fea03 vldr s28, \[pc, #12\] ; 0000009c <foo\+0x9c>
-0000008c <foo\+0x8c> eddffa02 vldr s31, \[pc, #8\] ; 0000009c <foo\+0x9c>
+00000050 <foo\+0x50> ed9f0a0e vldr s0, \[pc, #56\] @ 00000090 <foo\+0x90>
+00000054 <foo\+0x54> ed9f7a0d vldr s14, \[pc, #52\] @ 00000090 <foo\+0x90>
+00000058 <foo\+0x58> ed9fea0c vldr s28, \[pc, #48\] @ 00000090 <foo\+0x90>
+0000005c <foo\+0x5c> eddffa0b vldr s31, \[pc, #44\] @ 00000090 <foo\+0x90>
+00000060 <foo\+0x60> ed9f0a0b vldr s0, \[pc, #44\] @ 00000094 <foo\+0x94>
+00000064 <foo\+0x64> ed9f7a0a vldr s14, \[pc, #40\] @ 00000094 <foo\+0x94>
+00000068 <foo\+0x68> ed9fea09 vldr s28, \[pc, #36\] @ 00000094 <foo\+0x94>
+0000006c <foo\+0x6c> eddffa08 vldr s31, \[pc, #32\] @ 00000094 <foo\+0x94>
+00000070 <foo\+0x70> ed9f0a08 vldr s0, \[pc, #32\] @ 00000098 <foo\+0x98>
+00000074 <foo\+0x74> ed9f7a07 vldr s14, \[pc, #28\] @ 00000098 <foo\+0x98>
+00000078 <foo\+0x78> ed9fea06 vldr s28, \[pc, #24\] @ 00000098 <foo\+0x98>
+0000007c <foo\+0x7c> eddffa05 vldr s31, \[pc, #20\] @ 00000098 <foo\+0x98>
+00000080 <foo\+0x80> ed9f0a05 vldr s0, \[pc, #20\] @ 0000009c <foo\+0x9c>
+00000084 <foo\+0x84> ed9f7a04 vldr s14, \[pc, #16\] @ 0000009c <foo\+0x9c>
+00000088 <foo\+0x88> ed9fea03 vldr s28, \[pc, #12\] @ 0000009c <foo\+0x9c>
+0000008c <foo\+0x8c> eddffa02 vldr s31, \[pc, #8\] @ 0000009c <foo\+0x9c>
00000090 <foo\+0x90> 00000000 .word 0x00000000
00000094 <foo\+0x94> 00ff0000 .word 0x00ff0000
00000098 <foo\+0x98> ff00ffff .word 0xff00ffff
0000009c <foo\+0x9c> 00fff000 .word 0x00fff000
-000000a0 <foo\+0xa0> 0d9f0a0e vldreq s0, \[pc, #56\] ; 000000e0 <foo\+0xe0>
-000000a4 <foo\+0xa4> 0d9f7a0d vldreq s14, \[pc, #52\] ; 000000e0 <foo\+0xe0>
-000000a8 <foo\+0xa8> 0d9fea0c vldreq s28, \[pc, #48\] ; 000000e0 <foo\+0xe0>
-000000ac <foo\+0xac> 0ddffa0b vldreq s31, \[pc, #44\] ; 000000e0 <foo\+0xe0>
-000000b0 <foo\+0xb0> 0d9f0a0b vldreq s0, \[pc, #44\] ; 000000e4 <foo\+0xe4>
-000000b4 <foo\+0xb4> 0d9f7a0a vldreq s14, \[pc, #40\] ; 000000e4 <foo\+0xe4>
-000000b8 <foo\+0xb8> 0d9fea09 vldreq s28, \[pc, #36\] ; 000000e4 <foo\+0xe4>
-000000bc <foo\+0xbc> 0ddffa08 vldreq s31, \[pc, #32\] ; 000000e4 <foo\+0xe4>
-000000c0 <foo\+0xc0> 0d9f0a08 vldreq s0, \[pc, #32\] ; 000000e8 <foo\+0xe8>
-000000c4 <foo\+0xc4> 0d9f7a07 vldreq s14, \[pc, #28\] ; 000000e8 <foo\+0xe8>
-000000c8 <foo\+0xc8> 0d9fea06 vldreq s28, \[pc, #24\] ; 000000e8 <foo\+0xe8>
-000000cc <foo\+0xcc> 0ddffa05 vldreq s31, \[pc, #20\] ; 000000e8 <foo\+0xe8>
-000000d0 <foo\+0xd0> 0d9f0a05 vldreq s0, \[pc, #20\] ; 000000ec <foo\+0xec>
-000000d4 <foo\+0xd4> 0d9f7a04 vldreq s14, \[pc, #16\] ; 000000ec <foo\+0xec>
-000000d8 <foo\+0xd8> 0d9fea03 vldreq s28, \[pc, #12\] ; 000000ec <foo\+0xec>
-000000dc <foo\+0xdc> 0ddffa02 vldreq s31, \[pc, #8\] ; 000000ec <foo\+0xec>
+000000a0 <foo\+0xa0> 0d9f0a0e vldreq s0, \[pc, #56\] @ 000000e0 <foo\+0xe0>
+000000a4 <foo\+0xa4> 0d9f7a0d vldreq s14, \[pc, #52\] @ 000000e0 <foo\+0xe0>
+000000a8 <foo\+0xa8> 0d9fea0c vldreq s28, \[pc, #48\] @ 000000e0 <foo\+0xe0>
+000000ac <foo\+0xac> 0ddffa0b vldreq s31, \[pc, #44\] @ 000000e0 <foo\+0xe0>
+000000b0 <foo\+0xb0> 0d9f0a0b vldreq s0, \[pc, #44\] @ 000000e4 <foo\+0xe4>
+000000b4 <foo\+0xb4> 0d9f7a0a vldreq s14, \[pc, #40\] @ 000000e4 <foo\+0xe4>
+000000b8 <foo\+0xb8> 0d9fea09 vldreq s28, \[pc, #36\] @ 000000e4 <foo\+0xe4>
+000000bc <foo\+0xbc> 0ddffa08 vldreq s31, \[pc, #32\] @ 000000e4 <foo\+0xe4>
+000000c0 <foo\+0xc0> 0d9f0a08 vldreq s0, \[pc, #32\] @ 000000e8 <foo\+0xe8>
+000000c4 <foo\+0xc4> 0d9f7a07 vldreq s14, \[pc, #28\] @ 000000e8 <foo\+0xe8>
+000000c8 <foo\+0xc8> 0d9fea06 vldreq s28, \[pc, #24\] @ 000000e8 <foo\+0xe8>
+000000cc <foo\+0xcc> 0ddffa05 vldreq s31, \[pc, #20\] @ 000000e8 <foo\+0xe8>
+000000d0 <foo\+0xd0> 0d9f0a05 vldreq s0, \[pc, #20\] @ 000000ec <foo\+0xec>
+000000d4 <foo\+0xd4> 0d9f7a04 vldreq s14, \[pc, #16\] @ 000000ec <foo\+0xec>
+000000d8 <foo\+0xd8> 0d9fea03 vldreq s28, \[pc, #12\] @ 000000ec <foo\+0xec>
+000000dc <foo\+0xdc> 0ddffa02 vldreq s31, \[pc, #8\] @ 000000ec <foo\+0xec>
000000e0 <foo\+0xe0> 00000000 .word 0x00000000
000000e4 <foo\+0xe4> 0000ff00 .word 0x0000ff00
000000e8 <foo\+0xe8> ffff00ff .word 0xffff00ff
000000ec <foo\+0xec> 000fff00 .word 0x000fff00
-000000f0 <foo\+0xf0> 4d9f0a0e vldrmi s0, \[pc, #56\] ; 00000130 <foo\+0x130>
-000000f4 <foo\+0xf4> 4d9f7a0d vldrmi s14, \[pc, #52\] ; 00000130 <foo\+0x130>
-000000f8 <foo\+0xf8> 4d9fea0c vldrmi s28, \[pc, #48\] ; 00000130 <foo\+0x130>
-000000fc <foo\+0xfc> 4ddffa0b vldrmi s31, \[pc, #44\] ; 00000130 <foo\+0x130>
-00000100 <foo\+0x100> 4d9f0a0b vldrmi s0, \[pc, #44\] ; 00000134 <foo\+0x134>
-00000104 <foo\+0x104> 4d9f7a0a vldrmi s14, \[pc, #40\] ; 00000134 <foo\+0x134>
-00000108 <foo\+0x108> 4d9fea09 vldrmi s28, \[pc, #36\] ; 00000134 <foo\+0x134>
-0000010c <foo\+0x10c> 4ddffa08 vldrmi s31, \[pc, #32\] ; 00000134 <foo\+0x134>
-00000110 <foo\+0x110> 4d9f0a08 vldrmi s0, \[pc, #32\] ; 00000138 <foo\+0x138>
-00000114 <foo\+0x114> 4d9f7a07 vldrmi s14, \[pc, #28\] ; 00000138 <foo\+0x138>
-00000118 <foo\+0x118> 4d9fea06 vldrmi s28, \[pc, #24\] ; 00000138 <foo\+0x138>
-0000011c <foo\+0x11c> 4ddffa05 vldrmi s31, \[pc, #20\] ; 00000138 <foo\+0x138>
-00000120 <foo\+0x120> 4d9f0a05 vldrmi s0, \[pc, #20\] ; 0000013c <foo\+0x13c>
-00000124 <foo\+0x124> 4d9f7a04 vldrmi s14, \[pc, #16\] ; 0000013c <foo\+0x13c>
-00000128 <foo\+0x128> 4d9fea03 vldrmi s28, \[pc, #12\] ; 0000013c <foo\+0x13c>
-0000012c <foo\+0x12c> 4ddffa02 vldrmi s31, \[pc, #8\] ; 0000013c <foo\+0x13c>
+000000f0 <foo\+0xf0> 4d9f0a0e vldrmi s0, \[pc, #56\] @ 00000130 <foo\+0x130>
+000000f4 <foo\+0xf4> 4d9f7a0d vldrmi s14, \[pc, #52\] @ 00000130 <foo\+0x130>
+000000f8 <foo\+0xf8> 4d9fea0c vldrmi s28, \[pc, #48\] @ 00000130 <foo\+0x130>
+000000fc <foo\+0xfc> 4ddffa0b vldrmi s31, \[pc, #44\] @ 00000130 <foo\+0x130>
+00000100 <foo\+0x100> 4d9f0a0b vldrmi s0, \[pc, #44\] @ 00000134 <foo\+0x134>
+00000104 <foo\+0x104> 4d9f7a0a vldrmi s14, \[pc, #40\] @ 00000134 <foo\+0x134>
+00000108 <foo\+0x108> 4d9fea09 vldrmi s28, \[pc, #36\] @ 00000134 <foo\+0x134>
+0000010c <foo\+0x10c> 4ddffa08 vldrmi s31, \[pc, #32\] @ 00000134 <foo\+0x134>
+00000110 <foo\+0x110> 4d9f0a08 vldrmi s0, \[pc, #32\] @ 00000138 <foo\+0x138>
+00000114 <foo\+0x114> 4d9f7a07 vldrmi s14, \[pc, #28\] @ 00000138 <foo\+0x138>
+00000118 <foo\+0x118> 4d9fea06 vldrmi s28, \[pc, #24\] @ 00000138 <foo\+0x138>
+0000011c <foo\+0x11c> 4ddffa05 vldrmi s31, \[pc, #20\] @ 00000138 <foo\+0x138>
+00000120 <foo\+0x120> 4d9f0a05 vldrmi s0, \[pc, #20\] @ 0000013c <foo\+0x13c>
+00000124 <foo\+0x124> 4d9f7a04 vldrmi s14, \[pc, #16\] @ 0000013c <foo\+0x13c>
+00000128 <foo\+0x128> 4d9fea03 vldrmi s28, \[pc, #12\] @ 0000013c <foo\+0x13c>
+0000012c <foo\+0x12c> 4ddffa02 vldrmi s31, \[pc, #8\] @ 0000013c <foo\+0x13c>
00000130 <foo\+0x130> 00000000 .word 0x00000000
00000134 <foo\+0x134> 000000ff .word 0x000000ff
00000138 <foo\+0x138> ffffff00 .word 0xffffff00
00000144 <foo\+0x144> f280ee30 vmov.i64 d14, #0x0000000000000000
00000148 <foo\+0x148> f2c0ce30 vmov.i64 d28, #0x0000000000000000
0000014c <foo\+0x14c> f2c0fe30 vmov.i64 d31, #0x0000000000000000
-00000150 <foo\+0x150> ed9f0b0a vldr d0, \[pc, #40\] ; 00000180 <foo\+0x180>
-00000154 <foo\+0x154> ed9feb09 vldr d14, \[pc, #36\] ; 00000180 <foo\+0x180>
-00000158 <foo\+0x158> eddfcb08 vldr d28, \[pc, #32\] ; 00000180 <foo\+0x180>
-0000015c <foo\+0x15c> eddffb07 vldr d31, \[pc, #28\] ; 00000180 <foo\+0x180>
+00000150 <foo\+0x150> ed9f0b0a vldr d0, \[pc, #40\] @ 00000180 <foo\+0x180>
+00000154 <foo\+0x154> ed9feb09 vldr d14, \[pc, #36\] @ 00000180 <foo\+0x180>
+00000158 <foo\+0x158> eddfcb08 vldr d28, \[pc, #32\] @ 00000180 <foo\+0x180>
+0000015c <foo\+0x15c> eddffb07 vldr d31, \[pc, #28\] @ 00000180 <foo\+0x180>
00000160 <foo\+0x160> f3870e3f vmov.i64 d0, #0xffffffffffffffff
00000164 <foo\+0x164> f387ee3f vmov.i64 d14, #0xffffffffffffffff
00000168 <foo\+0x168> f3c7ce3f vmov.i64 d28, #0xffffffffffffffff
0000016c <foo\+0x16c> f3c7fe3f vmov.i64 d31, #0xffffffffffffffff
-00000170 <foo\+0x170> ed9f0b04 vldr d0, \[pc, #16\] ; 00000188 <foo\+0x188>
-00000174 <foo\+0x174> ed9feb03 vldr d14, \[pc, #12\] ; 00000188 <foo\+0x188>
-00000178 <foo\+0x178> eddfcb02 vldr d28, \[pc, #8\] ; 00000188 <foo\+0x188>
-0000017c <foo\+0x17c> eddffb01 vldr d31, \[pc, #4\] ; 00000188 <foo\+0x188>
+00000170 <foo\+0x170> ed9f0b04 vldr d0, \[pc, #16\] @ 00000188 <foo\+0x188>
+00000174 <foo\+0x174> ed9feb03 vldr d14, \[pc, #12\] @ 00000188 <foo\+0x188>
+00000178 <foo\+0x178> eddfcb02 vldr d28, \[pc, #8\] @ 00000188 <foo\+0x188>
+0000017c <foo\+0x17c> eddffb01 vldr d31, \[pc, #4\] @ 00000188 <foo\+0x188>
00000180 <foo\+0x180> ca000000 .word 0xca000000
00000184 <foo\+0x184> 00000000 .word 0x00000000
00000188 <foo\+0x188> 0fff0000 .word 0x0fff0000
000001b4 <foo\+0x1b4> f280ee39 vmov.i64 d14, #0x00000000ff0000ff
000001b8 <foo\+0x1b8> f2c0ce39 vmov.i64 d28, #0x00000000ff0000ff
000001bc <foo\+0x1bc> f2c0fe39 vmov.i64 d31, #0x00000000ff0000ff
-000001c0 <foo\+0x1c0> ed9f0b02 vldr d0, \[pc, #8\] ; 000001d0 <foo\+0x1d0>
-000001c4 <foo\+0x1c4> ed9feb01 vldr d14, \[pc, #4\] ; 000001d0 <foo\+0x1d0>
-000001c8 <foo\+0x1c8> eddfcb00 vldr d28, \[pc\] ; 000001d0 <foo\+0x1d0>
-000001cc <foo\+0x1cc> ed5ffb01 vldr d31, \[pc, #-4\] ; 000001d0 <foo\+0x1d0>
+000001c0 <foo\+0x1c0> ed9f0b02 vldr d0, \[pc, #8\] @ 000001d0 <foo\+0x1d0>
+000001c4 <foo\+0x1c4> ed9feb01 vldr d14, \[pc, #4\] @ 000001d0 <foo\+0x1d0>
+000001c8 <foo\+0x1c8> eddfcb00 vldr d28, \[pc\] @ 000001d0 <foo\+0x1d0>
+000001cc <foo\+0x1cc> ed5ffb01 vldr d31, \[pc, #-4\] @ 000001d0 <foo\+0x1d0>
000001d0 <foo\+0x1d0> 00fff000 .word 0x00fff000
000001d4 <foo\+0x1d4> 00000000 .word 0x00000000
000001d8 <foo\+0x1d8> f2800e30 vmov.i64 d0, #0x0000000000000000
000001fc <foo\+0x1fc> f280ee3d vmov.i64 d14, #0x00000000ffff00ff
00000200 <foo\+0x200> f2c0ce3d vmov.i64 d28, #0x00000000ffff00ff
00000204 <foo\+0x204> f2c0fe3d vmov.i64 d31, #0x00000000ffff00ff
-00000208 <foo\+0x208> 0d9f0b02 vldreq d0, \[pc, #8\] ; 00000218 <foo\+0x218>
-0000020c <foo\+0x20c> 0d9feb01 vldreq d14, \[pc, #4\] ; 00000218 <foo\+0x218>
-00000210 <foo\+0x210> 0ddfcb00 vldreq d28, \[pc\] ; 00000218 <foo\+0x218>
-00000214 <foo\+0x214> 0d5ffb01 vldreq d31, \[pc, #-4\] ; 00000218 <foo\+0x218>
+00000208 <foo\+0x208> 0d9f0b02 vldreq d0, \[pc, #8\] @ 00000218 <foo\+0x218>
+0000020c <foo\+0x20c> 0d9feb01 vldreq d14, \[pc, #4\] @ 00000218 <foo\+0x218>
+00000210 <foo\+0x210> 0ddfcb00 vldreq d28, \[pc\] @ 00000218 <foo\+0x218>
+00000214 <foo\+0x214> 0d5ffb01 vldreq d31, \[pc, #-4\] @ 00000218 <foo\+0x218>
00000218 <foo\+0x218> 000fff00 .word 0x000fff00
0000021c <foo\+0x21c> 00000000 .word 0x00000000
00000220 <foo\+0x220> f2800e30 vmov.i64 d0, #0x0000000000000000
00000284 <foo\+0x284> f387ee3f vmov.i64 d14, #0xffffffffffffffff
00000288 <foo\+0x288> f3c7ce3f vmov.i64 d28, #0xffffffffffffffff
0000028c <foo\+0x28c> f3c7fe3f vmov.i64 d31, #0xffffffffffffffff
-00000290 <foo\+0x290> ed9f0b02 vldr d0, \[pc, #8\] ; 000002a0 <foo\+0x2a0>
-00000294 <foo\+0x294> ed9feb01 vldr d14, \[pc, #4\] ; 000002a0 <foo\+0x2a0>
-00000298 <foo\+0x298> eddfcb00 vldr d28, \[pc\] ; 000002a0 <foo\+0x2a0>
-0000029c <foo\+0x29c> ed5ffb01 vldr d31, \[pc, #-4\] ; 000002a0 <foo\+0x2a0>
+00000290 <foo\+0x290> ed9f0b02 vldr d0, \[pc, #8\] @ 000002a0 <foo\+0x2a0>
+00000294 <foo\+0x294> ed9feb01 vldr d14, \[pc, #4\] @ 000002a0 <foo\+0x2a0>
+00000298 <foo\+0x298> eddfcb00 vldr d28, \[pc\] @ 000002a0 <foo\+0x2a0>
+0000029c <foo\+0x29c> ed5ffb01 vldr d31, \[pc, #-4\] @ 000002a0 <foo\+0x2a0>
000002a0 <foo\+0x2a0> 00000000 .word 0x00000000
000002a4 <foo\+0x2a4> 0fff0000 .word 0x0fff0000
000002a8 <foo\+0x2a8> f2800e30 vmov.i64 d0, #0x0000000000000000
000002ac <foo\+0x2ac> f280ee30 vmov.i64 d14, #0x0000000000000000
000002b0 <foo\+0x2b0> f2c0ce30 vmov.i64 d28, #0x0000000000000000
000002b4 <foo\+0x2b4> f2c0fe30 vmov.i64 d31, #0x0000000000000000
-000002b8 <foo\+0x2b8> ed9f0b0a vldr d0, \[pc, #40\] ; 000002e8 <foo\+0x2e8>
-000002bc <foo\+0x2bc> ed9feb09 vldr d14, \[pc, #36\] ; 000002e8 <foo\+0x2e8>
-000002c0 <foo\+0x2c0> eddfcb08 vldr d28, \[pc, #32\] ; 000002e8 <foo\+0x2e8>
-000002c4 <foo\+0x2c4> eddffb07 vldr d31, \[pc, #28\] ; 000002e8 <foo\+0x2e8>
-000002c8 <foo\+0x2c8> ed9f0b08 vldr d0, \[pc, #32\] ; 000002f0 <foo\+0x2f0>
-000002cc <foo\+0x2cc> ed9feb07 vldr d14, \[pc, #28\] ; 000002f0 <foo\+0x2f0>
-000002d0 <foo\+0x2d0> eddfcb06 vldr d28, \[pc, #24\] ; 000002f0 <foo\+0x2f0>
-000002d4 <foo\+0x2d4> eddffb05 vldr d31, \[pc, #20\] ; 000002f0 <foo\+0x2f0>
-000002d8 <foo\+0x2d8> ed9f0b06 vldr d0, \[pc, #24\] ; 000002f8 <foo\+0x2f8>
-000002dc <foo\+0x2dc> ed9feb05 vldr d14, \[pc, #20\] ; 000002f8 <foo\+0x2f8>
-000002e0 <foo\+0x2e0> eddfcb04 vldr d28, \[pc, #16\] ; 000002f8 <foo\+0x2f8>
-000002e4 <foo\+0x2e4> eddffb03 vldr d31, \[pc, #12\] ; 000002f8 <foo\+0x2f8>
+000002b8 <foo\+0x2b8> ed9f0b0a vldr d0, \[pc, #40\] @ 000002e8 <foo\+0x2e8>
+000002bc <foo\+0x2bc> ed9feb09 vldr d14, \[pc, #36\] @ 000002e8 <foo\+0x2e8>
+000002c0 <foo\+0x2c0> eddfcb08 vldr d28, \[pc, #32\] @ 000002e8 <foo\+0x2e8>
+000002c4 <foo\+0x2c4> eddffb07 vldr d31, \[pc, #28\] @ 000002e8 <foo\+0x2e8>
+000002c8 <foo\+0x2c8> ed9f0b08 vldr d0, \[pc, #32\] @ 000002f0 <foo\+0x2f0>
+000002cc <foo\+0x2cc> ed9feb07 vldr d14, \[pc, #28\] @ 000002f0 <foo\+0x2f0>
+000002d0 <foo\+0x2d0> eddfcb06 vldr d28, \[pc, #24\] @ 000002f0 <foo\+0x2f0>
+000002d4 <foo\+0x2d4> eddffb05 vldr d31, \[pc, #20\] @ 000002f0 <foo\+0x2f0>
+000002d8 <foo\+0x2d8> ed9f0b06 vldr d0, \[pc, #24\] @ 000002f8 <foo\+0x2f8>
+000002dc <foo\+0x2dc> ed9feb05 vldr d14, \[pc, #20\] @ 000002f8 <foo\+0x2f8>
+000002e0 <foo\+0x2e0> eddfcb04 vldr d28, \[pc, #16\] @ 000002f8 <foo\+0x2f8>
+000002e4 <foo\+0x2e4> eddffb03 vldr d31, \[pc, #12\] @ 000002f8 <foo\+0x2f8>
000002e8 <foo\+0x2e8> 00000000 .word 0x00000000
000002ec <foo\+0x2ec> 000ff000 .word 0x000ff000
000002f0 <foo\+0x2f0> f0000000 .word 0xf0000000
00000324 <foo\+0x324> f385ee30 vmov.i64 d14, #0xffff00ff00000000
00000328 <foo\+0x328> f3c5ce30 vmov.i64 d28, #0xffff00ff00000000
0000032c <foo\+0x32c> f3c5fe30 vmov.i64 d31, #0xffff00ff00000000
-00000330 <foo\+0x330> 0d9f0b02 vldreq d0, \[pc, #8\] ; 00000340 <foo\+0x340>
-00000334 <foo\+0x334> 0d9feb01 vldreq d14, \[pc, #4\] ; 00000340 <foo\+0x340>
-00000338 <foo\+0x338> 0ddfcb00 vldreq d28, \[pc\] ; 00000340 <foo\+0x340>
-0000033c <foo\+0x33c> 0d5ffb01 vldreq d31, \[pc, #-4\] ; 00000340 <foo\+0x340>
+00000330 <foo\+0x330> 0d9f0b02 vldreq d0, \[pc, #8\] @ 00000340 <foo\+0x340>
+00000334 <foo\+0x334> 0d9feb01 vldreq d14, \[pc, #4\] @ 00000340 <foo\+0x340>
+00000338 <foo\+0x338> 0ddfcb00 vldreq d28, \[pc\] @ 00000340 <foo\+0x340>
+0000033c <foo\+0x33c> 0d5ffb01 vldreq d31, \[pc, #-4\] @ 00000340 <foo\+0x340>
00000340 <foo\+0x340> 00000000 .word 0x00000000
00000344 <foo\+0x344> 000fff00 .word 0x000fff00
00000348 <foo\+0x348> f2800e30 vmov.i64 d0, #0x0000000000000000
0000036c <foo\+0x36c> f386ee30 vmov.i64 d14, #0xffffff0000000000
00000370 <foo\+0x370> f3c6ce30 vmov.i64 d28, #0xffffff0000000000
00000374 <foo\+0x374> f3c6fe30 vmov.i64 d31, #0xffffff0000000000
-00000378 <foo\+0x378> 4d9f0b02 vldrmi d0, \[pc, #8\] ; 00000388 <foo\+0x388>
-0000037c <foo\+0x37c> 4d9feb01 vldrmi d14, \[pc, #4\] ; 00000388 <foo\+0x388>
-00000380 <foo\+0x380> 4ddfcb00 vldrmi d28, \[pc\] ; 00000388 <foo\+0x388>
-00000384 <foo\+0x384> 4d5ffb01 vldrmi d31, \[pc, #-4\] ; 00000388 <foo\+0x388>
+00000378 <foo\+0x378> 4d9f0b02 vldrmi d0, \[pc, #8\] @ 00000388 <foo\+0x388>
+0000037c <foo\+0x37c> 4d9feb01 vldrmi d14, \[pc, #4\] @ 00000388 <foo\+0x388>
+00000380 <foo\+0x380> 4ddfcb00 vldrmi d28, \[pc\] @ 00000388 <foo\+0x388>
+00000384 <foo\+0x384> 4d5ffb01 vldrmi d31, \[pc, #-4\] @ 00000388 <foo\+0x388>
00000388 <foo\+0x388> 00000000 .word 0x00000000
0000038c <foo\+0x38c> 0000fff0 .word 0x0000fff0
-00000390 <foo\+0x390> ed9f1b00 vldr d1, \[pc\] ; 00000398 <foo\+0x398>
+00000390 <foo\+0x390> ed9f1b00 vldr d1, \[pc\] @ 00000398 <foo\+0x398>
\.\.\.
0000039c <foo\+0x39c> 0000fff0 .word 0x0000fff0
000003a0 <foo\+0x3a0> e2810000 add r0, r1, #0
-000003a4 <foo\+0x3a4> ed1f1b01 vldr d1, \[pc, #-4\] ; 000003a8 <foo\+0x3a8>
+000003a4 <foo\+0x3a4> ed1f1b01 vldr d1, \[pc, #-4\] @ 000003a8 <foo\+0x3a8>
000003a8 <foo\+0x3a8> 00000000 .word 0x00000000
000003ac <foo\+0x3ac> 0000fff0 .word 0x0000fff0
-000003b0 <foo\+0x3b0> ed9f1b10 vldr d1, \[pc, #64\] ; 000003f8 <foo\+0x3f8>
-000003b4 <foo\+0x3b4> ed9f1a11 vldr s2, \[pc, #68\] ; 00000400 <foo\+0x400>
-000003b8 <foo\+0x3b8> ed9f3b12 vldr d3, \[pc, #72\] ; 00000408 <foo\+0x408>
-000003bc <foo\+0x3bc> ed9f2a10 vldr s4, \[pc, #64\] ; 00000404 <foo\+0x404>
-000003c0 <foo\+0x3c0> ed9f5b10 vldr d5, \[pc, #64\] ; 00000408 <foo\+0x408>
-000003c4 <foo\+0x3c4> ed9f6b11 vldr d6, \[pc, #68\] ; 00000410 <foo\+0x410>
-000003c8 <foo\+0x3c8> ed9f7b12 vldr d7, \[pc, #72\] ; 00000418 <foo\+0x418>
-000003cc <foo\+0x3cc> ed9f4a13 vldr s8, \[pc, #76\] ; 00000420 <foo\+0x420>
-000003d0 <foo\+0x3d0> ed9f9b14 vldr d9, \[pc, #80\] ; 00000428 <foo\+0x428>
-000003d4 <foo\+0x3d4> ed9f5a12 vldr s10, \[pc, #72\] ; 00000424 <foo\+0x424>
-000003d8 <foo\+0x3d8> ed9fbb14 vldr d11, \[pc, #80\] ; 00000430 <foo\+0x430>
-000003dc <foo\+0x3dc> ed9f6a15 vldr s12, \[pc, #84\] ; 00000438 <foo\+0x438>
-000003e0 <foo\+0x3e0> eddf6a15 vldr s13, \[pc, #84\] ; 0000043c <foo\+0x43c>
-000003e4 <foo\+0x3e4> ed9f7a06 vldr s14, \[pc, #24\] ; 00000404 <foo\+0x404>
-000003e8 <foo\+0x3e8> eddf7a03 vldr s15, \[pc, #12\] ; 000003fc <foo\+0x3fc>
-000003ec <foo\+0x3ec> eddf0b11 vldr d16, \[pc, #68\] ; 00000438 <foo\+0x438>
-000003f0 <foo\+0x3f0> eddf1b12 vldr d17, \[pc, #72\] ; 00000440 <foo\+0x440>
+000003b0 <foo\+0x3b0> ed9f1b10 vldr d1, \[pc, #64\] @ 000003f8 <foo\+0x3f8>
+000003b4 <foo\+0x3b4> ed9f1a11 vldr s2, \[pc, #68\] @ 00000400 <foo\+0x400>
+000003b8 <foo\+0x3b8> ed9f3b12 vldr d3, \[pc, #72\] @ 00000408 <foo\+0x408>
+000003bc <foo\+0x3bc> ed9f2a10 vldr s4, \[pc, #64\] @ 00000404 <foo\+0x404>
+000003c0 <foo\+0x3c0> ed9f5b10 vldr d5, \[pc, #64\] @ 00000408 <foo\+0x408>
+000003c4 <foo\+0x3c4> ed9f6b11 vldr d6, \[pc, #68\] @ 00000410 <foo\+0x410>
+000003c8 <foo\+0x3c8> ed9f7b12 vldr d7, \[pc, #72\] @ 00000418 <foo\+0x418>
+000003cc <foo\+0x3cc> ed9f4a13 vldr s8, \[pc, #76\] @ 00000420 <foo\+0x420>
+000003d0 <foo\+0x3d0> ed9f9b14 vldr d9, \[pc, #80\] @ 00000428 <foo\+0x428>
+000003d4 <foo\+0x3d4> ed9f5a12 vldr s10, \[pc, #72\] @ 00000424 <foo\+0x424>
+000003d8 <foo\+0x3d8> ed9fbb14 vldr d11, \[pc, #80\] @ 00000430 <foo\+0x430>
+000003dc <foo\+0x3dc> ed9f6a15 vldr s12, \[pc, #84\] @ 00000438 <foo\+0x438>
+000003e0 <foo\+0x3e0> eddf6a15 vldr s13, \[pc, #84\] @ 0000043c <foo\+0x43c>
+000003e4 <foo\+0x3e4> ed9f7a06 vldr s14, \[pc, #24\] @ 00000404 <foo\+0x404>
+000003e8 <foo\+0x3e8> eddf7a03 vldr s15, \[pc, #12\] @ 000003fc <foo\+0x3fc>
+000003ec <foo\+0x3ec> eddf0b11 vldr d16, \[pc, #68\] @ 00000438 <foo\+0x438>
+000003f0 <foo\+0x3f0> eddf1b12 vldr d17, \[pc, #72\] @ 00000440 <foo\+0x440>
\.\.\.
000003fc <foo\+0x3fc> 0000fff0 .word 0x0000fff0
00000400 <foo\+0x400> ff000000 .word 0xff000000
.*: +file format .*arm.*
Disassembly of section .text:
-00000000 <foo> ed9f0a0e vldr s0, \[pc, #56\] ; 00000040 <foo\+0x40>
-00000004 <foo\+0x4> ed9f7a0d vldr s14, \[pc, #52\] ; 00000040 <foo\+0x40>
-00000008 <foo\+0x8> ed9fea0c vldr s28, \[pc, #48\] ; 00000040 <foo\+0x40>
-0000000c <foo\+0xc> eddffa0b vldr s31, \[pc, #44\] ; 00000040 <foo\+0x40>
-00000010 <foo\+0x10> ed9f0a0b vldr s0, \[pc, #44\] ; 00000044 <foo\+0x44>
-00000014 <foo\+0x14> ed9f7a0a vldr s14, \[pc, #40\] ; 00000044 <foo\+0x44>
-00000018 <foo\+0x18> ed9fea09 vldr s28, \[pc, #36\] ; 00000044 <foo\+0x44>
-0000001c <foo\+0x1c> eddffa08 vldr s31, \[pc, #32\] ; 00000044 <foo\+0x44>
-00000020 <foo\+0x20> ed9f0a08 vldr s0, \[pc, #32\] ; 00000048 <foo\+0x48>
-00000024 <foo\+0x24> ed9f7a07 vldr s14, \[pc, #28\] ; 00000048 <foo\+0x48>
-00000028 <foo\+0x28> ed9fea06 vldr s28, \[pc, #24\] ; 00000048 <foo\+0x48>
-0000002c <foo\+0x2c> eddffa05 vldr s31, \[pc, #20\] ; 00000048 <foo\+0x48>
-00000030 <foo\+0x30> ed9f0a05 vldr s0, \[pc, #20\] ; 0000004c <foo\+0x4c>
-00000034 <foo\+0x34> ed9f7a04 vldr s14, \[pc, #16\] ; 0000004c <foo\+0x4c>
-00000038 <foo\+0x38> ed9fea03 vldr s28, \[pc, #12\] ; 0000004c <foo\+0x4c>
-0000003c <foo\+0x3c> eddffa02 vldr s31, \[pc, #8\] ; 0000004c <foo\+0x4c>
+00000000 <foo> ed9f0a0e vldr s0, \[pc, #56\] @ 00000040 <foo\+0x40>
+00000004 <foo\+0x4> ed9f7a0d vldr s14, \[pc, #52\] @ 00000040 <foo\+0x40>
+00000008 <foo\+0x8> ed9fea0c vldr s28, \[pc, #48\] @ 00000040 <foo\+0x40>
+0000000c <foo\+0xc> eddffa0b vldr s31, \[pc, #44\] @ 00000040 <foo\+0x40>
+00000010 <foo\+0x10> ed9f0a0b vldr s0, \[pc, #44\] @ 00000044 <foo\+0x44>
+00000014 <foo\+0x14> ed9f7a0a vldr s14, \[pc, #40\] @ 00000044 <foo\+0x44>
+00000018 <foo\+0x18> ed9fea09 vldr s28, \[pc, #36\] @ 00000044 <foo\+0x44>
+0000001c <foo\+0x1c> eddffa08 vldr s31, \[pc, #32\] @ 00000044 <foo\+0x44>
+00000020 <foo\+0x20> ed9f0a08 vldr s0, \[pc, #32\] @ 00000048 <foo\+0x48>
+00000024 <foo\+0x24> ed9f7a07 vldr s14, \[pc, #28\] @ 00000048 <foo\+0x48>
+00000028 <foo\+0x28> ed9fea06 vldr s28, \[pc, #24\] @ 00000048 <foo\+0x48>
+0000002c <foo\+0x2c> eddffa05 vldr s31, \[pc, #20\] @ 00000048 <foo\+0x48>
+00000030 <foo\+0x30> ed9f0a05 vldr s0, \[pc, #20\] @ 0000004c <foo\+0x4c>
+00000034 <foo\+0x34> ed9f7a04 vldr s14, \[pc, #16\] @ 0000004c <foo\+0x4c>
+00000038 <foo\+0x38> ed9fea03 vldr s28, \[pc, #12\] @ 0000004c <foo\+0x4c>
+0000003c <foo\+0x3c> eddffa02 vldr s31, \[pc, #8\] @ 0000004c <foo\+0x4c>
00000040 <foo\+0x40> 00000000 .word 0x00000000
00000044 <foo\+0x44> ff000000 .word 0xff000000
00000048 <foo\+0x48> ffffffff .word 0xffffffff
0000004c <foo\+0x4c> 0fff0000 .word 0x0fff0000
-00000050 <foo\+0x50> ed9f0a0e vldr s0, \[pc, #56\] ; 00000090 <foo\+0x90>
-00000054 <foo\+0x54> ed9f7a0d vldr s14, \[pc, #52\] ; 00000090 <foo\+0x90>
-00000058 <foo\+0x58> ed9fea0c vldr s28, \[pc, #48\] ; 00000090 <foo\+0x90>
-0000005c <foo\+0x5c> eddffa0b vldr s31, \[pc, #44\] ; 00000090 <foo\+0x90>
-00000060 <foo\+0x60> ed9f0a0b vldr s0, \[pc, #44\] ; 00000094 <foo\+0x94>
-00000064 <foo\+0x64> ed9f7a0a vldr s14, \[pc, #40\] ; 00000094 <foo\+0x94>
-00000068 <foo\+0x68> ed9fea09 vldr s28, \[pc, #36\] ; 00000094 <foo\+0x94>
-0000006c <foo\+0x6c> eddffa08 vldr s31, \[pc, #32\] ; 00000094 <foo\+0x94>
-00000070 <foo\+0x70> ed9f0a08 vldr s0, \[pc, #32\] ; 00000098 <foo\+0x98>
-00000074 <foo\+0x74> ed9f7a07 vldr s14, \[pc, #28\] ; 00000098 <foo\+0x98>
-00000078 <foo\+0x78> ed9fea06 vldr s28, \[pc, #24\] ; 00000098 <foo\+0x98>
-0000007c <foo\+0x7c> eddffa05 vldr s31, \[pc, #20\] ; 00000098 <foo\+0x98>
-00000080 <foo\+0x80> ed9f0a05 vldr s0, \[pc, #20\] ; 0000009c <foo\+0x9c>
-00000084 <foo\+0x84> ed9f7a04 vldr s14, \[pc, #16\] ; 0000009c <foo\+0x9c>
-00000088 <foo\+0x88> ed9fea03 vldr s28, \[pc, #12\] ; 0000009c <foo\+0x9c>
-0000008c <foo\+0x8c> eddffa02 vldr s31, \[pc, #8\] ; 0000009c <foo\+0x9c>
+00000050 <foo\+0x50> ed9f0a0e vldr s0, \[pc, #56\] @ 00000090 <foo\+0x90>
+00000054 <foo\+0x54> ed9f7a0d vldr s14, \[pc, #52\] @ 00000090 <foo\+0x90>
+00000058 <foo\+0x58> ed9fea0c vldr s28, \[pc, #48\] @ 00000090 <foo\+0x90>
+0000005c <foo\+0x5c> eddffa0b vldr s31, \[pc, #44\] @ 00000090 <foo\+0x90>
+00000060 <foo\+0x60> ed9f0a0b vldr s0, \[pc, #44\] @ 00000094 <foo\+0x94>
+00000064 <foo\+0x64> ed9f7a0a vldr s14, \[pc, #40\] @ 00000094 <foo\+0x94>
+00000068 <foo\+0x68> ed9fea09 vldr s28, \[pc, #36\] @ 00000094 <foo\+0x94>
+0000006c <foo\+0x6c> eddffa08 vldr s31, \[pc, #32\] @ 00000094 <foo\+0x94>
+00000070 <foo\+0x70> ed9f0a08 vldr s0, \[pc, #32\] @ 00000098 <foo\+0x98>
+00000074 <foo\+0x74> ed9f7a07 vldr s14, \[pc, #28\] @ 00000098 <foo\+0x98>
+00000078 <foo\+0x78> ed9fea06 vldr s28, \[pc, #24\] @ 00000098 <foo\+0x98>
+0000007c <foo\+0x7c> eddffa05 vldr s31, \[pc, #20\] @ 00000098 <foo\+0x98>
+00000080 <foo\+0x80> ed9f0a05 vldr s0, \[pc, #20\] @ 0000009c <foo\+0x9c>
+00000084 <foo\+0x84> ed9f7a04 vldr s14, \[pc, #16\] @ 0000009c <foo\+0x9c>
+00000088 <foo\+0x88> ed9fea03 vldr s28, \[pc, #12\] @ 0000009c <foo\+0x9c>
+0000008c <foo\+0x8c> eddffa02 vldr s31, \[pc, #8\] @ 0000009c <foo\+0x9c>
00000090 <foo\+0x90> 00000000 .word 0x00000000
00000094 <foo\+0x94> 00ff0000 .word 0x00ff0000
00000098 <foo\+0x98> ff00ffff .word 0xff00ffff
0000009c <foo\+0x9c> 00fff000 .word 0x00fff000
-000000a0 <foo\+0xa0> 0d9f0a0e vldreq s0, \[pc, #56\] ; 000000e0 <foo\+0xe0>
-000000a4 <foo\+0xa4> 0d9f7a0d vldreq s14, \[pc, #52\] ; 000000e0 <foo\+0xe0>
-000000a8 <foo\+0xa8> 0d9fea0c vldreq s28, \[pc, #48\] ; 000000e0 <foo\+0xe0>
-000000ac <foo\+0xac> 0ddffa0b vldreq s31, \[pc, #44\] ; 000000e0 <foo\+0xe0>
-000000b0 <foo\+0xb0> 0d9f0a0b vldreq s0, \[pc, #44\] ; 000000e4 <foo\+0xe4>
-000000b4 <foo\+0xb4> 0d9f7a0a vldreq s14, \[pc, #40\] ; 000000e4 <foo\+0xe4>
-000000b8 <foo\+0xb8> 0d9fea09 vldreq s28, \[pc, #36\] ; 000000e4 <foo\+0xe4>
-000000bc <foo\+0xbc> 0ddffa08 vldreq s31, \[pc, #32\] ; 000000e4 <foo\+0xe4>
-000000c0 <foo\+0xc0> 0d9f0a08 vldreq s0, \[pc, #32\] ; 000000e8 <foo\+0xe8>
-000000c4 <foo\+0xc4> 0d9f7a07 vldreq s14, \[pc, #28\] ; 000000e8 <foo\+0xe8>
-000000c8 <foo\+0xc8> 0d9fea06 vldreq s28, \[pc, #24\] ; 000000e8 <foo\+0xe8>
-000000cc <foo\+0xcc> 0ddffa05 vldreq s31, \[pc, #20\] ; 000000e8 <foo\+0xe8>
-000000d0 <foo\+0xd0> 0d9f0a05 vldreq s0, \[pc, #20\] ; 000000ec <foo\+0xec>
-000000d4 <foo\+0xd4> 0d9f7a04 vldreq s14, \[pc, #16\] ; 000000ec <foo\+0xec>
-000000d8 <foo\+0xd8> 0d9fea03 vldreq s28, \[pc, #12\] ; 000000ec <foo\+0xec>
-000000dc <foo\+0xdc> 0ddffa02 vldreq s31, \[pc, #8\] ; 000000ec <foo\+0xec>
+000000a0 <foo\+0xa0> 0d9f0a0e vldreq s0, \[pc, #56\] @ 000000e0 <foo\+0xe0>
+000000a4 <foo\+0xa4> 0d9f7a0d vldreq s14, \[pc, #52\] @ 000000e0 <foo\+0xe0>
+000000a8 <foo\+0xa8> 0d9fea0c vldreq s28, \[pc, #48\] @ 000000e0 <foo\+0xe0>
+000000ac <foo\+0xac> 0ddffa0b vldreq s31, \[pc, #44\] @ 000000e0 <foo\+0xe0>
+000000b0 <foo\+0xb0> 0d9f0a0b vldreq s0, \[pc, #44\] @ 000000e4 <foo\+0xe4>
+000000b4 <foo\+0xb4> 0d9f7a0a vldreq s14, \[pc, #40\] @ 000000e4 <foo\+0xe4>
+000000b8 <foo\+0xb8> 0d9fea09 vldreq s28, \[pc, #36\] @ 000000e4 <foo\+0xe4>
+000000bc <foo\+0xbc> 0ddffa08 vldreq s31, \[pc, #32\] @ 000000e4 <foo\+0xe4>
+000000c0 <foo\+0xc0> 0d9f0a08 vldreq s0, \[pc, #32\] @ 000000e8 <foo\+0xe8>
+000000c4 <foo\+0xc4> 0d9f7a07 vldreq s14, \[pc, #28\] @ 000000e8 <foo\+0xe8>
+000000c8 <foo\+0xc8> 0d9fea06 vldreq s28, \[pc, #24\] @ 000000e8 <foo\+0xe8>
+000000cc <foo\+0xcc> 0ddffa05 vldreq s31, \[pc, #20\] @ 000000e8 <foo\+0xe8>
+000000d0 <foo\+0xd0> 0d9f0a05 vldreq s0, \[pc, #20\] @ 000000ec <foo\+0xec>
+000000d4 <foo\+0xd4> 0d9f7a04 vldreq s14, \[pc, #16\] @ 000000ec <foo\+0xec>
+000000d8 <foo\+0xd8> 0d9fea03 vldreq s28, \[pc, #12\] @ 000000ec <foo\+0xec>
+000000dc <foo\+0xdc> 0ddffa02 vldreq s31, \[pc, #8\] @ 000000ec <foo\+0xec>
000000e0 <foo\+0xe0> 00000000 .word 0x00000000
000000e4 <foo\+0xe4> 0000ff00 .word 0x0000ff00
000000e8 <foo\+0xe8> ffff00ff .word 0xffff00ff
000000ec <foo\+0xec> 000fff00 .word 0x000fff00
-000000f0 <foo\+0xf0> 4d9f0a0e vldrmi s0, \[pc, #56\] ; 00000130 <foo\+0x130>
-000000f4 <foo\+0xf4> 4d9f7a0d vldrmi s14, \[pc, #52\] ; 00000130 <foo\+0x130>
-000000f8 <foo\+0xf8> 4d9fea0c vldrmi s28, \[pc, #48\] ; 00000130 <foo\+0x130>
-000000fc <foo\+0xfc> 4ddffa0b vldrmi s31, \[pc, #44\] ; 00000130 <foo\+0x130>
-00000100 <foo\+0x100> 4d9f0a0b vldrmi s0, \[pc, #44\] ; 00000134 <foo\+0x134>
-00000104 <foo\+0x104> 4d9f7a0a vldrmi s14, \[pc, #40\] ; 00000134 <foo\+0x134>
-00000108 <foo\+0x108> 4d9fea09 vldrmi s28, \[pc, #36\] ; 00000134 <foo\+0x134>
-0000010c <foo\+0x10c> 4ddffa08 vldrmi s31, \[pc, #32\] ; 00000134 <foo\+0x134>
-00000110 <foo\+0x110> 4d9f0a08 vldrmi s0, \[pc, #32\] ; 00000138 <foo\+0x138>
-00000114 <foo\+0x114> 4d9f7a07 vldrmi s14, \[pc, #28\] ; 00000138 <foo\+0x138>
-00000118 <foo\+0x118> 4d9fea06 vldrmi s28, \[pc, #24\] ; 00000138 <foo\+0x138>
-0000011c <foo\+0x11c> 4ddffa05 vldrmi s31, \[pc, #20\] ; 00000138 <foo\+0x138>
-00000120 <foo\+0x120> 4d9f0a05 vldrmi s0, \[pc, #20\] ; 0000013c <foo\+0x13c>
-00000124 <foo\+0x124> 4d9f7a04 vldrmi s14, \[pc, #16\] ; 0000013c <foo\+0x13c>
-00000128 <foo\+0x128> 4d9fea03 vldrmi s28, \[pc, #12\] ; 0000013c <foo\+0x13c>
-0000012c <foo\+0x12c> 4ddffa02 vldrmi s31, \[pc, #8\] ; 0000013c <foo\+0x13c>
+000000f0 <foo\+0xf0> 4d9f0a0e vldrmi s0, \[pc, #56\] @ 00000130 <foo\+0x130>
+000000f4 <foo\+0xf4> 4d9f7a0d vldrmi s14, \[pc, #52\] @ 00000130 <foo\+0x130>
+000000f8 <foo\+0xf8> 4d9fea0c vldrmi s28, \[pc, #48\] @ 00000130 <foo\+0x130>
+000000fc <foo\+0xfc> 4ddffa0b vldrmi s31, \[pc, #44\] @ 00000130 <foo\+0x130>
+00000100 <foo\+0x100> 4d9f0a0b vldrmi s0, \[pc, #44\] @ 00000134 <foo\+0x134>
+00000104 <foo\+0x104> 4d9f7a0a vldrmi s14, \[pc, #40\] @ 00000134 <foo\+0x134>
+00000108 <foo\+0x108> 4d9fea09 vldrmi s28, \[pc, #36\] @ 00000134 <foo\+0x134>
+0000010c <foo\+0x10c> 4ddffa08 vldrmi s31, \[pc, #32\] @ 00000134 <foo\+0x134>
+00000110 <foo\+0x110> 4d9f0a08 vldrmi s0, \[pc, #32\] @ 00000138 <foo\+0x138>
+00000114 <foo\+0x114> 4d9f7a07 vldrmi s14, \[pc, #28\] @ 00000138 <foo\+0x138>
+00000118 <foo\+0x118> 4d9fea06 vldrmi s28, \[pc, #24\] @ 00000138 <foo\+0x138>
+0000011c <foo\+0x11c> 4ddffa05 vldrmi s31, \[pc, #20\] @ 00000138 <foo\+0x138>
+00000120 <foo\+0x120> 4d9f0a05 vldrmi s0, \[pc, #20\] @ 0000013c <foo\+0x13c>
+00000124 <foo\+0x124> 4d9f7a04 vldrmi s14, \[pc, #16\] @ 0000013c <foo\+0x13c>
+00000128 <foo\+0x128> 4d9fea03 vldrmi s28, \[pc, #12\] @ 0000013c <foo\+0x13c>
+0000012c <foo\+0x12c> 4ddffa02 vldrmi s31, \[pc, #8\] @ 0000013c <foo\+0x13c>
00000130 <foo\+0x130> 00000000 .word 0x00000000
00000134 <foo\+0x134> 000000ff .word 0x000000ff
00000138 <foo\+0x138> ffffff00 .word 0xffffff00
00000144 <foo\+0x144> f280ee30 vmov.i64 d14, #0x0000000000000000
00000148 <foo\+0x148> f2c0ce30 vmov.i64 d28, #0x0000000000000000
0000014c <foo\+0x14c> f2c0fe30 vmov.i64 d31, #0x0000000000000000
-00000150 <foo\+0x150> ed9f0b0a vldr d0, \[pc, #40\] ; 00000180 <foo\+0x180>
-00000154 <foo\+0x154> ed9feb09 vldr d14, \[pc, #36\] ; 00000180 <foo\+0x180>
-00000158 <foo\+0x158> eddfcb08 vldr d28, \[pc, #32\] ; 00000180 <foo\+0x180>
-0000015c <foo\+0x15c> eddffb07 vldr d31, \[pc, #28\] ; 00000180 <foo\+0x180>
+00000150 <foo\+0x150> ed9f0b0a vldr d0, \[pc, #40\] @ 00000180 <foo\+0x180>
+00000154 <foo\+0x154> ed9feb09 vldr d14, \[pc, #36\] @ 00000180 <foo\+0x180>
+00000158 <foo\+0x158> eddfcb08 vldr d28, \[pc, #32\] @ 00000180 <foo\+0x180>
+0000015c <foo\+0x15c> eddffb07 vldr d31, \[pc, #28\] @ 00000180 <foo\+0x180>
00000160 <foo\+0x160> f3870e3f vmov.i64 d0, #0xffffffffffffffff
00000164 <foo\+0x164> f387ee3f vmov.i64 d14, #0xffffffffffffffff
00000168 <foo\+0x168> f3c7ce3f vmov.i64 d28, #0xffffffffffffffff
0000016c <foo\+0x16c> f3c7fe3f vmov.i64 d31, #0xffffffffffffffff
-00000170 <foo\+0x170> ed9f0b04 vldr d0, \[pc, #16\] ; 00000188 <foo\+0x188>
-00000174 <foo\+0x174> ed9feb03 vldr d14, \[pc, #12\] ; 00000188 <foo\+0x188>
-00000178 <foo\+0x178> eddfcb02 vldr d28, \[pc, #8\] ; 00000188 <foo\+0x188>
-0000017c <foo\+0x17c> eddffb01 vldr d31, \[pc, #4\] ; 00000188 <foo\+0x188>
+00000170 <foo\+0x170> ed9f0b04 vldr d0, \[pc, #16\] @ 00000188 <foo\+0x188>
+00000174 <foo\+0x174> ed9feb03 vldr d14, \[pc, #12\] @ 00000188 <foo\+0x188>
+00000178 <foo\+0x178> eddfcb02 vldr d28, \[pc, #8\] @ 00000188 <foo\+0x188>
+0000017c <foo\+0x17c> eddffb01 vldr d31, \[pc, #4\] @ 00000188 <foo\+0x188>
00000180 <foo\+0x180> 00000000 .word 0x00000000
00000184 <foo\+0x184> ca000000 .word 0xca000000
00000188 <foo\+0x188> 00000000 .word 0x00000000
000001b4 <foo\+0x1b4> f280ee39 vmov.i64 d14, #0x00000000ff0000ff
000001b8 <foo\+0x1b8> f2c0ce39 vmov.i64 d28, #0x00000000ff0000ff
000001bc <foo\+0x1bc> f2c0fe39 vmov.i64 d31, #0x00000000ff0000ff
-000001c0 <foo\+0x1c0> ed9f0b02 vldr d0, \[pc, #8\] ; 000001d0 <foo\+0x1d0>
-000001c4 <foo\+0x1c4> ed9feb01 vldr d14, \[pc, #4\] ; 000001d0 <foo\+0x1d0>
-000001c8 <foo\+0x1c8> eddfcb00 vldr d28, \[pc\] ; 000001d0 <foo\+0x1d0>
-000001cc <foo\+0x1cc> ed5ffb01 vldr d31, \[pc, #-4\] ; 000001d0 <foo\+0x1d0>
+000001c0 <foo\+0x1c0> ed9f0b02 vldr d0, \[pc, #8\] @ 000001d0 <foo\+0x1d0>
+000001c4 <foo\+0x1c4> ed9feb01 vldr d14, \[pc, #4\] @ 000001d0 <foo\+0x1d0>
+000001c8 <foo\+0x1c8> eddfcb00 vldr d28, \[pc\] @ 000001d0 <foo\+0x1d0>
+000001cc <foo\+0x1cc> ed5ffb01 vldr d31, \[pc, #-4\] @ 000001d0 <foo\+0x1d0>
000001d0 <foo\+0x1d0> 00000000 .word 0x00000000
000001d4 <foo\+0x1d4> 00fff000 .word 0x00fff000
000001d8 <foo\+0x1d8> f2800e30 vmov.i64 d0, #0x0000000000000000
000001fc <foo\+0x1fc> f280ee3d vmov.i64 d14, #0x00000000ffff00ff
00000200 <foo\+0x200> f2c0ce3d vmov.i64 d28, #0x00000000ffff00ff
00000204 <foo\+0x204> f2c0fe3d vmov.i64 d31, #0x00000000ffff00ff
-00000208 <foo\+0x208> 0d9f0b02 vldreq d0, \[pc, #8\] ; 00000218 <foo\+0x218>
-0000020c <foo\+0x20c> 0d9feb01 vldreq d14, \[pc, #4\] ; 00000218 <foo\+0x218>
-00000210 <foo\+0x210> 0ddfcb00 vldreq d28, \[pc\] ; 00000218 <foo\+0x218>
-00000214 <foo\+0x214> 0d5ffb01 vldreq d31, \[pc, #-4\] ; 00000218 <foo\+0x218>
+00000208 <foo\+0x208> 0d9f0b02 vldreq d0, \[pc, #8\] @ 00000218 <foo\+0x218>
+0000020c <foo\+0x20c> 0d9feb01 vldreq d14, \[pc, #4\] @ 00000218 <foo\+0x218>
+00000210 <foo\+0x210> 0ddfcb00 vldreq d28, \[pc\] @ 00000218 <foo\+0x218>
+00000214 <foo\+0x214> 0d5ffb01 vldreq d31, \[pc, #-4\] @ 00000218 <foo\+0x218>
00000218 <foo\+0x218> 00000000 .word 0x00000000
0000021c <foo\+0x21c> 000fff00 .word 0x000fff00
00000220 <foo\+0x220> f2800e30 vmov.i64 d0, #0x0000000000000000
00000284 <foo\+0x284> f387ee3f vmov.i64 d14, #0xffffffffffffffff
00000288 <foo\+0x288> f3c7ce3f vmov.i64 d28, #0xffffffffffffffff
0000028c <foo\+0x28c> f3c7fe3f vmov.i64 d31, #0xffffffffffffffff
-00000290 <foo\+0x290> ed9f0b02 vldr d0, \[pc, #8\] ; 000002a0 <foo\+0x2a0>
-00000294 <foo\+0x294> ed9feb01 vldr d14, \[pc, #4\] ; 000002a0 <foo\+0x2a0>
-00000298 <foo\+0x298> eddfcb00 vldr d28, \[pc\] ; 000002a0 <foo\+0x2a0>
-0000029c <foo\+0x29c> ed5ffb01 vldr d31, \[pc, #-4\] ; 000002a0 <foo\+0x2a0>
+00000290 <foo\+0x290> ed9f0b02 vldr d0, \[pc, #8\] @ 000002a0 <foo\+0x2a0>
+00000294 <foo\+0x294> ed9feb01 vldr d14, \[pc, #4\] @ 000002a0 <foo\+0x2a0>
+00000298 <foo\+0x298> eddfcb00 vldr d28, \[pc\] @ 000002a0 <foo\+0x2a0>
+0000029c <foo\+0x29c> ed5ffb01 vldr d31, \[pc, #-4\] @ 000002a0 <foo\+0x2a0>
000002a0 <foo\+0x2a0> 0fff0000 .word 0x0fff0000
000002a4 <foo\+0x2a4> 00000000 .word 0x00000000
000002a8 <foo\+0x2a8> f2800e30 vmov.i64 d0, #0x0000000000000000
000002ac <foo\+0x2ac> f280ee30 vmov.i64 d14, #0x0000000000000000
000002b0 <foo\+0x2b0> f2c0ce30 vmov.i64 d28, #0x0000000000000000
000002b4 <foo\+0x2b4> f2c0fe30 vmov.i64 d31, #0x0000000000000000
-000002b8 <foo\+0x2b8> ed9f0b0a vldr d0, \[pc, #40\] ; 000002e8 <foo\+0x2e8>
-000002bc <foo\+0x2bc> ed9feb09 vldr d14, \[pc, #36\] ; 000002e8 <foo\+0x2e8>
-000002c0 <foo\+0x2c0> eddfcb08 vldr d28, \[pc, #32\] ; 000002e8 <foo\+0x2e8>
-000002c4 <foo\+0x2c4> eddffb07 vldr d31, \[pc, #28\] ; 000002e8 <foo\+0x2e8>
-000002c8 <foo\+0x2c8> ed9f0b08 vldr d0, \[pc, #32\] ; 000002f0 <foo\+0x2f0>
-000002cc <foo\+0x2cc> ed9feb07 vldr d14, \[pc, #28\] ; 000002f0 <foo\+0x2f0>
-000002d0 <foo\+0x2d0> eddfcb06 vldr d28, \[pc, #24\] ; 000002f0 <foo\+0x2f0>
-000002d4 <foo\+0x2d4> eddffb05 vldr d31, \[pc, #20\] ; 000002f0 <foo\+0x2f0>
-000002d8 <foo\+0x2d8> ed9f0b06 vldr d0, \[pc, #24\] ; 000002f8 <foo\+0x2f8>
-000002dc <foo\+0x2dc> ed9feb05 vldr d14, \[pc, #20\] ; 000002f8 <foo\+0x2f8>
-000002e0 <foo\+0x2e0> eddfcb04 vldr d28, \[pc, #16\] ; 000002f8 <foo\+0x2f8>
-000002e4 <foo\+0x2e4> eddffb03 vldr d31, \[pc, #12\] ; 000002f8 <foo\+0x2f8>
+000002b8 <foo\+0x2b8> ed9f0b0a vldr d0, \[pc, #40\] @ 000002e8 <foo\+0x2e8>
+000002bc <foo\+0x2bc> ed9feb09 vldr d14, \[pc, #36\] @ 000002e8 <foo\+0x2e8>
+000002c0 <foo\+0x2c0> eddfcb08 vldr d28, \[pc, #32\] @ 000002e8 <foo\+0x2e8>
+000002c4 <foo\+0x2c4> eddffb07 vldr d31, \[pc, #28\] @ 000002e8 <foo\+0x2e8>
+000002c8 <foo\+0x2c8> ed9f0b08 vldr d0, \[pc, #32\] @ 000002f0 <foo\+0x2f0>
+000002cc <foo\+0x2cc> ed9feb07 vldr d14, \[pc, #28\] @ 000002f0 <foo\+0x2f0>
+000002d0 <foo\+0x2d0> eddfcb06 vldr d28, \[pc, #24\] @ 000002f0 <foo\+0x2f0>
+000002d4 <foo\+0x2d4> eddffb05 vldr d31, \[pc, #20\] @ 000002f0 <foo\+0x2f0>
+000002d8 <foo\+0x2d8> ed9f0b06 vldr d0, \[pc, #24\] @ 000002f8 <foo\+0x2f8>
+000002dc <foo\+0x2dc> ed9feb05 vldr d14, \[pc, #20\] @ 000002f8 <foo\+0x2f8>
+000002e0 <foo\+0x2e0> eddfcb04 vldr d28, \[pc, #16\] @ 000002f8 <foo\+0x2f8>
+000002e4 <foo\+0x2e4> eddffb03 vldr d31, \[pc, #12\] @ 000002f8 <foo\+0x2f8>
000002e8 <foo\+0x2e8> 000ff000 .word 0x000ff000
000002ec <foo\+0x2ec> 00000000 .word 0x00000000
000002f0 <foo\+0x2f0> 0ff00fff .word 0x0ff00fff
00000324 <foo\+0x324> f385ee30 vmov.i64 d14, #0xffff00ff00000000
00000328 <foo\+0x328> f3c5ce30 vmov.i64 d28, #0xffff00ff00000000
0000032c <foo\+0x32c> f3c5fe30 vmov.i64 d31, #0xffff00ff00000000
-00000330 <foo\+0x330> 0d9f0b02 vldreq d0, \[pc, #8\] ; 00000340 <foo\+0x340>
-00000334 <foo\+0x334> 0d9feb01 vldreq d14, \[pc, #4\] ; 00000340 <foo\+0x340>
-00000338 <foo\+0x338> 0ddfcb00 vldreq d28, \[pc\] ; 00000340 <foo\+0x340>
-0000033c <foo\+0x33c> 0d5ffb01 vldreq d31, \[pc, #-4\] ; 00000340 <foo\+0x340>
+00000330 <foo\+0x330> 0d9f0b02 vldreq d0, \[pc, #8\] @ 00000340 <foo\+0x340>
+00000334 <foo\+0x334> 0d9feb01 vldreq d14, \[pc, #4\] @ 00000340 <foo\+0x340>
+00000338 <foo\+0x338> 0ddfcb00 vldreq d28, \[pc\] @ 00000340 <foo\+0x340>
+0000033c <foo\+0x33c> 0d5ffb01 vldreq d31, \[pc, #-4\] @ 00000340 <foo\+0x340>
00000340 <foo\+0x340> 000fff00 .word 0x000fff00
00000344 <foo\+0x344> 00000000 .word 0x00000000
00000348 <foo\+0x348> f2800e30 vmov.i64 d0, #0x0000000000000000
0000036c <foo\+0x36c> f386ee30 vmov.i64 d14, #0xffffff0000000000
00000370 <foo\+0x370> f3c6ce30 vmov.i64 d28, #0xffffff0000000000
00000374 <foo\+0x374> f3c6fe30 vmov.i64 d31, #0xffffff0000000000
-00000378 <foo\+0x378> 4d9f0b02 vldrmi d0, \[pc, #8\] ; 00000388 <foo\+0x388>
-0000037c <foo\+0x37c> 4d9feb01 vldrmi d14, \[pc, #4\] ; 00000388 <foo\+0x388>
-00000380 <foo\+0x380> 4ddfcb00 vldrmi d28, \[pc\] ; 00000388 <foo\+0x388>
-00000384 <foo\+0x384> 4d5ffb01 vldrmi d31, \[pc, #-4\] ; 00000388 <foo\+0x388>
+00000378 <foo\+0x378> 4d9f0b02 vldrmi d0, \[pc, #8\] @ 00000388 <foo\+0x388>
+0000037c <foo\+0x37c> 4d9feb01 vldrmi d14, \[pc, #4\] @ 00000388 <foo\+0x388>
+00000380 <foo\+0x380> 4ddfcb00 vldrmi d28, \[pc\] @ 00000388 <foo\+0x388>
+00000384 <foo\+0x384> 4d5ffb01 vldrmi d31, \[pc, #-4\] @ 00000388 <foo\+0x388>
00000388 <foo\+0x388> 0000fff0 .word 0x0000fff0
0000038c <foo\+0x38c> 00000000 .word 0x00000000
-00000390 <foo\+0x390> ed9f1b00 vldr d1, \[pc\] ; 00000398 <foo\+0x398>
+00000390 <foo\+0x390> ed9f1b00 vldr d1, \[pc\] @ 00000398 <foo\+0x398>
00000394 <foo\+0x394> 00000000 .word 0x00000000
00000398 <foo\+0x398> 0000fff0 .word 0x0000fff0
0000039c <foo\+0x39c> 00000000 .word 0x00000000
000003a0 <foo\+0x3a0> e2810000 add r0, r1, #0
-000003a4 <foo\+0x3a4> ed1f1b01 vldr d1, \[pc, #-4\] ; 000003a8 <foo\+0x3a8>
+000003a4 <foo\+0x3a4> ed1f1b01 vldr d1, \[pc, #-4\] @ 000003a8 <foo\+0x3a8>
000003a8 <foo\+0x3a8> 0000fff0 .word 0x0000fff0
000003ac <foo\+0x3ac> 00000000 .word 0x00000000
-000003b0 <foo\+0x3b0> ed9f1b10 vldr d1, \[pc, #64\] ; 000003f8 <foo\+0x3f8>
-000003b4 <foo\+0x3b4> ed9f1a11 vldr s2, \[pc, #68\] ; 00000400 <foo\+0x400>
-000003b8 <foo\+0x3b8> ed9f3b12 vldr d3, \[pc, #72\] ; 00000408 <foo\+0x408>
-000003bc <foo\+0x3bc> ed9f2a10 vldr s4, \[pc, #64\] ; 00000404 <foo\+0x404>
-000003c0 <foo\+0x3c0> ed9f5b10 vldr d5, \[pc, #64\] ; 00000408 <foo\+0x408>
-000003c4 <foo\+0x3c4> ed9f6b11 vldr d6, \[pc, #68\] ; 00000410 <foo\+0x410>
-000003c8 <foo\+0x3c8> ed9f7b12 vldr d7, \[pc, #72\] ; 00000418 <foo\+0x418>
-000003cc <foo\+0x3cc> ed9f4a13 vldr s8, \[pc, #76\] ; 00000420 <foo\+0x420>
-000003d0 <foo\+0x3d0> ed9f9b14 vldr d9, \[pc, #80\] ; 00000428 <foo\+0x428>
-000003d4 <foo\+0x3d4> ed9f5a12 vldr s10, \[pc, #72\] ; 00000424 <foo\+0x424>
-000003d8 <foo\+0x3d8> ed9fbb14 vldr d11, \[pc, #80\] ; 00000430 <foo\+0x430>
-000003dc <foo\+0x3dc> ed9f6a15 vldr s12, \[pc, #84\] ; 00000438 <foo\+0x438>
-000003e0 <foo\+0x3e0> eddf6a15 vldr s13, \[pc, #84\] ; 0000043c <foo\+0x43c>
-000003e4 <foo\+0x3e4> ed9f7a06 vldr s14, \[pc, #24\] ; 00000404 <foo\+0x404>
-000003e8 <foo\+0x3e8> eddf7a02 vldr s15, \[pc, #8\] ; 000003f8 <foo\+0x3f8>
-000003ec <foo\+0x3ec> eddf0b13 vldr d16, \[pc, #76\] ; 00000440 <foo\+0x440>
-000003f0 <foo\+0x3f0> eddf1b14 vldr d17, \[pc, #80\] ; 00000448 <foo\+0x448>
+000003b0 <foo\+0x3b0> ed9f1b10 vldr d1, \[pc, #64\] @ 000003f8 <foo\+0x3f8>
+000003b4 <foo\+0x3b4> ed9f1a11 vldr s2, \[pc, #68\] @ 00000400 <foo\+0x400>
+000003b8 <foo\+0x3b8> ed9f3b12 vldr d3, \[pc, #72\] @ 00000408 <foo\+0x408>
+000003bc <foo\+0x3bc> ed9f2a10 vldr s4, \[pc, #64\] @ 00000404 <foo\+0x404>
+000003c0 <foo\+0x3c0> ed9f5b10 vldr d5, \[pc, #64\] @ 00000408 <foo\+0x408>
+000003c4 <foo\+0x3c4> ed9f6b11 vldr d6, \[pc, #68\] @ 00000410 <foo\+0x410>
+000003c8 <foo\+0x3c8> ed9f7b12 vldr d7, \[pc, #72\] @ 00000418 <foo\+0x418>
+000003cc <foo\+0x3cc> ed9f4a13 vldr s8, \[pc, #76\] @ 00000420 <foo\+0x420>
+000003d0 <foo\+0x3d0> ed9f9b14 vldr d9, \[pc, #80\] @ 00000428 <foo\+0x428>
+000003d4 <foo\+0x3d4> ed9f5a12 vldr s10, \[pc, #72\] @ 00000424 <foo\+0x424>
+000003d8 <foo\+0x3d8> ed9fbb14 vldr d11, \[pc, #80\] @ 00000430 <foo\+0x430>
+000003dc <foo\+0x3dc> ed9f6a15 vldr s12, \[pc, #84\] @ 00000438 <foo\+0x438>
+000003e0 <foo\+0x3e0> eddf6a15 vldr s13, \[pc, #84\] @ 0000043c <foo\+0x43c>
+000003e4 <foo\+0x3e4> ed9f7a06 vldr s14, \[pc, #24\] @ 00000404 <foo\+0x404>
+000003e8 <foo\+0x3e8> eddf7a02 vldr s15, \[pc, #8\] @ 000003f8 <foo\+0x3f8>
+000003ec <foo\+0x3ec> eddf0b13 vldr d16, \[pc, #76\] @ 00000440 <foo\+0x440>
+000003f0 <foo\+0x3f0> eddf1b14 vldr d17, \[pc, #80\] @ 00000448 <foo\+0x448>
000003f4 <foo\+0x3f4> 00000000 .word 0x00000000
000003f8 <foo\+0x3f8> 0000fff0 .word 0x0000fff0
000003fc <foo\+0x3fc> 00000000 .word 0x00000000
Disassembly of section .text:
0[0-9a-f]+ <[^>]+> bf00 nop
-0[0-9a-f]+ <[^>]+> ed9f 0b03 vldr d0, \[pc, #12\] ; 00000010 <float>
-0[0-9a-f]+ <[^>]+> ed9f 0b02 vldr d0, \[pc, #8\] ; 00000010 <float>
+0[0-9a-f]+ <[^>]+> ed9f 0b03 vldr d0, \[pc, #12\] @ 00000010 <float>
+0[0-9a-f]+ <[^>]+> ed9f 0b02 vldr d0, \[pc, #8\] @ 00000010 <float>
0[0-9a-f]+ <[^>]+> bf00 nop
0[0-9a-f]+ <[^>]+> bf00 nop
0[0-9a-f]+ <[^>]+> bf00 nop
Disassembly of section .text:
0+000 <global_data> 00000007 andeq r0, r0, r7
0: ARM_32 global_data
-0+004 <global_sym> e1a00000 nop ; \(mov r0, r0\)
-0+008 <global_sym\+0x4> e1a00000 nop ; \(mov r0, r0\)
-0+00c <global_sym\+0x8> e1a00000 nop ; \(mov r0, r0\)
+0+004 <global_sym> e1a00000 nop @ \(mov r0, r0\)
+0+008 <global_sym\+0x4> e1a00000 nop @ \(mov r0, r0\)
+0+00c <global_sym\+0x8> e1a00000 nop @ \(mov r0, r0\)
0+010 <global_sym\+0xc> eafffffb b f+ff8 <global_sym\+0xf+ff4>
10: ARM_26D global_sym-0x4
0+014 <global_sym\+0x10> ebfffffa bl f+ff4 <global_sym\+0xf+ff0>
0+024 <global_sym\+0x20> 0afffff6 beq 0+004 <global_sym>
0+028 <global_sym\+0x24> eafffff5 b 0+004 <global_sym>
0+02c <global_sym\+0x28> ebfffff4 bl 0+004 <global_sym>
-0+030 <global_sym\+0x2c> e51f0034 ldr r0, \[pc, #-52\] ; 0+004 <global_sym>
-0+034 <global_sym\+0x30> e51f0038 ldr r0, \[pc, #-56\] ; 0+004 <global_sym>
-0+038 <global_sym\+0x34> e51f003c ldr r0, \[pc, #-60\] ; 0+004 <global_sym>
+0+030 <global_sym\+0x2c> e51f0034 ldr r0, \[pc, #-52\] @ 0+004 <global_sym>
+0+034 <global_sym\+0x30> e51f0038 ldr r0, \[pc, #-56\] @ 0+004 <global_sym>
+0+038 <global_sym\+0x34> e51f003c ldr r0, \[pc, #-60\] @ 0+004 <global_sym>
0+14c <[^>]*> e1720004 ? cmn r2, r4
0+150 <[^>]*> e1750287 ? cmn r5, r7, lsl #5
0+154 <[^>]*> e1710113 ? cmn r1, r3, lsl r1
-0+158 <[^>]*> e330f00a ? teq r0, #10 ; <UNPREDICTABLE>
-0+15c <[^>]*> e132f004 ? teq r2, r4 ; <UNPREDICTABLE>
-0+160 <[^>]*> e135f287 ? teq r5, r7, lsl #5 ; <UNPREDICTABLE>
-0+164 <[^>]*> e131f113 ? teq r1, r3, lsl r1 ; <UNPREDICTABLE>
-0+168 <[^>]*> e370f00a ? cmn r0, #10 ; <UNPREDICTABLE>
-0+16c <[^>]*> e172f004 ? cmn r2, r4 ; <UNPREDICTABLE>
-0+170 <[^>]*> e175f287 ? cmn r5, r7, lsl #5 ; <UNPREDICTABLE>
-0+174 <[^>]*> e171f113 ? cmn r1, r3, lsl r1 ; <UNPREDICTABLE>
-0+178 <[^>]*> e350f00a ? cmp r0, #10 ; <UNPREDICTABLE>
-0+17c <[^>]*> e152f004 ? cmp r2, r4 ; <UNPREDICTABLE>
-0+180 <[^>]*> e155f287 ? cmp r5, r7, lsl #5 ; <UNPREDICTABLE>
-0+184 <[^>]*> e151f113 ? cmp r1, r3, lsl r1 ; <UNPREDICTABLE>
-0+188 <[^>]*> e310f00a ? tst r0, #10 ; <UNPREDICTABLE>
-0+18c <[^>]*> e112f004 ? tst r2, r4 ; <UNPREDICTABLE>
-0+190 <[^>]*> e115f287 ? tst r5, r7, lsl #5 ; <UNPREDICTABLE>
-0+194 <[^>]*> e111f113 ? tst r1, r3, lsl r1 ; <UNPREDICTABLE>
+0+158 <[^>]*> e330f00a ? teq r0, #10 @ <UNPREDICTABLE>
+0+15c <[^>]*> e132f004 ? teq r2, r4 @ <UNPREDICTABLE>
+0+160 <[^>]*> e135f287 ? teq r5, r7, lsl #5 @ <UNPREDICTABLE>
+0+164 <[^>]*> e131f113 ? teq r1, r3, lsl r1 @ <UNPREDICTABLE>
+0+168 <[^>]*> e370f00a ? cmn r0, #10 @ <UNPREDICTABLE>
+0+16c <[^>]*> e172f004 ? cmn r2, r4 @ <UNPREDICTABLE>
+0+170 <[^>]*> e175f287 ? cmn r5, r7, lsl #5 @ <UNPREDICTABLE>
+0+174 <[^>]*> e171f113 ? cmn r1, r3, lsl r1 @ <UNPREDICTABLE>
+0+178 <[^>]*> e350f00a ? cmp r0, #10 @ <UNPREDICTABLE>
+0+17c <[^>]*> e152f004 ? cmp r2, r4 @ <UNPREDICTABLE>
+0+180 <[^>]*> e155f287 ? cmp r5, r7, lsl #5 @ <UNPREDICTABLE>
+0+184 <[^>]*> e151f113 ? cmp r1, r3, lsl r1 @ <UNPREDICTABLE>
+0+188 <[^>]*> e310f00a ? tst r0, #10 @ <UNPREDICTABLE>
+0+18c <[^>]*> e112f004 ? tst r2, r4 @ <UNPREDICTABLE>
+0+190 <[^>]*> e115f287 ? tst r5, r7, lsl #5 @ <UNPREDICTABLE>
+0+194 <[^>]*> e111f113 ? tst r1, r3, lsl r1 @ <UNPREDICTABLE>
0+198 <[^>]*> e0000291 ? mul r0, r1, r2
0+19c <[^>]*> e0110392 ? muls r1, r2, r3
0+1a0 <[^>]*> 10000091 ? mulne r0, r1, r0
0+1d0 <[^>]*> 14954006 ? ldrne r4, \[r5\], #6
0+1d4 <[^>]*> e6b21003 ? ldrt r1, \[r2\], r3
0+1d8 <[^>]*> e6942425 ? ldr r2, \[r4\], r5, lsr #8
-0+1dc <[^>]*> e51f0008 ? ldr r0, \[pc, #-8\] ; 0+1dc <[^>]*>
+0+1dc <[^>]*> e51f0008 ? ldr r0, \[pc, #-8\] @ 0+1dc <[^>]*>
0+1e0 <[^>]*> e5d43000 ? ldrb r3, \[r4\]
0+1e4 <[^>]*> 14f85000 ? ldrbtne r5, \[r8\], #0
0+1e8 <[^>]*> e5810000 ? str r0, \[r1\]
0+200 <[^>]*> 14854006 ? strne r4, \[r5\], #6
0+204 <[^>]*> e6821003 ? str r1, \[r2\], r3
0+208 <[^>]*> e6a42425 ? strt r2, \[r4\], r5, lsr #8
-0+20c <[^>]*> e50f1004 ? str r1, \[pc, #-4\] ; 0+210 <[^>]*>
+0+20c <[^>]*> e50f1004 ? str r1, \[pc, #-4\] @ 0+210 <[^>]*>
0+210 <[^>]*> e5c71000 ? strb r1, \[r7\]
0+214 <[^>]*> e4e02000 ? strbt r2, \[r0\], #0
0+218 <[^>]*> e8900002 ? ldm r0, {r1}
0+5c <[^>]*> e5910000 ldr r0, \[r1\]
0+60 <[^>]*> e5832000 str r2, \[r3\]
0+64 <[^>]*> e321f011 msr CPSR_c, #17
-0+68 <[^>]*> e1a00000 ? nop[ ]+; \(mov r0, r0\)
-0+6c <[^>]*> e1a00000 ? nop[ ]+; \(mov r0, r0\)
+0+68 <[^>]*> e1a00000 ? nop[ ]+@ \(mov r0, r0\)
+0+6c <[^>]*> e1a00000 ? nop[ ]+@ \(mov r0, r0\)
Disassembly of section .plt:
.* <.plt>:
- +.*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
- +.*: e59fe004 ldr lr, \[pc, #4\] ; .* <.*>
+ +.*: e52de004 push {lr} @ \(str lr, \[sp, #-4\]!\)
+ +.*: e59fe004 ldr lr, \[pc, #4\] @ .* <.*>
+.*: e08fe00e add lr, pc, lr
+.*: e5bef008 ldr pc, \[lr, #8\]!
+.*: .* .*
.* <lib_func1@plt>:
+.*: e28fc6.* add ip, pc, #.*
- +.*: e28cca.* add ip, ip, #.* ; .*
+ +.*: e28cca.* add ip, ip, #.* @ .*
+.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
Disassembly of section .text:
.* <_start>:
+.*: e1a0c00d mov ip, sp
+.*: e92dd800 push {fp, ip, lr, pc}
- +.*: e59f0004 ldr r0, \[pc, #4\] ; .* <_start\+0x14>
+ +.*: e59f0004 ldr r0, \[pc, #4\] @ .* <_start\+0x14>
+.*: e89d6800 ldm sp, {fp, sp, lr}
+.*: e12fff1e bx lr
+.*: .* .*
Disassembly of section .plt:
.* <.plt>:
- .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
- .*: e59fe004 ldr lr, \[pc, #4\] ; .* <.*>
+ .*: e52de004 push {lr} @ \(str lr, \[sp, #-4\]!\)
+ .*: e59fe004 ldr lr, \[pc, #4\] @ .* <.*>
.*: e08fe00e add lr, pc, lr
.*: e5bef008 ldr pc, \[lr, #8\]!
.*: .*
.* <lib_func1@plt>:
.*: e28fc6.* add ip, pc, #.*
- .*: e28cca.* add ip, ip, #.* ; 0x.*
+ .*: e28cca.* add ip, ip, #.* @ 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
Disassembly of section .text:
8004: e12fff1e bx lr
00008008 <thumb>:
- 8008: 46c0 nop ; \(mov r8, r8\)
+ 8008: 46c0 nop @ \(mov r8, r8\)
800a: 4770 bx lr
800c: f7ff fffc bl 8008 <thumb>
00008038 <t4>:
8038: 4770 bx lr
- 803a: 46c0 nop ; \(mov r8, r8\)
+ 803a: 46c0 nop @ \(mov r8, r8\)
0000803c <arm>:
803c: e12fff1e bx lr
0000804a <t5>:
804a: f000 f801 bl 8050 <local_thumb>
- 804e: 46c0 nop ; \(mov r8, r8\)
+ 804e: 46c0 nop @ \(mov r8, r8\)
00008050 <local_thumb>:
8050: f7ff fff1 bl 8036 <t3>
...
00008060 <__t1_from_arm>:
- 8060: e51ff004 ldr pc, \[pc, #-4\] ; 8064 <__t1_from_arm\+0x4>
+ 8060: e51ff004 ldr pc, \[pc, #-4\] @ 8064 <__t1_from_arm\+0x4>
8064: 00008041 .word 0x00008041
00008068 <__t2_from_arm>:
- 8068: e51ff004 ldr pc, \[pc, #-4\] ; 806c <__t2_from_arm\+0x4>
+ 8068: e51ff004 ldr pc, \[pc, #-4\] @ 806c <__t2_from_arm\+0x4>
806c: 00008043 .word 0x00008043
Disassembly of section .plt:
.* <.plt>:
- .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
- .*: e59fe004 ldr lr, \[pc, #4\] ; .* <.*>
+ .*: e52de004 push {lr} @ \(str lr, \[sp, #-4\]!\)
+ .*: e59fe004 ldr lr, \[pc, #4\] @ .* <.*>
.*: e08fe00e add lr, pc, lr
.*: e5bef008 ldr pc, \[lr, #8\]!
.*: .*
.* <app_func2@plt>:
.*: e28fc6.* add ip, pc, #.*
- .*: e28cca.* add ip, ip, #.* ; 0x.*
+ .*: e28cca.* add ip, ip, #.* @ 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
Disassembly of section .text:
Disassembly of section .plt:
.* <.plt>:
- .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
- .*: e59fe004 ldr lr, \[pc, #4\] ; .* <.*>
+ .*: e52de004 push {lr} @ \(str lr, \[sp, #-4\]!\)
+ .*: e59fe004 ldr lr, \[pc, #4\] @ .* <.*>
.*: e08fe00e add lr, pc, lr
.*: e5bef008 ldr pc, \[lr, #8\]!
.*: .*
.* <app_func2@plt>:
.*: e28fc6.* add ip, pc, #.*
- .*: e28cca.* add ip, ip, #.* ; 0x.*
+ .*: e28cca.* add ip, ip, #.* @ 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
Disassembly of section .text:
00008000 <[^>]*>:
8000: e3000000 movw r0, #0
- 8004: e3411234 movt r1, #4660 ; 0x1234
- 8008: e3082000 movw r2, #32768 ; 0x8000
- 800c: e3413233 movt r3, #4659 ; 0x1233
+ 8004: e3411234 movt r1, #4660 @ 0x1234
+ 8008: e3082000 movw r2, #32768 @ 0x8000
+ 800c: e3413233 movt r3, #4659 @ 0x1233
8010: e3004011 movw r4, #17
- 8014: e3415234 movt r5, #4660 ; 0x1234
- 8018: e3086011 movw r6, #32785 ; 0x8011
- 801c: e3417233 movt r7, #4659 ; 0x1233
+ 8014: e3415234 movt r5, #4660 @ 0x1234
+ 8018: e3086011 movw r6, #32785 @ 0x8011
+ 801c: e3417233 movt r7, #4659 @ 0x1233
00008020 <[^>]*>:
8020: f240 0700 movw r7, #0
- 8024: f2c1 2634 movt r6, #4660 ; 0x1234
- 8028: f248 0500 movw r5, #32768 ; 0x8000
- 802c: f2c1 2433 movt r4, #4659 ; 0x1233
+ 8024: f2c1 2634 movt r6, #4660 @ 0x1234
+ 8028: f248 0500 movw r5, #32768 @ 0x8000
+ 802c: f2c1 2433 movt r4, #4659 @ 0x1233
8030: f240 0311 movw r3, #17
- 8034: f2c1 2234 movt r2, #4660 ; 0x1234
- 8038: f248 0111 movw r1, #32785 ; 0x8011
- 803c: f2c1 2033 movt r0, #4659 ; 0x1233
+ 8034: f2c1 2234 movt r2, #4660 @ 0x1234
+ 8038: f248 0111 movw r1, #32785 @ 0x8011
+ 803c: f2c1 2033 movt r0, #4659 @ 0x1233
Disassembly of section .far:
12340000 <[^>]*>:
-12340000: e3080000 movw r0, #32768 ; 0x8000
-12340004: e34e0dcc movt r0, #60876 ; 0xedcc
-12340008: e3080021 movw r0, #32801 ; 0x8021
-1234000c: e34e0dcc movt r0, #60876 ; 0xedcc
+12340000: e3080000 movw r0, #32768 @ 0x8000
+12340004: e34e0dcc movt r0, #60876 @ 0xedcc
+12340008: e3080021 movw r0, #32801 @ 0x8021
+1234000c: e34e0dcc movt r0, #60876 @ 0xedcc
12340010 <[^>]*>:
-12340010: f248 0000 movw r0, #32768 ; 0x8000
-12340014: f6ce 50cc movt r0, #60876 ; 0xedcc
-12340018: f248 0021 movw r0, #32801 ; 0x8021
-1234001c: f6ce 50cc movt r0, #60876 ; 0xedcc
+12340010: f248 0000 movw r0, #32768 @ 0x8000
+12340014: f6ce 50cc movt r0, #60876 @ 0xedcc
+12340018: f248 0021 movw r0, #32801 @ 0x8021
+1234001c: f6ce 50cc movt r0, #60876 @ 0xedcc
8000: ea...... b 800. <.*>
00008004 <foo>:
- 8004: 46c0 nop ; \(mov r8, r8\)
+ 8004: 46c0 nop @ \(mov r8, r8\)
8006: 4770 bx lr
00008008 <__foo_from_arm>:
- 8008: e59fc004 ldr ip, \[pc, #4\] ; 8014 <__foo_from_arm\+0xc>
+ 8008: e59fc004 ldr ip, \[pc, #4\] @ 8014 <__foo_from_arm\+0xc>
800c: e08fc00c add ip, pc, ip
8010: e12fff1c bx ip
8014: fffffff1 .word 0xfffffff1
Disassembly of section .plt:
.* <.plt>:
- .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
- .*: e59fe004 ldr lr, \[pc, #4\] ; .* <.*>
+ .*: e52de004 push {lr} @ \(str lr, \[sp, #-4\]!\)
+ .*: e59fe004 ldr lr, \[pc, #4\] @ .* <.*>
.*: e08fe00e add lr, pc, lr
.*: e5bef008 ldr pc, \[lr, #8\]!
.*: .*
.* <app_func2@plt>:
.*: e28fc6.* add ip, pc, #.*
- .*: e28cca.* add ip, ip, #.* ; 0x.*
+ .*: e28cca.* add ip, ip, #.* @ 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
Disassembly of section .text:
.*: ebfffff. bl .* <app_func2@plt>
.*: e89d6800 ldm sp, {fp, sp, lr}
.*: e12fff1e bx lr
- .*: e1a00000 nop ; \(mov r0, r0\)
- .*: e1a00000 nop ; \(mov r0, r0\)
- .*: e1a00000 nop ; \(mov r0, r0\)
+ .*: e1a00000 nop @ \(mov r0, r0\)
+ .*: e1a00000 nop @ \(mov r0, r0\)
+ .*: e1a00000 nop @ \(mov r0, r0\)
.* <__real_lib_func2>:
.*: 4770 bx lr
- .*: 46c0 nop ; \(mov r8, r8\)
+ .*: 46c0 nop @ \(mov r8, r8\)
.* <lib_func2>:
- .*: e59fc004 ldr ip, \[pc, #4\] ; .* <lib_func2\+0xc>
+ .*: e59fc004 ldr ip, \[pc, #4\] @ .* <lib_func2\+0xc>
.*: e08cc00f add ip, ip, pc
.*: e12fff1c bx ip
.*: fffffff1 .*
#source: attr-merge-wchar-4.s
#as:
#ld: -r
-#warning: warning: .* uses 4-byte wchar_t yet the output is to use 2-byte wchar_t; use of wchar_t values across objects may fail
+#warning: warning: .* uses 4-byte wchar_t yet the output is to use 2-byte wchar_t@ use of wchar_t values across objects may fail
#source: attr-merge-wchar-2.s
#as:
#ld: -r
-#warning: warning: .* uses 2-byte wchar_t yet the output is to use 4-byte wchar_t; use of wchar_t values across objects may fail
+#warning: warning: .* uses 2-byte wchar_t yet the output is to use 4-byte wchar_t@ use of wchar_t values across objects may fail
Disassembly of section .far:
12340000 <[^>]*>:
-12340000: e1a00000 nop ; \(mov r0, r0\)
+12340000: e1a00000 nop @ \(mov r0, r0\)
12340004: 01a00000 moveq r0, r0
12340008 <[^>]*>:
...
#...
00800008 <__far_fn_from_thumb>:
- 800008: e51ff004 ldr pc, \[pc, #-4\] ; 80000c <__far_fn_from_thumb\+0x4>
+ 800008: e51ff004 ldr pc, \[pc, #-4\] @ 80000c <__far_fn_from_thumb\+0x4>
80000c: 7fff0000 .word 0x7fff0000
00800010 <three>:
...
00801018 <__far_fn2_from_thumb>:
- 801018: e51ff004 ldr pc, \[pc, #-4\] ; 80101c <__far_fn2_from_thumb\+0x4>
+ 801018: e51ff004 ldr pc, \[pc, #-4\] @ 80101c <__far_fn2_from_thumb\+0x4>
80101c: 80000004 .word 0x80000004
00801020 <__far_fn1_from_thumb>:
- 801020: e51ff004 ldr pc, \[pc, #-4\] ; 801024 <__far_fn1_from_thumb\+0x4>
+ 801020: e51ff004 ldr pc, \[pc, #-4\] @ 801024 <__far_fn1_from_thumb\+0x4>
801024: 80000000 .word 0x80000000
801028: d001 beq.n 80102e <__far_fn1_from_thumb\+0xe>
80102a: f7ff bfea b.w 801002 <label1\+0x8>
Disassembly of section \.plt:
00008000 <.*>:
- 8000: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
- 8004: e59fe004 ldr lr, \[pc, #4\] ; 8010 <.*>
+ 8000: e52de004 push {lr} @ \(str lr, \[sp, #-4\]!\)
+ 8004: e59fe004 ldr lr, \[pc, #4\] @ 8010 <.*>
8008: e08fe00e add lr, pc, lr
800c: e5bef008 ldr pc, \[lr, #8\]!
8010: 00000ffc \.word 0x00000ffc
8016: e7fd b.n .+ <.+>
8018: e28fc600 add ip, pc, #0, 12
801c: e28cca00 add ip, ip, #0, 20
- 8020: e5bcfff8 ldr pc, \[ip, #4088\]! ; 0xff8
+ 8020: e5bcfff8 ldr pc, \[ip, #4088\]! @ 0xff8
Disassembly of section \.text:
00008ff0 <foo>:
- 8ff0: 46c0 nop ; \(mov r8, r8\)
+ 8ff0: 46c0 nop @ \(mov r8, r8\)
8ff2: f240 0000 movw r0, #0
8ff6: f240 0000 movw r0, #0
8ffa: f240 0000 movw r0, #0
Disassembly of section \.plt:
00008000 <.plt>:
- 8000: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
- 8004: e59fe004 ldr lr, \[pc, #4\] ; 8010 <.*>
+ 8000: e52de004 push {lr} @ \(str lr, \[sp, #-4\]!\)
+ 8004: e59fe004 ldr lr, \[pc, #4\] @ 8010 <.*>
8008: e08fe00e add lr, pc, lr
800c: e5bef008 ldr pc, \[lr, #8\]!
8010: 00001004 \.word 0x00001004
8014: 4778 bx pc
8016: e7fd b.n .+ <.+>
8018: e28fc600 add ip, pc, #0, 12
- 801c: e28cca01 add ip, ip, #4096 ; 0x1000
+ 801c: e28cca01 add ip, ip, #4096 @ 0x1000
8020: e5bcf000 ldr pc, \[ip, #0\]!
Disassembly of section \.text:
00008ff0 <foo>:
- 8ff0: 46c0 nop ; \(mov r8, r8\)
+ 8ff0: 46c0 nop @ \(mov r8, r8\)
8ff2: f240 0000 movw r0, #0
8ff6: f240 0000 movw r0, #0
8ffa: f240 0000 movw r0, #0
Disassembly of section \.plt:
00008000 <.plt>:
- 8000: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
- 8004: e59fe004 ldr lr, \[pc, #4\] ; 8010 <.*>
+ 8000: e52de004 push {lr} @ \(str lr, \[sp, #-4\]!\)
+ 8004: e59fe004 ldr lr, \[pc, #4\] @ 8010 <.*>
8008: e08fe00e add lr, pc, lr
800c: e5bef008 ldr pc, \[lr, #8\]!
8010: 00000ffc \.word 0x00000ffc
00008014 <bar@plt>:
8014: e28fc600 add ip, pc, #0, 12
8018: e28cca00 add ip, ip, #0, 20
- 801c: e5bcfffc ldr pc, \[ip, #4092\]! ; 0xffc
+ 801c: e5bcfffc ldr pc, \[ip, #4092\]! @ 0xffc
Disassembly of section \.text:
00008ff0 <foo>:
- 8ff0: 46c0 nop ; \(mov r8, r8\)
+ 8ff0: 46c0 nop @ \(mov r8, r8\)
8ff2: f240 0000 movw r0, #0
8ff6: f240 0000 movw r0, #0
8ffa: f240 0000 movw r0, #0
Disassembly of section \.plt:
00008e00 <.plt>:
- 8e00: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
- 8e04: e59fe004 ldr lr, \[pc, #4\] ; 8e10 <.*>
+ 8e00: e52de004 push {lr} @ \(str lr, \[sp, #-4\]!\)
+ 8e04: e59fe004 ldr lr, \[pc, #4\] @ 8e10 <.*>
8e08: e08fe00e add lr, pc, lr
8e0c: e5bef008 ldr pc, \[lr, #8\]!
8e10: 0001027c \.word 0x0001027c
00008e14 <targetfn@plt>:
8e14: e28fc600 add ip, pc, #0, 12
- 8e18: e28cca10 add ip, ip, #16, 20 ; 0x10000
- 8e1c: e5bcf27c ldr pc, \[ip, #636\]! ; 0x27c
+ 8e18: e28cca10 add ip, ip, #16, 20 @ 0x10000
+ 8e1c: e5bcf27c ldr pc, \[ip, #636\]! @ 0x27c
Disassembly of section \.text:
Disassembly of section \.plt:
00008000 <.plt>:
- 8000: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
- 8004: e59fe004 ldr lr, \[pc, #4\] ; 8010 <.*>
+ 8000: e52de004 push {lr} @ \(str lr, \[sp, #-4\]!\)
+ 8004: e59fe004 ldr lr, \[pc, #4\] @ 8010 <.*>
8008: e08fe00e add lr, pc, lr
800c: e5bef008 ldr pc, \[lr, #8\]!
8010: 00000ffc \.word 0x00000ffc
00008014 <bar@plt>:
8014: e28fc600 add ip, pc, #0, 12
8018: e28cca00 add ip, ip, #0, 20
- 801c: e5bcfffc ldr pc, \[ip, #4092\]! ; 0xffc
+ 801c: e5bcfffc ldr pc, \[ip, #4092\]! @ 0xffc
Disassembly of section \.text:
00008ff0 <foo>:
- 8ff0: 46c0 nop ; \(mov r8, r8\)
+ 8ff0: 46c0 nop @ \(mov r8, r8\)
8ff2: f240 0000 movw r0, #0
8ff6: f240 0000 movw r0, #0
8ffa: f240 0000 movw r0, #0
1004: 00000000 andeq r0, r0, r0
00001008 <__bar_veneer>:
- 1008: e59fc000 ldr ip, \[pc\] ; 1010 <__bar_veneer\+0x8>
+ 1008: e59fc000 ldr ip, \[pc\] @ 1010 <__bar_veneer\+0x8>
100c: e08ff00c add pc, pc, ip
1010: 0200000c .word 0x0200000c
1014: 00000000 .word 0x00000000
1004: 00000000 andeq r0, r0, r0
00001008 <__bar_veneer>:
- 1008: e51ff004 ldr pc, \[pc, #-4\] ; 100c <__bar_veneer\+0x4>
+ 1008: e51ff004 ldr pc, \[pc, #-4\] @ 100c <__bar_veneer\+0x4>
100c: 02001020 .word 0x02001020
Disassembly of section .foo:
#...
0+1010 <__bar_veneer>:
-\s*1010:\s+e59fc00c\s+ldr\s+ip, \[pc, #12\]\s+; 1024 <__bar_veneer\+0x14>
+\s*1010:\s+e59fc00c\s+ldr\s+ip, \[pc, #12\]\s+@ 1024 <__bar_veneer\+0x14>
\s*1014:\s+e08cc00f\s+add\s+ip, ip, pc
-\s*1018:\s+e3ccc13f\s+bic\s+ip, ip, #-1073741809\s+; 0xc000000f
+\s*1018:\s+e3ccc13f\s+bic\s+ip, ip, #-1073741809\s+@ 0xc000000f
\s*101c:\s+e12fff1c\s+bx\s+ip
\s*1020:\s+e125be70\s+bkpt\s+0x5be0
\s*1024:\s+02000004\s+.word\s+0x02000004
#...
0+1010 <__bar_veneer>:
-\s*1010:\s+e59fc00c\s+ldr\s+ip, \[pc, #12\]\s+; 1024 <__bar_veneer\+0x14>
-\s*1014:\s+e3ccc13f\s+bic\s+ip, ip, #-1073741809\s+; 0xc000000f
+\s*1010:\s+e59fc00c\s+ldr\s+ip, \[pc, #12\]\s+@ 1024 <__bar_veneer\+0x14>
+\s*1014:\s+e3ccc13f\s+bic\s+ip, ip, #-1073741809\s+@ 0xc000000f
\s*1018:\s+e12fff1c\s+bx\s+ip
\s*101c:\s+e320f000\s+nop\s+\{0\}
\s*1020:\s+e125be70\s+bkpt\s+0x5be0
1004: 00000000 andeq r0, r0, r0
00001008 <__bar_from_arm>:
- 1008: e59fc004 ldr ip, \[pc, #4\] ; 1014 <__bar_from_arm\+0xc>
+ 1008: e59fc004 ldr ip, \[pc, #4\] @ 1014 <__bar_from_arm\+0xc>
100c: e08fc00c add ip, pc, ip
1010: e12fff1c bx ip
1014: 02000001 .word 0x02000001
1004: 00000000 andeq r0, r0, r0
00001008 <__bar_from_arm>:
- 1008: e51ff004 ldr pc, \[pc, #-4\] ; 100c <__bar_from_arm\+0x4>
+ 1008: e51ff004 ldr pc, \[pc, #-4\] @ 100c <__bar_from_arm\+0x4>
100c: 02001015 .word 0x02001015
Disassembly of section .foo:
1004: 00000000 andeq r0, r0, r0
00001008 <__bar_from_arm>:
- 1008: e59fc004 ldr ip, \[pc, #4\] ; 1014 <__bar_from_arm\+0xc>
+ 1008: e59fc004 ldr ip, \[pc, #4\] @ 1014 <__bar_from_arm\+0xc>
100c: e08fc00c add ip, pc, ip
1010: e12fff1c bx ip
1014: 02000001 .word 0x02000001
1004: 00000000 andeq r0, r0, r0
00001008 <__bar_from_arm>:
- 1008: e59fc000 ldr ip, \[pc\] ; 1010 <__bar_from_arm\+0x8>
+ 1008: e59fc000 ldr ip, \[pc\] @ 1010 <__bar_from_arm\+0x8>
100c: e12fff1c bx ip
1010: 02001015 .word 0x02001015
1014: 00000000 .word 0x00000000
#...
0+8010 <__far_veneer>:
-\s*8010:\s+e59fc00c\s+ldr\s+ip, \[pc, #12\]\s+; 8024 <__far_veneer\+0x14>
-\s*8014:\s+e3ccc13f\s+bic\s+ip, ip, #-1073741809\s+; 0xc000000f
+\s*8010:\s+e59fc00c\s+ldr\s+ip, \[pc, #12\]\s+@ 8024 <__far_veneer\+0x14>
+\s*8014:\s+e3ccc13f\s+bic\s+ip, ip, #-1073741809\s+@ 0xc000000f
\s*8018:\s+e12fff1c\s+bx\s+ip
\s*801c:\s+e320f000\s+nop\s+\{0\}
\s*8020:\s+e125be70\s+bkpt\s+0x5be0
8004: 00000000 andeq r0, r0, r0
00008008 <__far_veneer>:
- 8008: e51ff004 ldr pc, \[pc, #-4\] ; 800c <__far_veneer\+0x4>
+ 8008: e51ff004 ldr pc, \[pc, #-4\] @ 800c <__far_veneer\+0x4>
800c: 12340000 \.word 0x12340000
00008010 <after>:
1004: 00000000 andeq r0, r0, r0
00001008 <__bar_veneer>:
- 1008: e51ff004 ldr pc, \[pc, #-4\] ; 100c <__bar_veneer\+0x4>
+ 1008: e51ff004 ldr pc, \[pc, #-4\] @ 100c <__bar_veneer\+0x4>
100c: 02003020 .word 0x02003020
00001010 <myfunc>:
1004: eb000002 bl 1014 <__bar2_veneer>
00001008 <__bar_from_arm>:
- 1008: e59fc000 ldr ip, \[pc\] ; 1010 <__bar_from_arm\+0x8>
+ 1008: e59fc000 ldr ip, \[pc\] @ 1010 <__bar_from_arm\+0x8>
100c: e12fff1c bx ip
1010: 02003021 .word 0x02003021
00001014 <__bar2_veneer>:
- 1014: e51ff004 ldr pc, \[pc, #-4\] ; 1018 <__bar2_veneer\+0x4>
+ 1014: e51ff004 ldr pc, \[pc, #-4\] @ 1018 <__bar2_veneer\+0x4>
1018: 02003024 .word 0x02003024
101c: 00000000 .word 0x00000000
102c: 00000000 andeq r0, r0, r0
00001030 <__bar4_from_arm>:
- 1030: e59fc000 ldr ip, \[pc\] ; 1038 <__bar4_from_arm\+0x8>
+ 1030: e59fc000 ldr ip, \[pc\] @ 1038 <__bar4_from_arm\+0x8>
1034: e12fff1c bx ip
1038: 0200302d .word 0x0200302d
0000103c <__bar5_from_arm>:
- 103c: e59fc000 ldr ip, \[pc\] ; 1044 <__bar5_from_arm\+0x8>
+ 103c: e59fc000 ldr ip, \[pc\] @ 1044 <__bar5_from_arm\+0x8>
1040: e12fff1c bx ip
1044: 0200302f .word 0x0200302f
00001048 <__bar3_veneer>:
- 1048: e51ff004 ldr pc, \[pc, #-4\] ; 104c <__bar3_veneer\+0x4>
+ 1048: e51ff004 ldr pc, \[pc, #-4\] @ 104c <__bar3_veneer\+0x4>
104c: 02003028 .word 0x02003028
...
+[0-9a-f]+: 00000000 andeq r0, r0, r0
[0-9a-f]+ <__bar4_from_arm>:
- +[0-9a-f]+: e59fc000 ldr ip, \[pc\] ; [0-9a-f]+ <__bar4_from_arm\+0x8>
+ +[0-9a-f]+: e59fc000 ldr ip, \[pc\] @ [0-9a-f]+ <__bar4_from_arm\+0x8>
+[0-9a-f]+: e12fff1c bx ip
+[0-9a-f]+: 0200302d .word 0x0200302d
[0-9a-f]+ <__bar2_veneer>:
- +[0-9a-f]+: e51ff004 ldr pc, \[pc, #-4\] ; [0-9a-f]+ <__bar2_veneer\+0x4>
+ +[0-9a-f]+: e51ff004 ldr pc, \[pc, #-4\] @ [0-9a-f]+ <__bar2_veneer\+0x4>
+[0-9a-f]+: 02003024 .word 0x02003024
[0-9a-f]+ <__bar_from_arm>:
- +[0-9a-f]+: e59fc000 ldr ip, \[pc\] ; [0-9a-f]+ <__bar_from_arm\+0x8>
+ +[0-9a-f]+: e59fc000 ldr ip, \[pc\] @ [0-9a-f]+ <__bar_from_arm\+0x8>
+[0-9a-f]+: e12fff1c bx ip
+[0-9a-f]+: 02003021 .word 0x02003021
[0-9a-f]+ <__bar5_from_arm>:
- +[0-9a-f]+: e59fc000 ldr ip, \[pc\] ; [0-9a-f]+ <__bar5_from_arm\+0x8>
+ +[0-9a-f]+: e59fc000 ldr ip, \[pc\] @ [0-9a-f]+ <__bar5_from_arm\+0x8>
+[0-9a-f]+: e12fff1c bx ip
+[0-9a-f]+: 0200302f .word 0x0200302f
[0-9a-f]+ <__bar3_veneer>:
- +[0-9a-f]+: e51ff004 ldr pc, \[pc, #-4\] ; [0-9a-f]+ <__bar3_veneer\+0x4>
+ +[0-9a-f]+: e51ff004 ldr pc, \[pc, #-4\] @ [0-9a-f]+ <__bar3_veneer\+0x4>
+[0-9a-f]+: 02003028 .word 0x02003028
...
+[0-9a-f]+: 00000000 andeq r0, r0, r0
[0-9a-f]+ <__bar_from_arm>:
- +[0-9a-f]+: e59fc000 ldr ip, \[pc\] ; [0-9a-f]+ <__bar_from_arm\+0x8>
+ +[0-9a-f]+: e59fc000 ldr ip, \[pc\] @ [0-9a-f]+ <__bar_from_arm\+0x8>
+[0-9a-f]+: e12fff1c bx ip
+[0-9a-f]+: 02002021 .word 0x02002021
[0-9a-f]+ <__bar3_veneer>:
- +[0-9a-f]+: e51ff004 ldr pc, \[pc, #-4\] ; [0-9a-f]+ <__bar3_veneer\+0x4>
+ +[0-9a-f]+: e51ff004 ldr pc, \[pc, #-4\] @ [0-9a-f]+ <__bar3_veneer\+0x4>
+[0-9a-f]+: 02002028 .word 0x02002028
[0-9a-f]+ <__bar5_from_arm>:
- +[0-9a-f]+: e59fc000 ldr ip, \[pc\] ; [0-9a-f]+ <__bar5_from_arm\+0x8>
+ +[0-9a-f]+: e59fc000 ldr ip, \[pc\] @ [0-9a-f]+ <__bar5_from_arm\+0x8>
+[0-9a-f]+: e12fff1c bx ip
+[0-9a-f]+: 0200202f .word 0x0200202f
[0-9a-f]+ <__bar4_from_arm>:
- +[0-9a-f]+: e59fc000 ldr ip, \[pc\] ; [0-9a-f]+ <__bar4_from_arm\+0x8>
+ +[0-9a-f]+: e59fc000 ldr ip, \[pc\] @ [0-9a-f]+ <__bar4_from_arm\+0x8>
+[0-9a-f]+: e12fff1c bx ip
+[0-9a-f]+: 0200202d .word 0x0200202d
[0-9a-f]+ <__bar2_veneer>:
- +[0-9a-f]+: e51ff004 ldr pc, \[pc, #-4\] ; [0-9a-f]+ <__bar2_veneer\+0x4>
+ +[0-9a-f]+: e51ff004 ldr pc, \[pc, #-4\] @ [0-9a-f]+ <__bar2_veneer\+0x4>
+[0-9a-f]+: 02002024 .word 0x02002024
...
+[0-9a-f]+: eb000002 bl [0-9a-f]+ <__bar2_veneer>
[0-9a-f]+ <__bar_from_arm>:
- +[0-9a-f]+: e59fc000 ldr ip, \[pc\] ; [0-9a-f]+ <__bar_from_arm\+0x8>
+ +[0-9a-f]+: e59fc000 ldr ip, \[pc\] @ [0-9a-f]+ <__bar_from_arm\+0x8>
+[0-9a-f]+: e12fff1c bx ip
+[0-9a-f]+: 02003021 .word 0x02003021
[0-9a-f]+ <__bar2_veneer>:
- +[0-9a-f]+: e51ff004 ldr pc, \[pc, #-4\] ; [0-9a-f]+ <__bar2_veneer\+0x4>
+ +[0-9a-f]+: e51ff004 ldr pc, \[pc, #-4\] @ [0-9a-f]+ <__bar2_veneer\+0x4>
+[0-9a-f]+: 02003024 .word 0x02003024
+[0-9a-f]+: 00000000 .word 0x00000000
Disassembly of section .mytext:
+[0-9a-f]+: 00000000 andeq r0, r0, r0
[0-9a-f]+ <__bar3_veneer>:
- +[0-9a-f]+: e51ff004 ldr pc, \[pc, #-4\] ; [0-9a-f]+ <__bar3_veneer\+0x4>
+ +[0-9a-f]+: e51ff004 ldr pc, \[pc, #-4\] @ [0-9a-f]+ <__bar3_veneer\+0x4>
+[0-9a-f]+: 02003028 .word 0x02003028
[0-9a-f]+ <__bar4_from_arm>:
- +[0-9a-f]+: e59fc000 ldr ip, \[pc\] ; [0-9a-f]+ <__bar4_from_arm\+0x8>
+ +[0-9a-f]+: e59fc000 ldr ip, \[pc\] @ [0-9a-f]+ <__bar4_from_arm\+0x8>
+[0-9a-f]+: e12fff1c bx ip
+[0-9a-f]+: 0200302d .word 0x0200302d
[0-9a-f]+ <__bar5_from_arm>:
- +[0-9a-f]+: e59fc000 ldr ip, \[pc\] ; [0-9a-f]+ <__bar5_from_arm\+0x8>
+ +[0-9a-f]+: e59fc000 ldr ip, \[pc\] @ [0-9a-f]+ <__bar5_from_arm\+0x8>
+[0-9a-f]+: e12fff1c bx ip
+[0-9a-f]+: 0200302f .word 0x0200302f
...
Disassembly of section .plt:
.* <.plt>:
- .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
- .*: e59fe004 ldr lr, \[pc, #4\] ; .* <.*>
+ .*: e52de004 push {lr} @ \(str lr, \[sp, #-4\]!\)
+ .*: e59fe004 ldr lr, \[pc, #4\] @ .* <.*>
.*: e08fe00e add lr, pc, lr
.*: e5bef008 ldr pc, \[lr, #8\]!
.*: .*
.* <lib_func2@plt>:
.*: e28fc6.* add ip, pc, #.*
- .*: e28cca.* add ip, ip, #.* ; 0x.*
+ .*: e28cca.* add ip, ip, #.* @ 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
.* <lib_func1@plt>:
.*: e28fc6.* add ip, pc, #.*
- .*: e28cca.* add ip, ip, #.* ; 0x.*
+ .*: e28cca.* add ip, ip, #.* @ 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
Disassembly of section .text:
.*: ebfffff1 bl .* <lib_func2@plt>
.*: e89d6800 ldm sp, {fp, sp, lr}
.*: e12fff1e bx lr
- .*: e1a00000 nop ; \(mov r0, r0\)
+ .*: e1a00000 nop @ \(mov r0, r0\)
.* <app_tfunc_close>:
.*: b500 push {lr}
.*: f7ff efdc blx .* <lib_func2@plt>
.*: bd00 pop {pc}
.*: 4770 bx lr
- .*: 46c0 nop ; \(mov r8, r8\)
+ .*: 46c0 nop @ \(mov r8, r8\)
#...
.* <__app_func_veneer>:
- .*: e51ff004 ldr pc, \[pc, #-4\] ; .* <__app_func_veneer\+0x4>
+ .*: e51ff004 ldr pc, \[pc, #-4\] @ .* <__app_func_veneer\+0x4>
.*: 02100000 .word 0x02100000
Disassembly of section .far_arm:
.*: eb00000(7|5) bl .* <__lib_func2_veneer>
.*: e89d6800 ldm sp, {fp, sp, lr}
.*: e12fff1e bx lr
- .*: e1a00000 nop ; \(mov r0, r0\)
- .*: e1a00000 nop ; \(mov r0, r0\)
+ .*: e1a00000 nop @ \(mov r0, r0\)
+ .*: e1a00000 nop @ \(mov r0, r0\)
.* <app_func2>:
.*: e12fff1e bx lr
#...
.* <__lib_func(1|2)_veneer>:
- .*: e51ff004 ldr pc, \[pc, #-4\] ; .* <__lib_func(1|2)_veneer\+0x4>
+ .*: e51ff004 ldr pc, \[pc, #-4\] @ .* <__lib_func(1|2)_veneer\+0x4>
.*: 000081(e8|dc) .word 0x000081(e8|dc)
.* <__lib_func(2|1)_veneer>:
- .*: e51ff004 ldr pc, \[pc, #-4\] ; .* <__lib_func(2|1)_veneer\+0x4>
+ .*: e51ff004 ldr pc, \[pc, #-4\] @ .* <__lib_func(2|1)_veneer\+0x4>
.*: 000081(dc|e8) .word 0x000081(dc|e8)
Disassembly of section .far_thumb:
.*: f000 e806 blx .* <__lib_func2_from_thumb>
.*: bd00 pop {pc}
.*: 4770 bx lr
- .*: 46c0 nop ; \(mov r8, r8\)
+ .*: 46c0 nop @ \(mov r8, r8\)
#...
.* <__lib_func2_from_thumb>:
- .*: e51ff004 ldr pc, \[pc, #-4\] ; 2200014 <__lib_func2_from_thumb\+0x4>
+ .*: e51ff004 ldr pc, \[pc, #-4\] @ 2200014 <__lib_func2_from_thumb\+0x4>
.*: 000081dc .word 0x000081dc
Disassembly of section .plt:
.* <.plt>:
- .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
- .*: e59fe004 ldr lr, \[pc, #4\] ; .* <.*>
+ .*: e52de004 push {lr} @ \(str lr, \[sp, #-4\]!\)
+ .*: e59fe004 ldr lr, \[pc, #4\] @ .* <.*>
.*: e08fe00e add lr, pc, lr
.*: e5bef008 ldr pc, \[lr, #8\]!
.*: .*
.*: 4778 bx pc
.*: e7fd b.n .+ <.+>
.*: e28fc6.* add ip, pc, #.*
- .*: e28cca.* add ip, ip, #.* ; 0x.*
+ .*: e28cca.* add ip, ip, #.* @ 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
.* <lib_func1@plt>:
.*: e28fc6.* add ip, pc, #.*
- .*: e28cca.* add ip, ip, #.* ; 0x.*
+ .*: e28cca.* add ip, ip, #.* @ 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
Disassembly of section .text:
.*: ebfffff2 bl .* <lib_func2@plt\+0x4>
.*: e89d6800 ldm sp, {fp, sp, lr}
.*: e12fff1e bx lr
- .*: e1a00000 nop ; \(mov r0, r0\)
+ .*: e1a00000 nop @ \(mov r0, r0\)
.* <app_tfunc_close>:
.*: b500 push {lr}
.*: f7ff ffdb bl 81dc <lib_func2@plt>
.*: bd00 pop {pc}
.*: 4770 bx lr
- .*: 46c0 nop ; \(mov r8, r8\)
+ .*: 46c0 nop @ \(mov r8, r8\)
#...
.* <__app_func_veneer>:
- .*: e51ff004 ldr pc, \[pc, #-4\] ; 8234 <__app_func_veneer\+0x4>
+ .*: e51ff004 ldr pc, \[pc, #-4\] @ 8234 <__app_func_veneer\+0x4>
.*: 02100000 .word 0x02100000
Disassembly of section .far_arm:
.*: eb00000(7|5) bl .* <__lib_func2_veneer>
.*: e89d6800 ldm sp, {fp, sp, lr}
.*: e12fff1e bx lr
- .*: e1a00000 nop ; \(mov r0, r0\)
- .*: e1a00000 nop ; \(mov r0, r0\)
+ .*: e1a00000 nop @ \(mov r0, r0\)
+ .*: e1a00000 nop @ \(mov r0, r0\)
.* <app_func2>:
.*: e12fff1e bx lr
#...
.* <__lib_func(1|2)_veneer>:
- .*: e51ff004 ldr pc, \[pc, #-4\] ; .* <__lib_func(1|2)_veneer\+0x4>
+ .*: e51ff004 ldr pc, \[pc, #-4\] @ .* <__lib_func(1|2)_veneer\+0x4>
.*: 000081e(c|0) .word 0x000081e(c|0)
.* <__lib_func(2|1)_veneer>:
- .*: e51ff004 ldr pc, \[pc, #-4\] ; .* <__lib_func(2|1)_veneer\+0x4>
+ .*: e51ff004 ldr pc, \[pc, #-4\] @ .* <__lib_func(2|1)_veneer\+0x4>
.*: 000081e(0|c) .word 0x000081e(0|c)
Disassembly of section .far_thumb:
.*: f000 f805 bl .* <__lib_func2_from_thumb>
.*: bd00 pop {pc}
.*: 4770 bx lr
- .*: 46c0 nop ; \(mov r8, r8\)
+ .*: 46c0 nop @ \(mov r8, r8\)
#...
.* <__lib_func2_from_thumb>:
.*: 4778 bx pc
.*: e7fd b.n .+ <.+>
- .*: e51ff004 ldr pc, \[pc, #-4\] ; 2200018 <__lib_func2_from_thumb\+0x8>
+ .*: e51ff004 ldr pc, \[pc, #-4\] @ 2200018 <__lib_func2_from_thumb\+0x8>
.*: 000081e0 .word 0x000081e0
.*: 00000000 .word 0x00000000
Disassembly of section .plt:
.* <.*>:
- .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
- .*: e59fe004 ldr lr, \[pc, #4\] ; .* <.*>
+ .*: e52de004 push {lr} @ \(str lr, \[sp, #-4\]!\)
+ .*: e59fe004 ldr lr, \[pc, #4\] @ .* <.*>
.*: e08fe00e add lr, pc, lr
.*: e5bef008 ldr pc, \[lr, #8\]!
.*: .*
.*: 4778 bx pc
.*: e7fd b.n .+ <.+>
.*: e28fc6.* add ip, pc, #.*
- .*: e28cca.* add ip, ip, #.* ; 0x.*
+ .*: e28cca.* add ip, ip, #.* @ 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
.* <lib_func1@plt>:
.*: e28fc6.* add ip, pc, #.*
- .*: e28cca.* add ip, ip, #.* ; 0x.*
+ .*: e28cca.* add ip, ip, #.* @ 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
Disassembly of section .text:
.*: ebfffff2 bl .* <lib_func2@plt\+0x4>
.*: e89d6800 ldm sp, {fp, sp, lr}
.*: e12fff1e bx lr
- .*: e1a00000 nop ; \(mov r0, r0\)
+ .*: e1a00000 nop @ \(mov r0, r0\)
.* <app_tfunc_close>:
.*: b500 push {lr}
.*: f7ff efde blx 81e0 <lib_func2@plt\+0x4>
.*: bd00 pop {pc}
.*: 4770 bx lr
- .*: 46c0 nop ; \(mov r8, r8\)
+ .*: 46c0 nop @ \(mov r8, r8\)
#...
.* <__app_func_veneer>:
- .*: e51ff004 ldr pc, \[pc, #-4\] ; 8234 <__app_func_veneer\+0x4>
+ .*: e51ff004 ldr pc, \[pc, #-4\] @ 8234 <__app_func_veneer\+0x4>
.*: 02100000 .word 0x02100000
Disassembly of section .mid_thumb:
.* <__lib_func2_from_thumb>:
.*: 4778 bx pc
.*: e7fd b.n .+ <.+>
- .*: e51ff004 ldr pc, \[pc, #-4\] ; 10081e8 <__lib_func2_from_thumb\+0x8>
+ .*: e51ff004 ldr pc, \[pc, #-4\] @ 10081e8 <__lib_func2_from_thumb\+0x8>
.*: 000081e0 .word 0x000081e0
.*: 00000000 .word 0x00000000
.*: eb000007 bl .* <__lib_func2_veneer>
.*: e89d6800 ldm sp, {fp, sp, lr}
.*: e12fff1e bx lr
- .*: e1a00000 nop ; \(mov r0, r0\)
- .*: e1a00000 nop ; \(mov r0, r0\)
+ .*: e1a00000 nop @ \(mov r0, r0\)
+ .*: e1a00000 nop @ \(mov r0, r0\)
.* <app_func2>:
.*: e12fff1e bx lr
#...
.* <__lib_func1_veneer>:
- .*: e51ff004 ldr pc, \[pc, #-4\] ; .* <__lib_func1_veneer\+0x4>
+ .*: e51ff004 ldr pc, \[pc, #-4\] @ .* <__lib_func1_veneer\+0x4>
.*: 000081ec .word 0x000081ec
.* <__lib_func2_veneer>:
- .*: e51ff004 ldr pc, \[pc, #-4\] ; .* <__lib_func2_veneer\+0x4>
+ .*: e51ff004 ldr pc, \[pc, #-4\] @ .* <__lib_func2_veneer\+0x4>
.*: 000081e0 .word 0x000081e0
Disassembly of section .far_thumb:
.*: f000 e806 blx .* <__lib_func2_from_thumb>
.*: bd00 pop {pc}
.*: 4770 bx lr
- .*: 46c0 nop ; \(mov r8, r8\)
+ .*: 46c0 nop @ \(mov r8, r8\)
#...
.* <__lib_func2_from_thumb>:
- .*: e51ff004 ldr pc, \[pc, #-4\] ; 2200014 <__lib_func2_from_thumb\+0x4>
+ .*: e51ff004 ldr pc, \[pc, #-4\] @ 2200014 <__lib_func2_from_thumb\+0x4>
.*: 000081e0 .word 0x000081e0
Disassembly of section .plt:
.* <.plt>:
- .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
- .*: e59fe004 ldr lr, \[pc, #4\] ; .* <.*>
+ .*: e52de004 push {lr} @ \(str lr, \[sp, #-4\]!\)
+ .*: e59fe004 ldr lr, \[pc, #4\] @ .* <.*>
.*: e08fe00e add lr, pc, lr
.*: e5bef008 ldr pc, \[lr, #8\]!
.*: .* .word .*
.*: 4778 bx pc
.*: e7fd b.n .+ <.+>
.*: e28fc6.* add ip, pc, #.*
- .*: e28cca.* add ip, ip, #.* ; 0x.*
- .*: e5bcf.* ldr pc, \[ip, #.*\]! ; .*
+ .*: e28cca.* add ip, ip, #.* @ 0x.*
+ .*: e5bcf.* ldr pc, \[ip, #.*\]! @ .*
.* <app_func_weak@plt>:
.*: 4778 bx pc
.*: e7fd b.n .+ <.+>
.*: e28fc6.* add ip, pc, #.*
- .*: e28cca.* add ip, ip, #.* ; 0x.*
- .*: e5bcf.* ldr pc, \[ip, #.*\]! ; 0x.*
+ .*: e28cca.* add ip, ip, #.* @ 0x.*
+ .*: e5bcf.* ldr pc, \[ip, #.*\]! @ 0x.*
.* <lib_func3@plt>:
.*: 4778 bx pc
.*: e7fd b.n .+ <.+>
.*: e28fc6.* add ip, pc, #.*
- .*: e28cca.* add ip, ip, #.* ; 0x.*
- .*: e5bcf.* ldr pc, \[ip, #.*\]! ; 0x.*
+ .*: e28cca.* add ip, ip, #.* @ 0x.*
+ .*: e5bcf.* ldr pc, \[ip, #.*\]! @ 0x.*
.* <lib_func4@plt>:
.*: 4778 bx pc
.*: e7fd b.n .+ <.+>
.*: e28fc6.* add ip, pc, #.*
- .*: e28cca.* add ip, ip, #.* ; 0x.*
- .*: e5bcf.* ldr pc, \[ip, #.*\]! ; 0x.*
+ .*: e28cca.* add ip, ip, #.* @ 0x.*
+ .*: e5bcf.* ldr pc, \[ip, #.*\]! @ 0x.*
Disassembly of section .text:
.* <__app_func_from_thumb>:
.*: 4778 bx pc
.*: e7fd b.n .+ <.+>
- .*: e59fc000 ldr ip, \[pc\] ; .* <__app_func_from_thumb\+0xc>
+ .*: e59fc000 ldr ip, \[pc\] @ .* <__app_func_from_thumb\+0xc>
.*: e08cf00f add pc, ip, pc
.*: feffff.. .word 0xfeffff..
.* <__lib_func4_from_thumb>:
.*: 4778 bx pc
.*: e7fd b.n .+ <.+>
- .*: e59fc000 ldr ip, \[pc\] ; .* <__lib_func4_from_thumb\+0xc>
+ .*: e59fc000 ldr ip, \[pc\] @ .* <__lib_func4_from_thumb\+0xc>
.*: e08cf00f add pc, ip, pc
.*: feffff.. .word 0xfeffff..
.* <__app_func_weak_from_thumb>:
.*: 4778 bx pc
.*: e7fd b.n .+ <.+>
- .*: e59fc000 ldr ip, \[pc\] ; .* <__app_func_weak_from_thumb\+0xc>
+ .*: e59fc000 ldr ip, \[pc\] @ .* <__app_func_weak_from_thumb\+0xc>
.*: e08cf00f add pc, ip, pc
.*: feffff.. .word 0xfeffff..
.* <__lib_func3_from_thumb>:
.*: 4778 bx pc
.*: e7fd b.n .+ <.+>
- .*: e59fc000 ldr ip, \[pc\] ; .* <__lib_func3_from_thumb\+0xc>
+ .*: e59fc000 ldr ip, \[pc\] @ .* <__lib_func3_from_thumb\+0xc>
.*: e08cf00f add pc, ip, pc
.*: feffff.. .word 0xfeffff..
...
.* <__app_func_weak_from_thumb>:
.*: 4778 bx pc
.*: e7fd b.n .+ <.+>
- .*: e59fc000 ldr ip, \[pc\] ; .* <__app_func_weak_from_thumb\+0xc>
+ .*: e59fc000 ldr ip, \[pc\] @ .* <__app_func_weak_from_thumb\+0xc>
.*: e08cf00f add pc, ip, pc
.*: fdffff34 .word 0xfdffff34
.* <__app_func_from_thumb>:
.*: 4778 bx pc
.*: e7fd b.n .+ <.+>
- .*: e59fc000 ldr ip, \[pc\] ; .* <__app_func_from_thumb\+0xc>
+ .*: e59fc000 ldr ip, \[pc\] @ .* <__app_func_from_thumb\+0xc>
.*: e08cf00f add pc, ip, pc
.*: fdffff14 .word 0xfdffff14
.* <lib_func3>:
- .*: e59fc004 ldr ip, \[pc, #4\] ; .* <lib_func3\+0xc>
+ .*: e59fc004 ldr ip, \[pc, #4\] @ .* <lib_func3\+0xc>
.*: e08cc00f add ip, ip, pc
.*: e12fff1c bx ip
.*: ffffffc5 .word 0xffffffc5
.* <lib_func2>:
- .*: e59fc004 ldr ip, \[pc, #4\] ; .* <lib_func2\+0xc>
+ .*: e59fc004 ldr ip, \[pc, #4\] @ .* <lib_func2\+0xc>
.*: e08cc00f add ip, ip, pc
.*: e12fff1c bx ip
.*: feffff55 .word 0xfeffff55
Disassembly of section .plt:
.* <.plt>:
- .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
- .*: e59fe004 ldr lr, \[pc, #4\] ; .* <.*>
+ .*: e52de004 push {lr} @ \(str lr, \[sp, #-4\]!\)
+ .*: e59fe004 ldr lr, \[pc, #4\] @ .* <.*>
.*: e08fe00e add lr, pc, lr
.*: e5bef008 ldr pc, \[lr, #8\]!
.*: .*
.* <app_func@plt>:
.*: e28fc6.* add ip, pc, #.*
- .*: e28cca.* add ip, ip, #.* ; 0x.*
+ .*: e28cca.* add ip, ip, #.* @ 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
.* <app_func_weak@plt>:
.*: e28fc6.* add ip, pc, #.*
- .*: e28cca.* add ip, ip, #.* ; 0x.*
+ .*: e28cca.* add ip, ip, #.* @ 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
.* <lib_func3@plt>:
.*: e28fc6.* add ip, pc, #.*
- .*: e28cca.* add ip, ip, #.* ; 0x.*
+ .*: e28cca.* add ip, ip, #.* @ 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
.* <lib_func4@plt>:
.*: e28fc6.* add ip, pc, #.*
- .*: e28cca.* add ip, ip, #.* ; 0x.*
+ .*: e28cca.* add ip, ip, #.* @ 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
Disassembly of section .text:
#...
.* <__lib_func3_from_thumb>:
- .*: e59fc000 ldr ip, \[pc\] ; .* <__lib_func3_from_thumb\+0x8>
+ .*: e59fc000 ldr ip, \[pc\] @ .* <__lib_func3_from_thumb\+0x8>
.*: e08ff00c add pc, pc, ip
.*: feffff.. .word 0xfeffff..
.* <__app_func_weak_from_thumb>:
- .*: e59fc000 ldr ip, \[pc\] ; .* <__app_func_weak_from_thumb\+0x8>
+ .*: e59fc000 ldr ip, \[pc\] @ .* <__app_func_weak_from_thumb\+0x8>
.*: e08ff00c add pc, pc, ip
.*: feffff.. .word 0xfeffff..
.* <__lib_func4_from_thumb>:
- .*: e59fc000 ldr ip, \[pc\] ; .* <__lib_func4_from_thumb\+0x8>
+ .*: e59fc000 ldr ip, \[pc\] @ .* <__lib_func4_from_thumb\+0x8>
.*: e08ff00c add pc, pc, ip
.*: feffff.. .word 0xfeffff..
.* <__app_func_from_thumb>:
- .*: e59fc000 ldr ip, \[pc\] ; .* <__app_func_from_thumb\+0x8>
+ .*: e59fc000 ldr ip, \[pc\] @ .* <__app_func_from_thumb\+0x8>
.*: e08ff00c add pc, pc, ip
.*: feffff.. .word 0xfeffff..
...
#...
.* <__app_func_weak_from_thumb>:
- .*: e59fc000 ldr ip, \[pc\] ; .* <__app_func_weak_from_thumb\+0x8>
+ .*: e59fc000 ldr ip, \[pc\] @ .* <__app_func_weak_from_thumb\+0x8>
.*: e08ff00c add pc, pc, ip
.*: fdffff40 .word 0xfdffff40
.* <__app_func_from_thumb>:
- .*: e59fc000 ldr ip, \[pc\] ; .* <__app_func_from_thumb\+0x8>
+ .*: e59fc000 ldr ip, \[pc\] @ .* <__app_func_from_thumb\+0x8>
.*: e08ff00c add pc, pc, ip
.*: fdffff28 .word 0xfdffff28
...
1f01014: f0ff effe blx 2001014 <bar>
01f01018 <__bar_from_thumb>:
- 1f01018: e59fc000 ldr ip, \[pc\] ; 1f01020 <__bar_from_thumb\+0x8>
+ 1f01018: e59fc000 ldr ip, \[pc\] @ 1f01020 <__bar_from_thumb\+0x8>
1f0101c: e08ff00c add pc, pc, ip
1f01020: 000ffff0 .word 0x000ffff0
1f01024: 00000000 .word 0x00000000
1f01014: f0ff effe blx 2001014 <bar>
01f01018 <__bar_from_thumb>:
- 1f01018: e51ff004 ldr pc, \[pc, #-4\] ; 1f0101c <__bar_from_thumb\+0x4>
+ 1f01018: e51ff004 ldr pc, \[pc, #-4\] @ 1f0101c <__bar_from_thumb\+0x4>
1f0101c: 02001014 .word 0x02001014
Disassembly of section .foo:
01f01018 <__bar_from_thumb>:
1f01018: 4778 bx pc
1f0101a: e7fd b.n .+ <.+>
- 1f0101c: e59fc000 ldr ip, \[pc\] ; 1f01024 <__bar_from_thumb\+0xc>
+ 1f0101c: e59fc000 ldr ip, \[pc\] @ 1f01024 <__bar_from_thumb\+0xc>
1f01020: e08cf00f add pc, ip, pc
1f01024: 000fffec .word 0x000fffec
01f01018 <__bar_from_thumb>:
1f01018: 4778 bx pc
1f0101a: e7fd b.n .+ <.+>
- 1f0101c: e51ff004 ldr pc, \[pc, #-4\] ; 1f01020 <__bar_from_thumb\+0x8>
+ 1f0101c: e51ff004 ldr pc, \[pc, #-4\] @ 1f01020 <__bar_from_thumb\+0x8>
1f01020: 02001014 .word 0x02001014
01f01024 <__bar_from_thumb>:
\.\.\.
00001008 <__bar_veneer>:
- 1008: e59fc004 ldr ip, \[pc, #4\] ; 1014 <__bar_veneer\+0xc>
+ 1008: e59fc004 ldr ip, \[pc, #4\] @ 1014 <__bar_veneer\+0xc>
100c: e08fc00c add ip, pc, ip
1010: e12fff1c bx ip
1014: 02000001 .word 0x02000001
\.\.\.
00001008 <__bar_veneer>:
- 1008: e51ff004 ldr pc, \[pc, #-4\] ; 100c <__bar_veneer\+0x4>
+ 1008: e51ff004 ldr pc, \[pc, #-4\] @ 100c <__bar_veneer\+0x4>
100c: 02001015 .word 0x02001015
Disassembly of section .foo:
00001008 <__myfunc_veneer>:
1008: b401 push {r0}
- 100a: 4802 ldr r0, \[pc, #8\] ; \(1014 <__myfunc_veneer\+0xc>\)
+ 100a: 4802 ldr r0, \[pc, #8\] @ \(1014 <__myfunc_veneer\+0xc>\)
100c: 4684 mov ip, r0
100e: bc01 pop {r0}
1010: 4760 bx ip
00001008 <__bar_veneer>:
1008: b401 push {r0}
- 100a: 4802 ldr r0, \[pc, #8\] ; \(1014 <__bar_veneer\+0xc>\)
+ 100a: 4802 ldr r0, \[pc, #8\] @ \(1014 <__bar_veneer\+0xc>\)
100c: 46fc mov ip, pc
100e: 4484 add ip, r0
1010: bc01 pop {r0}
00001008 <__bar_veneer>:
1008: b401 push {r0}
- 100a: 4802 ldr r0, \[pc, #8\] ; \(1014 <__bar_veneer\+0xc>\)
+ 100a: 4802 ldr r0, \[pc, #8\] @ \(1014 <__bar_veneer\+0xc>\)
100c: 4684 mov ip, r0
100e: bc01 pop {r0}
1010: 4760 bx ip
00001008 <__bar_veneer>:
1008: 4778 bx pc
100a: e7fd b.n .+ <.+>
- 100c: e59fc004 ldr ip, \[pc, #4\] ; 1018 <__bar_veneer\+0x10>
+ 100c: e59fc004 ldr ip, \[pc, #4\] @ 1018 <__bar_veneer\+0x10>
1010: e08fc00c add ip, pc, ip
1014: e12fff1c bx ip
1018: 01fffffd .word 0x01fffffd
00001008 <__bar_veneer>:
1008: 4778 bx pc
100a: e7fd b.n .+ <.+>
- 100c: e59fc000 ldr ip, \[pc\] ; 1014 <__bar_veneer\+0xc>
+ 100c: e59fc000 ldr ip, \[pc\] @ 1014 <__bar_veneer\+0xc>
1010: e12fff1c bx ip
1014: 02001015 .word 0x02001015
Disassembly of section .foo:
\.\.\.
02001028 <__bar_veneer>:
- 2001028: f241 0c01 movw ip, #4097 ; 0x1001
+ 2001028: f241 0c01 movw ip, #4097 @ 0x1001
200102c: f2c0 0c00 movt ip, #0
2001030: 4760 bx ip
2001032: 0000 movs r0, r0
\.\.\.
00001008 <__bar_veneer>:
- 1008: f85f f000 ldr.w pc, \[pc\] ; 100c <__bar_veneer\+0x4>
+ 1008: f85f f000 ldr.w pc, \[pc\] @ 100c <__bar_veneer\+0x4>
100c: 02001015 .word 0x02001015
Disassembly of section .foo:
Disassembly of section .plt:
.* <.plt>:
- .*: f8df c00c ldr.w ip, \[pc, #12\] ; .* <.plt\+0x10>
+ .*: f8df c00c ldr.w ip, \[pc, #12\] @ .* <.plt\+0x10>
.*: eb0c 0c09 add.w ip, ip, r9
.*: f8dc 9004 ldr.w r9, \[ip, #4\]
.*: f8dc f000 ldr.w pc, \[ip\]
.*: 0000000c .word 0x0000000c
.*: 00000000 .word 0x00000000
- .*: f85f c008 ldr.w ip, \[pc, #-8\] ; .* <.plt\+0x14>
+ .*: f85f c008 ldr.w ip, \[pc, #-8\] @ .* <.plt\+0x14>
.*: f84d cd04 str.w ip, \[sp, #-4\]!
.*: f8d9 c004 ldr.w ip, \[r9, #4\]
.*: f8d9 f000 ldr.w pc, \[r9\]
- .*: f8df c00c ldr.w ip, \[pc, #12\] ; .* <.plt\+0x38>
+ .*: f8df c00c ldr.w ip, \[pc, #12\] @ .* <.plt\+0x38>
.*: eb0c 0c09 add.w ip, ip, r9
.*: f8dc 9004 ldr.w r9, \[ip, #4\]
.*: f8dc f000 ldr.w pc, \[ip]
.*: 00000014 .word 0x00000014
.*: 00000008 .word 0x00000008
- .*: f85f c008 ldr.w ip, \[pc, #-8\] ; .* <.plt\+0x3c>
+ .*: f85f c008 ldr.w ip, \[pc, #-8\] @ .* <.plt\+0x3c>
.*: f84d cd04 str.w ip, \[sp, #-4\]!
.*: f8d9 c004 ldr.w ip, \[r9, #4\]
.*: f8d9 f000 ldr.w pc, \[r9\]
.*: f000 b800 b.w .* <main>
.* <main>:
- .*: 4a11 ldr r2, \[pc, #68\] ; .* <main\+0x48>.*
- .*: 4b12 ldr r3, \[pc, #72\] ; .* <main\+0x4c>.*
+ .*: 4a11 ldr r2, \[pc, #68\] @ .* <main\+0x48>.*
+ .*: 4b12 ldr r3, \[pc, #72\] @ .* <main\+0x4c>.*
.*: b570 push {r4, r5, r6, lr}
.*: f859 5002 ldr.w r5, \[r9, r2\]
.*: 464c mov r4, r9
.*: 6828 ldr r0, \[r5, #0\]
.*: 46a1 mov r9, r4
.*: f7ff ffd9 bl .* <.plt\+0x28>
- .*: 4b0b ldr r3, \[pc, #44\] ; .* <main\+0x50>.*
+ .*: 4b0b ldr r3, \[pc, #44\] @ .* <main\+0x50>.*
.*: 46a1 mov r9, r4
.*: 444b add r3, r9
.*: 4618 mov r0, r3
.*: 602b str r3, \[r5, #0\]
.*: 46a1 mov r9, r4
.*: f7ff ffd1 bl .* <.plt\+0x28>
- .*: 4b08 ldr r3, \[pc, #32\] ; .* <main\+0x54>.*
+ .*: 4b08 ldr r3, \[pc, #32\] @ .* <main\+0x54>.*
.*: 46a1 mov r9, r4
.*: f859 3003 ldr.w r3, \[r9, r3\]
.*: 6818 ldr r0, \[r3, #0\]
Disassembly of section .plt:
.* <.plt>:
- .*: e59fc008 ldr ip, \[pc, #8\] ; .* <.plt\+0x10>
+ .*: e59fc008 ldr ip, \[pc, #8\] @ .* <.plt\+0x10>
.*: e08cc009 add ip, ip, r9
.*: e59c9004 ldr r9, \[ip, #4\]
.*: e59cf000 ldr pc, \[ip\]
.*: 0000000c .word 0x0000000c
.*: 00000000 .word 0x00000000
- .*: e51fc00c ldr ip, \[pc, #-12\] ; .* <.plt\+0x14>
+ .*: e51fc00c ldr ip, \[pc, #-12\] @ .* <.plt\+0x14>
.*: e92d1000 stmfd sp!, {ip}
.*: e599c004 ldr ip, \[r9, #4\]
.*: e599f000 ldr pc, \[r9\]
- .*: e59fc008 ldr ip, \[pc, #8\] ; .* <.plt\+0x38>
+ .*: e59fc008 ldr ip, \[pc, #8\] @ .* <.plt\+0x38>
.*: e08cc009 add ip, ip, r9
.*: e59c9004 ldr r9, \[ip, #4\]
.*: e59cf000 ldr pc, \[ip]
.*: 00000014 .word 0x00000014
.*: 00000008 .word 0x00000008
- .*: e51fc00c ldr ip, \[pc, #-12\] ; .* <.plt\+0x3c>
+ .*: e51fc00c ldr ip, \[pc, #-12\] @ .* <.plt\+0x3c>
.*: e92d1000 stmfd sp!, {ip}
.*: e599c004 ldr ip, \[r9, #4\]
.*: e599f000 ldr pc, \[r9\]
.*: eaffffff b .* <main>
.* <main>:
- .*: e59f206c ldr r2, \[pc, #108\] ; .* <main\+0x74>
- .*: e59f306c ldr r3, \[pc, #108\] ; .* <main\+0x78>
+ .*: e59f206c ldr r2, \[pc, #108\] @ .* <main\+0x74>
+ .*: e59f306c ldr r3, \[pc, #108\] @ .* <main\+0x78>
.*: e92d4070 push {r4, r5, r6, lr}
.*: e7995002 ldr r5, \[r9, r2\]
.*: e1a04009 mov r4, r9
.*: e5950000 ldr r0, \[r5\]
.*: e1a09004 mov r9, r4
.*: ebffffe7 bl .* <.plt\+0x28>
- .*: e59f3040 ldr r3, \[pc, #64\] ; .* <main\+0x7c>
+ .*: e59f3040 ldr r3, \[pc, #64\] @ .* <main\+0x7c>
.*: e1a09004 mov r9, r4
.*: e0833009 add r3, r3, r9
.*: e1a00003 mov r0, r3
.*: e5853000 str r3, \[r5\]
.*: e1a09004 mov r9, r4
.*: ebffffe0 bl .* <.plt\+0x28>
- .*: e59f3028 ldr r3, \[pc, #40\] ; .* <main\+0x80>
+ .*: e59f3028 ldr r3, \[pc, #40\] @ .* <main\+0x80>
.*: e1a09004 mov r9, r4
.*: e7993003 ldr r3, \[r9, r3\]
.*: e5930000 ldr r0, \[r3\]
Disassembly of section .plt:
.* <.plt>:
- .*: f8df c00c ldr.w ip, \[pc, #12\] ; .* <.plt\+0x10>
+ .*: f8df c00c ldr.w ip, \[pc, #12\] @ .* <.plt\+0x10>
.*: eb0c 0c09 add.w ip, ip, r9
.*: f8dc 9004 ldr.w r9, \[ip, #4\]
.*: f8dc f000 ldr.w pc, \[ip\]
.*: 0000000c .word 0x0000000c
.*: 00000000 .word 0x00000000
- .*: f85f c008 ldr.w ip, \[pc, #-8\] ; .* <.plt\+0x14>
+ .*: f85f c008 ldr.w ip, \[pc, #-8\] @ .* <.plt\+0x14>
.*: f84d cd04 str.w ip, \[sp, #-4\]!
.*: f8d9 c004 ldr.w ip, \[r9, #4\]
.*: f8d9 f000 ldr.w pc, \[r9\]
Disassembly of section .plt:
.* <.plt>:
- .*: e59fc008 ldr ip, \[pc, #8\] ; .* <.plt\+0x10>
+ .*: e59fc008 ldr ip, \[pc, #8\] @ .* <.plt\+0x10>
.*: e08cc009 add ip, ip, r9
.*: e59c9004 ldr r9, \[ip, #4\]
.*: e59cf000 ldr pc, \[ip\]
.*: 0000000c .word 0x0000000c
.*: 00000000 .word 0x00000000
- .*: e51fc00c ldr ip, \[pc, #-12\] ; .* <.plt\+0x14>
+ .*: e51fc00c ldr ip, \[pc, #-12\] @ .* <.plt\+0x14>
.*: e92d1000 stmfd sp!, {ip}
.*: e599c004 ldr ip, \[r9, #4\]
.*: e599f000 ldr pc, \[r9\]
+[0-9a-f]+: f000 e800 blx 2001018 <__func_to_branch_to_veneer>
[0-9a-f]+ <__func_to_branch_to_veneer>:
- +[0-9a-f]+: e51ff004 ldr pc, \[pc, #-4\] ; 200101c <__func_to_branch_to_veneer\+0x4>
+ +[0-9a-f]+: e51ff004 ldr pc, \[pc, #-4\] @ 200101c <__func_to_branch_to_veneer\+0x4>
+[0-9a-f]+: ........ .word 0x........
Disassembly of section .text:
[0-9a-f]+ <__func_to_branch_to_veneer>:
+[0-9a-f]+: 4778 bx pc
+[0-9a-f]+: e7fd b.n .+ <.+>
- +[0-9a-f]+: e51ff004 ldr pc, \[pc, #-4\] ; 2001020 <__func_to_branch_to_veneer\+0x8>
+ +[0-9a-f]+: e51ff004 ldr pc, \[pc, #-4\] @ 2001020 <__func_to_branch_to_veneer\+0x8>
+[0-9a-f]+: ........ .word 0x........
+[0-9a-f]+: 00000000 .word 0x00000000
Disassembly of section .text:
0+[0-9a-f]+ <_start>:
-\s*[0-9a-f]+:\s+e52de004\s+push {lr} ; \(str lr, \[sp, #-4\]!\)
+\s*[0-9a-f]+:\s+e52de004\s+push {lr} @ \(str lr, \[sp, #-4\]!\)
\s*[0-9a-f]+:\s+eb000000\s+bl [0-9a-f]+ <hidfn>
\s*[0-9a-f]+:\s+e8bd8000\s+ldmfd sp!, {pc}
Disassembly of section .text:
00008000 <_start>:
- 8000: e28f00bc add r0, pc, #188 ; 0xbc
- 8004: e28f0c6e add r0, pc, #28160 ; 0x6e00
- 8008: e28000ec add r0, r0, #236 ; 0xec
- 800c: e28f08ff add r0, pc, #16711680 ; 0xff0000
- 8010: e2800c6e add r0, r0, #28160 ; 0x6e00
- 8014: e28000e4 add r0, r0, #228 ; 0xe4
+ 8000: e28f00bc add r0, pc, #188 @ 0xbc
+ 8004: e28f0c6e add r0, pc, #28160 @ 0x6e00
+ 8008: e28000ec add r0, r0, #236 @ 0xec
+ 800c: e28f08ff add r0, pc, #16711680 @ 0xff0000
+ 8010: e2800c6e add r0, r0, #28160 @ 0x6e00
+ 8014: e28000e4 add r0, r0, #228 @ 0xe4
8018: e280000c add r0, r0, #12
- 801c: e2800cee add r0, r0, #60928 ; 0xee00
- 8020: e28000f0 add r0, r0, #240 ; 0xf0
- 8024: e28008ff add r0, r0, #16711680 ; 0xff0000
- 8028: e2800cee add r0, r0, #60928 ; 0xee00
- 802c: e28000f0 add r0, r0, #240 ; 0xf0
- 8030: e28f0c6e add r0, pc, #28160 ; 0x6e00
+ 801c: e2800cee add r0, r0, #60928 @ 0xee00
+ 8020: e28000f0 add r0, r0, #240 @ 0xf0
+ 8024: e28008ff add r0, r0, #16711680 @ 0xff0000
+ 8028: e2800cee add r0, r0, #60928 @ 0xee00
+ 802c: e28000f0 add r0, r0, #240 @ 0xf0
+ 8030: e28f0c6e add r0, pc, #28160 @ 0x6e00
8034: e59010c0 ldr r1, \[r0, #192\].*
- 8038: e28f08ff add r0, pc, #16711680 ; 0xff0000
- 803c: e2800c6e add r0, r0, #28160 ; 0x6e00
+ 8038: e28f08ff add r0, pc, #16711680 @ 0xff0000
+ 803c: e2800c6e add r0, r0, #28160 @ 0x6e00
8040: e59010b8 ldr r1, \[r0, #184\].*
8044: e590100c ldr r1, \[r0, #12\]
- 8048: e2800cee add r0, r0, #60928 ; 0xee00
+ 8048: e2800cee add r0, r0, #60928 @ 0xee00
804c: e59010f0 ldr r1, \[r0, #240\].*
- 8050: e28008ff add r0, r0, #16711680 ; 0xff0000
- 8054: e2800cee add r0, r0, #60928 ; 0xee00
+ 8050: e28008ff add r0, r0, #16711680 @ 0xff0000
+ 8054: e2800cee add r0, r0, #60928 @ 0xee00
8058: e59010f0 ldr r1, \[r0, #240\].*
805c: e1cf26d0 ldrd r2, \[pc, #96\].*
- 8060: e28f0c6e add r0, pc, #28160 ; 0x6e00
+ 8060: e28f0c6e add r0, pc, #28160 @ 0x6e00
8064: e1c029d0 ldrd r2, \[r0, #144\].*
- 8068: e28f08ff add r0, pc, #16711680 ; 0xff0000
- 806c: e2800c6e add r0, r0, #28160 ; 0x6e00
+ 8068: e28f08ff add r0, pc, #16711680 @ 0xff0000
+ 806c: e2800c6e add r0, r0, #28160 @ 0x6e00
8070: e1c028d8 ldrd r2, \[r0, #136\].*
8074: e1c020dc ldrd r2, \[r0, #12\]
- 8078: e2800cee add r0, r0, #60928 ; 0xee00
+ 8078: e2800cee add r0, r0, #60928 @ 0xee00
807c: e1c02fd0 ldrd r2, \[r0, #240\].*
- 8080: e28008ff add r0, r0, #16711680 ; 0xff0000
- 8084: e2800cee add r0, r0, #60928 ; 0xee00
+ 8080: e28008ff add r0, r0, #16711680 @ 0xff0000
+ 8084: e2800cee add r0, r0, #60928 @ 0xee00
8088: e1c02fd0 ldrd r2, \[r0, #240\].*
808c: ed9f000c ldc 0, cr0, \[pc, #48\].*
- 8090: e28f0c6e add r0, pc, #28160 ; 0x6e00
+ 8090: e28f0c6e add r0, pc, #28160 @ 0x6e00
8094: ed900018 ldc 0, cr0, \[r0, #96\].*
- 8098: e28f08ff add r0, pc, #16711680 ; 0xff0000
- 809c: e2800c6e add r0, r0, #28160 ; 0x6e00
+ 8098: e28f08ff add r0, pc, #16711680 @ 0xff0000
+ 809c: e2800c6e add r0, r0, #28160 @ 0x6e00
80a0: ed900016 ldc 0, cr0, \[r0, #88\].*
80a4: ed900003 ldc 0, cr0, \[r0, #12\]
- 80a8: e2800cee add r0, r0, #60928 ; 0xee00
+ 80a8: e2800cee add r0, r0, #60928 @ 0xee00
80ac: ed90003c ldc 0, cr0, \[r0, #240\].*
- 80b0: e28008ff add r0, r0, #16711680 ; 0xff0000
- 80b4: e2800cee add r0, r0, #60928 ; 0xee00
+ 80b0: e28008ff add r0, r0, #16711680 @ 0xff0000
+ 80b4: e2800cee add r0, r0, #60928 @ 0xee00
80b8: ed90003c ldc 0, cr0, \[r0, #240\].*
000080bc <one_group_needed_alu_pc>:
#------ f1's .iplt entry
#------------------------------------------------------------------------------
9000: e28fc600 add ip, pc, #0, 12
- 9004: e28cca08 add ip, ip, #8, 20 ; 0x8000
+ 9004: e28cca08 add ip, ip, #8, 20 @ 0x8000
9008: e5bcf004 ldr pc, \[ip, #4\]!
0000900c <f3>:
900c: e28fc600 add ip, pc, #0, 12
- 9010: e28cca07 add ip, ip, #28672 ; 0x7000
- 9014: e5bcfffc ldr pc, \[ip, #4092\]! ; 0xffc
+ 9010: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9014: e5bcfffc ldr pc, \[ip, #4092\]! @ 0xffc
00009018 <f2>:
9018: e28fc600 add ip, pc, #0, 12
- 901c: e28cca07 add ip, ip, #28672 ; 0x7000
- 9020: e5bcfff4 ldr pc, \[ip, #4084\]! ; 0xff4
+ 901c: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9020: e5bcfff4 ldr pc, \[ip, #4084\]! @ 0xff4
Disassembly of section \.text:
0000a00c <_start>:
a00c: eb0017fb bl 10000 <foo>
- a010: e59f400c ldr r4, \[pc, #12\] ; a024 <_start\+0x18>
- a014: e59f400c ldr r4, \[pc, #12\] ; a028 <_start\+0x1c>
- a018: e59f400c ldr r4, \[pc, #12\] ; a02c <_start\+0x20>
- a01c: e59f400c ldr r4, \[pc, #12\] ; a030 <_start\+0x24>
- a020: e59f500c ldr r5, \[pc, #12\] ; a034 <_start\+0x28>
+ a010: e59f400c ldr r4, \[pc, #12\] @ a024 <_start\+0x18>
+ a014: e59f400c ldr r4, \[pc, #12\] @ a028 <_start\+0x1c>
+ a018: e59f400c ldr r4, \[pc, #12\] @ a02c <_start\+0x20>
+ a01c: e59f400c ldr r4, \[pc, #12\] @ a030 <_start\+0x24>
+ a020: e59f500c ldr r5, \[pc, #12\] @ a034 <_start\+0x28>
#------------------------------------------------------------------------------
#------ foo
#------------------------------------------------------------------------------
#------ f1's .iplt entry
#------------------------------------------------------------------------------
a038: ebfffbf0 bl 9000 <__irel_end\+0xfe8>
- a03c: e59f400c ldr r4, \[pc, #12\] ; a050 <_start\+0x44>
- a040: e59f400c ldr r4, \[pc, #12\] ; a054 <_start\+0x48>
- a044: e59f400c ldr r4, \[pc, #12\] ; a058 <_start\+0x4c>
- a048: e59f400c ldr r4, \[pc, #12\] ; a05c <_start\+0x50>
- a04c: e59f500c ldr r5, \[pc, #12\] ; a060 <_start\+0x54>
+ a03c: e59f400c ldr r4, \[pc, #12\] @ a050 <_start\+0x44>
+ a040: e59f400c ldr r4, \[pc, #12\] @ a054 <_start\+0x48>
+ a044: e59f400c ldr r4, \[pc, #12\] @ a058 <_start\+0x4c>
+ a048: e59f400c ldr r4, \[pc, #12\] @ a05c <_start\+0x50>
+ a04c: e59f500c ldr r5, \[pc, #12\] @ a060 <_start\+0x54>
#------------------------------------------------------------------------------
#------ f1's .iplt entry
#------------------------------------------------------------------------------
#------------------------------------------------------------------------------
a060: 00006fbc \.word 0x00006fbc
a064: ebfffbeb bl 9018 <f2>
- a068: e59f400c ldr r4, \[pc, #12\] ; a07c <_start\+0x70>
- a06c: e59f400c ldr r4, \[pc, #12\] ; a080 <_start\+0x74>
- a070: e59f400c ldr r4, \[pc, #12\] ; a084 <_start\+0x78>
- a074: e59f400c ldr r4, \[pc, #12\] ; a088 <_start\+0x7c>
- a078: e59f500c ldr r5, \[pc, #12\] ; a08c <_start\+0x80>
+ a068: e59f400c ldr r4, \[pc, #12\] @ a07c <_start\+0x70>
+ a06c: e59f400c ldr r4, \[pc, #12\] @ a080 <_start\+0x74>
+ a070: e59f400c ldr r4, \[pc, #12\] @ a084 <_start\+0x78>
+ a074: e59f400c ldr r4, \[pc, #12\] @ a088 <_start\+0x7c>
+ a078: e59f500c ldr r5, \[pc, #12\] @ a08c <_start\+0x80>
#------------------------------------------------------------------------------
#------ f2
#------------------------------------------------------------------------------
#------------------------------------------------------------------------------
a08c: 00006f9c \.word 0x00006f9c
a090: ebfffbdd bl 900c <f3>
- a094: e59f400c ldr r4, \[pc, #12\] ; a0a8 <_start\+0x9c>
- a098: e59f400c ldr r4, \[pc, #12\] ; a0ac <_start\+0xa0>
- a09c: e59f400c ldr r4, \[pc, #12\] ; a0b0 <_start\+0xa4>
- a0a0: e59f400c ldr r4, \[pc, #12\] ; a0b4 <_start\+0xa8>
- a0a4: e59f500c ldr r5, \[pc, #12\] ; a0b8 <_start\+0xac>
+ a094: e59f400c ldr r4, \[pc, #12\] @ a0a8 <_start\+0x9c>
+ a098: e59f400c ldr r4, \[pc, #12\] @ a0ac <_start\+0xa0>
+ a09c: e59f400c ldr r4, \[pc, #12\] @ a0b0 <_start\+0xa4>
+ a0a0: e59f400c ldr r4, \[pc, #12\] @ a0b4 <_start\+0xa8>
+ a0a4: e59f500c ldr r5, \[pc, #12\] @ a0b8 <_start\+0xac>
#------------------------------------------------------------------------------
#------ f3
#------------------------------------------------------------------------------
Disassembly of section \.plt:
00009000 <.plt>:
- 9000: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
- 9004: e59fe004 ldr lr, \[pc, #4\] ; 9010 <.*>
+ 9000: e52de004 push {lr} @ \(str lr, \[sp, #-4\]!\)
+ 9004: e59fe004 ldr lr, \[pc, #4\] @ 9010 <.*>
9008: e08fe00e add lr, pc, lr
900c: e5bef008 ldr pc, \[lr, #8\]!
#------------------------------------------------------------------------------
#------ atf2's .plt entry
#------------------------------------------------------------------------------
9018: e28fc600 add ip, pc, #0, 12
- 901c: e28cca07 add ip, ip, #28672 ; 0x7000
- 9020: e5bcffec ldr pc, \[ip, #4076\]! ; 0xfec
+ 901c: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9020: e5bcffec ldr pc, \[ip, #4076\]! @ 0xfec
#------------------------------------------------------------------------------
#------ aaf4's .plt entry
#------------------------------------------------------------------------------
00009024 <aaf4@plt>:
9024: e28fc600 add ip, pc, #0, 12
- 9028: e28cca07 add ip, ip, #28672 ; 0x7000
- 902c: e5bcffe4 ldr pc, \[ip, #4068\]! ; 0xfe4
+ 9028: e28cca07 add ip, ip, #28672 @ 0x7000
+ 902c: e5bcffe4 ldr pc, \[ip, #4068\]! @ 0xfe4
#------------------------------------------------------------------------------
#------ thumb entry to ttf2's .plt entry
#------------------------------------------------------------------------------
#------ ttf2's .plt entry
#------------------------------------------------------------------------------
9034: e28fc600 add ip, pc, #0, 12
- 9038: e28cca07 add ip, ip, #28672 ; 0x7000
- 903c: e5bcffd8 ldr pc, \[ip, #4056\]! ; 0xfd8
+ 9038: e28cca07 add ip, ip, #28672 @ 0x7000
+ 903c: e5bcffd8 ldr pc, \[ip, #4056\]! @ 0xfd8
#------------------------------------------------------------------------------
#------ thumb entry to tbf2's .plt entry
#------------------------------------------------------------------------------
#------ tbf2's .plt entry
#------------------------------------------------------------------------------
9044: e28fc600 add ip, pc, #0, 12
- 9048: e28cca07 add ip, ip, #28672 ; 0x7000
- 904c: e5bcffcc ldr pc, \[ip, #4044\]! ; 0xfcc
+ 9048: e28cca07 add ip, ip, #28672 @ 0x7000
+ 904c: e5bcffcc ldr pc, \[ip, #4044\]! @ 0xfcc
#------------------------------------------------------------------------------
#------ taf2's .plt entry
#------------------------------------------------------------------------------
00009050 <taf2@plt>:
9050: e28fc600 add ip, pc, #0, 12
- 9054: e28cca07 add ip, ip, #28672 ; 0x7000
- 9058: e5bcffc4 ldr pc, \[ip, #4036\]! ; 0xfc4
+ 9054: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9058: e5bcffc4 ldr pc, \[ip, #4036\]! @ 0xfc4
#------------------------------------------------------------------------------
#------ aaf2's .plt entry
#------------------------------------------------------------------------------
0000905c <aaf2@plt>:
905c: e28fc600 add ip, pc, #0, 12
- 9060: e28cca07 add ip, ip, #28672 ; 0x7000
- 9064: e5bcffbc ldr pc, \[ip, #4028\]! ; 0xfbc
+ 9060: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9064: e5bcffbc ldr pc, \[ip, #4028\]! @ 0xfbc
#------------------------------------------------------------------------------
#------ thumb entry to abf4's .plt entry
#------------------------------------------------------------------------------
#------ abf4's .plt entry
#------------------------------------------------------------------------------
906c: e28fc600 add ip, pc, #0, 12
- 9070: e28cca07 add ip, ip, #28672 ; 0x7000
- 9074: e5bcffb0 ldr pc, \[ip, #4016\]! ; 0xfb0
+ 9070: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9074: e5bcffb0 ldr pc, \[ip, #4016\]! @ 0xfb0
#------------------------------------------------------------------------------
#------ thumb entry to tbf4's .plt entry
#------------------------------------------------------------------------------
#------ tbf4's .plt entry
#------------------------------------------------------------------------------
907c: e28fc600 add ip, pc, #0, 12
- 9080: e28cca07 add ip, ip, #28672 ; 0x7000
- 9084: e5bcffa4 ldr pc, \[ip, #4004\]! ; 0xfa4
+ 9080: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9084: e5bcffa4 ldr pc, \[ip, #4004\]! @ 0xfa4
#------------------------------------------------------------------------------
#------ thumb entry to ttf4's .plt entry
#------------------------------------------------------------------------------
#------ ttf4's .plt entry
#------------------------------------------------------------------------------
908c: e28fc600 add ip, pc, #0, 12
- 9090: e28cca07 add ip, ip, #28672 ; 0x7000
- 9094: e5bcff98 ldr pc, \[ip, #3992\]! ; 0xf98
+ 9090: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9094: e5bcff98 ldr pc, \[ip, #3992\]! @ 0xf98
#------------------------------------------------------------------------------
#------ thumb entry to atf4's .plt entry
#------------------------------------------------------------------------------
#------ atf4's .plt entry
#------------------------------------------------------------------------------
909c: e28fc600 add ip, pc, #0, 12
- 90a0: e28cca07 add ip, ip, #28672 ; 0x7000
- 90a4: e5bcff8c ldr pc, \[ip, #3980\]! ; 0xf8c
+ 90a0: e28cca07 add ip, ip, #28672 @ 0x7000
+ 90a4: e5bcff8c ldr pc, \[ip, #3980\]! @ 0xf8c
#------------------------------------------------------------------------------
#------ taf4's .plt entry
#------------------------------------------------------------------------------
000090a8 <taf4@plt>:
90a8: e28fc600 add ip, pc, #0, 12
- 90ac: e28cca07 add ip, ip, #28672 ; 0x7000
- 90b0: e5bcff84 ldr pc, \[ip, #3972\]! ; 0xf84
+ 90ac: e28cca07 add ip, ip, #28672 @ 0x7000
+ 90b0: e5bcff84 ldr pc, \[ip, #3972\]! @ 0xf84
#------------------------------------------------------------------------------
#------ thumb entry to abf2's .plt entry
#------------------------------------------------------------------------------
#------ abf2's .plt entry
#------------------------------------------------------------------------------
90b8: e28fc600 add ip, pc, #0, 12
- 90bc: e28cca07 add ip, ip, #28672 ; 0x7000
- 90c0: e5bcff78 ldr pc, \[ip, #3960\]! ; 0xf78
+ 90bc: e28cca07 add ip, ip, #28672 @ 0x7000
+ 90c0: e5bcff78 ldr pc, \[ip, #3960\]! @ 0xf78
Disassembly of section \.iplt:
#------ aaf1's .iplt entry
#------------------------------------------------------------------------------
90c4: e28fc600 add ip, pc, #0, 12
- 90c8: e28cca07 add ip, ip, #28672 ; 0x7000
- 90cc: e5bcff70 ldr pc, \[ip, #3952\]! ; 0xf70
+ 90c8: e28cca07 add ip, ip, #28672 @ 0x7000
+ 90cc: e5bcff70 ldr pc, \[ip, #3952\]! @ 0xf70
#------------------------------------------------------------------------------
#------ thumb entry to atf1's .iplt entry
#------------------------------------------------------------------------------
#------ atf1's .iplt entry
#------------------------------------------------------------------------------
90d4: e28fc600 add ip, pc, #0, 12
- 90d8: e28cca07 add ip, ip, #28672 ; 0x7000
- 90dc: e5bcff64 ldr pc, \[ip, #3940\]! ; 0xf64
+ 90d8: e28cca07 add ip, ip, #28672 @ 0x7000
+ 90dc: e5bcff64 ldr pc, \[ip, #3940\]! @ 0xf64
#------------------------------------------------------------------------------
#------ thumb entry to abf1's .iplt entry
#------------------------------------------------------------------------------
#------ abf1's .iplt entry
#------------------------------------------------------------------------------
90e4: e28fc600 add ip, pc, #0, 12
- 90e8: e28cca07 add ip, ip, #28672 ; 0x7000
- 90ec: e5bcff58 ldr pc, \[ip, #3928\]! ; 0xf58
+ 90e8: e28cca07 add ip, ip, #28672 @ 0x7000
+ 90ec: e5bcff58 ldr pc, \[ip, #3928\]! @ 0xf58
#------------------------------------------------------------------------------
#------ taf1's .iplt entry
#------------------------------------------------------------------------------
90f0: e28fc600 add ip, pc, #0, 12
- 90f4: e28cca07 add ip, ip, #28672 ; 0x7000
- 90f8: e5bcff50 ldr pc, \[ip, #3920\]! ; 0xf50
+ 90f4: e28cca07 add ip, ip, #28672 @ 0x7000
+ 90f8: e5bcff50 ldr pc, \[ip, #3920\]! @ 0xf50
#------------------------------------------------------------------------------
#------ thumb entry to ttf1's .iplt entry
#------------------------------------------------------------------------------
#------ ttf1's .iplt entry
#------------------------------------------------------------------------------
9100: e28fc600 add ip, pc, #0, 12
- 9104: e28cca07 add ip, ip, #28672 ; 0x7000
- 9108: e5bcff44 ldr pc, \[ip, #3908\]! ; 0xf44
+ 9104: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9108: e5bcff44 ldr pc, \[ip, #3908\]! @ 0xf44
#------------------------------------------------------------------------------
#------ thumb entry to tbf1's .iplt entry
#------------------------------------------------------------------------------
#------ tbf1's .iplt entry
#------------------------------------------------------------------------------
9110: e28fc600 add ip, pc, #0, 12
- 9114: e28cca07 add ip, ip, #28672 ; 0x7000
- 9118: e5bcff38 ldr pc, \[ip, #3896\]! ; 0xf38
+ 9114: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9118: e5bcff38 ldr pc, \[ip, #3896\]! @ 0xf38
#------------------------------------------------------------------------------
#------ thumb entry to atf3
#------------------------------------------------------------------------------
00009120 <atf3>:
9120: e28fc600 add ip, pc, #0, 12
- 9124: e28cca07 add ip, ip, #28672 ; 0x7000
- 9128: e5bcff2c ldr pc, \[ip, #3884\]! ; 0xf2c
+ 9124: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9128: e5bcff2c ldr pc, \[ip, #3884\]! @ 0xf2c
#------------------------------------------------------------------------------
#------ thumb entry to abf3
#------------------------------------------------------------------------------
00009130 <abf3>:
9130: e28fc600 add ip, pc, #0, 12
- 9134: e28cca07 add ip, ip, #28672 ; 0x7000
- 9138: e5bcff20 ldr pc, \[ip, #3872\]! ; 0xf20
+ 9134: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9138: e5bcff20 ldr pc, \[ip, #3872\]! @ 0xf20
#------------------------------------------------------------------------------
#------ thumb entry to ttf3
#------------------------------------------------------------------------------
00009140 <ttf3>:
9140: e28fc600 add ip, pc, #0, 12
- 9144: e28cca07 add ip, ip, #28672 ; 0x7000
- 9148: e5bcff14 ldr pc, \[ip, #3860\]! ; 0xf14
+ 9144: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9148: e5bcff14 ldr pc, \[ip, #3860\]! @ 0xf14
#------------------------------------------------------------------------------
#------ thumb entry to tbf3
#------------------------------------------------------------------------------
00009150 <tbf3>:
9150: e28fc600 add ip, pc, #0, 12
- 9154: e28cca07 add ip, ip, #28672 ; 0x7000
- 9158: e5bcff08 ldr pc, \[ip, #3848\]! ; 0xf08
+ 9154: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9158: e5bcff08 ldr pc, \[ip, #3848\]! @ 0xf08
0000915c <taf3>:
915c: e28fc600 add ip, pc, #0, 12
- 9160: e28cca07 add ip, ip, #28672 ; 0x7000
- 9164: e5bcff00 ldr pc, \[ip, #3840\]! ; 0xf00
+ 9160: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9164: e5bcff00 ldr pc, \[ip, #3840\]! @ 0xf00
00009168 <aaf3>:
9168: e28fc600 add ip, pc, #0, 12
- 916c: e28cca07 add ip, ip, #28672 ; 0x7000
- 9170: e5bcfef8 ldr pc, \[ip, #3832\]! ; 0xef8
+ 916c: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9170: e5bcfef8 ldr pc, \[ip, #3832\]! @ 0xef8
Disassembly of section \.text:
a028: eb0017f4 bl 10000 <foo>
a02c: ea0017f3 b 10000 <foo>
a030: 0a0017f2 beq 10000 <foo>
- a034: e59f4000 ldr r4, \[pc\] ; a03c <_start\+0x14>
- a038: e59f4000 ldr r4, \[pc\] ; a040 <_start\+0x18>
+ a034: e59f4000 ldr r4, \[pc\] @ a03c <_start\+0x14>
+ a038: e59f4000 ldr r4, \[pc\] @ a040 <_start\+0x18>
#------------------------------------------------------------------------------
#------ .got offset for foo
#------------------------------------------------------------------------------
#------ aaf1's .iplt entry
#------------------------------------------------------------------------------
a04c: 0afffc1c beq 90c4 <abf2@plt\+0x10>
- a050: e59f4000 ldr r4, \[pc\] ; a058 <_start\+0x30>
- a054: e59f4000 ldr r4, \[pc\] ; a05c <_start\+0x34>
+ a050: e59f4000 ldr r4, \[pc\] @ a058 <_start\+0x30>
+ a054: e59f4000 ldr r4, \[pc\] @ a05c <_start\+0x34>
#------------------------------------------------------------------------------
#------ .got offset for aaf1's .iplt entry
#------------------------------------------------------------------------------
#------ taf1's .iplt entry
#------------------------------------------------------------------------------
a068: 0afffc20 beq 90f0 <abf2@plt\+0x3c>
- a06c: e59f4000 ldr r4, \[pc\] ; a074 <_start\+0x4c>
- a070: e59f4000 ldr r4, \[pc\] ; a078 <_start\+0x50>
+ a06c: e59f4000 ldr r4, \[pc\] @ a074 <_start\+0x4c>
+ a070: e59f4000 ldr r4, \[pc\] @ a078 <_start\+0x50>
#------------------------------------------------------------------------------
#------ .got offset for taf1's .iplt entry
#------------------------------------------------------------------------------
#------ abf1's .iplt entry
#------------------------------------------------------------------------------
a084: 0afffc16 beq 90e4 <abf2@plt\+0x30>
- a088: e59f4000 ldr r4, \[pc\] ; a090 <_start\+0x68>
- a08c: e59f4000 ldr r4, \[pc\] ; a094 <_start\+0x6c>
+ a088: e59f4000 ldr r4, \[pc\] @ a090 <_start\+0x68>
+ a08c: e59f4000 ldr r4, \[pc\] @ a094 <_start\+0x6c>
#------------------------------------------------------------------------------
#------ .got offset for abf1's .iplt entry
#------------------------------------------------------------------------------
#------ tbf1's .iplt entry
#------------------------------------------------------------------------------
a0a0: 0afffc1a beq 9110 <abf2@plt\+0x5c>
- a0a4: e59f4000 ldr r4, \[pc\] ; a0ac <_start\+0x84>
- a0a8: e59f4000 ldr r4, \[pc\] ; a0b0 <_start\+0x88>
+ a0a4: e59f4000 ldr r4, \[pc\] @ a0ac <_start\+0x84>
+ a0a8: e59f4000 ldr r4, \[pc\] @ a0b0 <_start\+0x88>
#------------------------------------------------------------------------------
#------ .got offset for tbf1's .iplt entry
#------------------------------------------------------------------------------
#------ aaf2's .plt entry
#------------------------------------------------------------------------------
a0bc: 0afffbe6 beq 905c <aaf2@plt>
- a0c0: e59f4000 ldr r4, \[pc\] ; a0c8 <_start\+0xa0>
- a0c4: e59f4000 ldr r4, \[pc\] ; a0cc <_start\+0xa4>
+ a0c0: e59f4000 ldr r4, \[pc\] @ a0c8 <_start\+0xa0>
+ a0c4: e59f4000 ldr r4, \[pc\] @ a0cc <_start\+0xa4>
#------------------------------------------------------------------------------
#------ .got offset for aaf2
#------------------------------------------------------------------------------
#------ taf2's .plt entry
#------------------------------------------------------------------------------
a0d8: 0afffbdc beq 9050 <taf2@plt>
- a0dc: e59f4000 ldr r4, \[pc\] ; a0e4 <_start\+0xbc>
- a0e0: e59f4000 ldr r4, \[pc\] ; a0e8 <_start\+0xc0>
+ a0dc: e59f4000 ldr r4, \[pc\] @ a0e4 <_start\+0xbc>
+ a0e0: e59f4000 ldr r4, \[pc\] @ a0e8 <_start\+0xc0>
#------------------------------------------------------------------------------
#------ .got offset for taf2
#------------------------------------------------------------------------------
#------ abf2's .plt entry
#------------------------------------------------------------------------------
a0f4: 0afffbef beq 90b8 <abf2@plt\+0x4>
- a0f8: e59f4000 ldr r4, \[pc\] ; a100 <_start\+0xd8>
- a0fc: e59f4000 ldr r4, \[pc\] ; a104 <_start\+0xdc>
+ a0f8: e59f4000 ldr r4, \[pc\] @ a100 <_start\+0xd8>
+ a0fc: e59f4000 ldr r4, \[pc\] @ a104 <_start\+0xdc>
#------------------------------------------------------------------------------
#------ .got offset for abf2
#------------------------------------------------------------------------------
#------ tbf2's .plt entry
#------------------------------------------------------------------------------
a110: 0afffbcb beq 9044 <tbf2@plt\+0x4>
- a114: e59f4000 ldr r4, \[pc\] ; a11c <_start\+0xf4>
- a118: e59f4000 ldr r4, \[pc\] ; a120 <_start\+0xf8>
+ a114: e59f4000 ldr r4, \[pc\] @ a11c <_start\+0xf4>
+ a118: e59f4000 ldr r4, \[pc\] @ a120 <_start\+0xf8>
#------------------------------------------------------------------------------
#------ .got offset for tbf2
#------------------------------------------------------------------------------
a124: ebfffc0f bl 9168 <aaf3>
a128: eafffc0e b 9168 <aaf3>
a12c: 0afffc0d beq 9168 <aaf3>
- a130: e59f4000 ldr r4, \[pc\] ; a138 <_start\+0x110>
- a134: e59f4000 ldr r4, \[pc\] ; a13c <_start\+0x114>
+ a130: e59f4000 ldr r4, \[pc\] @ a138 <_start\+0x110>
+ a134: e59f4000 ldr r4, \[pc\] @ a13c <_start\+0x114>
#------------------------------------------------------------------------------
#------ .got offset for aaf3
#------------------------------------------------------------------------------
a140: ebfffc05 bl 915c <taf3>
a144: eafffc04 b 915c <taf3>
a148: 0afffc03 beq 915c <taf3>
- a14c: e59f4000 ldr r4, \[pc\] ; a154 <_start\+0x12c>
- a150: e59f4000 ldr r4, \[pc\] ; a158 <_start\+0x130>
+ a14c: e59f4000 ldr r4, \[pc\] @ a154 <_start\+0x12c>
+ a150: e59f4000 ldr r4, \[pc\] @ a158 <_start\+0x130>
#------------------------------------------------------------------------------
#------ .got offset for taf3
#------------------------------------------------------------------------------
a15c: ebfffbf3 bl 9130 <abf3>
a160: eafffbf2 b 9130 <abf3>
a164: 0afffbf1 beq 9130 <abf3>
- a168: e59f4000 ldr r4, \[pc\] ; a170 <_start\+0x148>
- a16c: e59f4000 ldr r4, \[pc\] ; a174 <_start\+0x14c>
+ a168: e59f4000 ldr r4, \[pc\] @ a170 <_start\+0x148>
+ a16c: e59f4000 ldr r4, \[pc\] @ a174 <_start\+0x14c>
#------------------------------------------------------------------------------
#------ .got offset for abf3
#------------------------------------------------------------------------------
a178: ebfffbf4 bl 9150 <tbf3>
a17c: eafffbf3 b 9150 <tbf3>
a180: 0afffbf2 beq 9150 <tbf3>
- a184: e59f4000 ldr r4, \[pc\] ; a18c <_start\+0x164>
- a188: e59f4000 ldr r4, \[pc\] ; a190 <_start\+0x168>
+ a184: e59f4000 ldr r4, \[pc\] @ a18c <_start\+0x164>
+ a188: e59f4000 ldr r4, \[pc\] @ a190 <_start\+0x168>
#------------------------------------------------------------------------------
#------ .got offset for tbf3
#------------------------------------------------------------------------------
#------ aaf4's .plt entry
#------------------------------------------------------------------------------
a19c: 0afffba0 beq 9024 <aaf4@plt>
- a1a0: e59f4000 ldr r4, \[pc\] ; a1a8 <_start\+0x180>
- a1a4: e59f4000 ldr r4, \[pc\] ; a1ac <_start\+0x184>
+ a1a0: e59f4000 ldr r4, \[pc\] @ a1a8 <_start\+0x180>
+ a1a4: e59f4000 ldr r4, \[pc\] @ a1ac <_start\+0x184>
#------------------------------------------------------------------------------
#------ .got offset for aaf4
#------------------------------------------------------------------------------
#------ taf4's .plt entry
#------------------------------------------------------------------------------
a1b8: 0afffbba beq 90a8 <taf4@plt>
- a1bc: e59f4000 ldr r4, \[pc\] ; a1c4 <_start\+0x19c>
- a1c0: e59f4000 ldr r4, \[pc\] ; a1c8 <_start\+0x1a0>
+ a1bc: e59f4000 ldr r4, \[pc\] @ a1c4 <_start\+0x19c>
+ a1c0: e59f4000 ldr r4, \[pc\] @ a1c8 <_start\+0x1a0>
#------------------------------------------------------------------------------
#------ .got offset for taf4
#------------------------------------------------------------------------------
#------ abf4's .plt entry
#------------------------------------------------------------------------------
a1d4: 0afffba4 beq 906c <abf4@plt\+0x4>
- a1d8: e59f4000 ldr r4, \[pc\] ; a1e0 <_start\+0x1b8>
- a1dc: e59f4000 ldr r4, \[pc\] ; a1e4 <_start\+0x1bc>
+ a1d8: e59f4000 ldr r4, \[pc\] @ a1e0 <_start\+0x1b8>
+ a1dc: e59f4000 ldr r4, \[pc\] @ a1e4 <_start\+0x1bc>
#------------------------------------------------------------------------------
#------ .got offset for abf4
#------------------------------------------------------------------------------
#------ tbf4's .plt entry
#------------------------------------------------------------------------------
a1f0: 0afffba1 beq 907c <tbf4@plt\+0x4>
- a1f4: e59f4000 ldr r4, \[pc\] ; a1fc <_start\+0x1d4>
- a1f8: e59f4000 ldr r4, \[pc\] ; a200 <_start\+0x1d8>
+ a1f4: e59f4000 ldr r4, \[pc\] @ a1fc <_start\+0x1d4>
+ a1f8: e59f4000 ldr r4, \[pc\] @ a200 <_start\+0x1d8>
#------------------------------------------------------------------------------
#------ .got offset for tbf4
#------------------------------------------------------------------------------
a204: f005 fefc bl 10000 <foo>
a208: f005 befa b\.w 10000 <foo>
a20c: f005 86f8 beq\.w 10000 <foo>
- a210: 4c00 ldr r4, \[pc, #0\] ; \(a214 <_thumb\+0x10>\)
- a212: 4c01 ldr r4, \[pc, #4\] ; \(a218 <_thumb\+0x14>\)
+ a210: 4c00 ldr r4, \[pc, #0\] @ \(a214 <_thumb\+0x10>\)
+ a212: 4c01 ldr r4, \[pc, #4\] @ \(a218 <_thumb\+0x14>\)
#------------------------------------------------------------------------------
#------ .got offset for foo
#------------------------------------------------------------------------------
#------ thumb entry to atf1's .iplt entry
#------------------------------------------------------------------------------
a224: f43e af54 beq\.w 90d0 <abf2@plt\+0x1c>
- a228: 4c00 ldr r4, \[pc, #0\] ; \(a22c <_thumb\+0x28>\)
- a22a: 4c01 ldr r4, \[pc, #4\] ; \(a230 <_thumb\+0x2c>\)
+ a228: 4c00 ldr r4, \[pc, #0\] @ \(a22c <_thumb\+0x28>\)
+ a22a: 4c01 ldr r4, \[pc, #4\] @ \(a230 <_thumb\+0x2c>\)
#------------------------------------------------------------------------------
#------ .got offset for atf1's .iplt entry
#------------------------------------------------------------------------------
#------ thumb entry to ttf1's .iplt entry
#------------------------------------------------------------------------------
a23c: f43e af5e beq\.w 90fc <abf2@plt\+0x48>
- a240: 4c00 ldr r4, \[pc, #0\] ; \(a244 <_thumb\+0x40>\)
- a242: 4c01 ldr r4, \[pc, #4\] ; \(a248 <_thumb\+0x44>\)
+ a240: 4c00 ldr r4, \[pc, #0\] @ \(a244 <_thumb\+0x40>\)
+ a242: 4c01 ldr r4, \[pc, #4\] @ \(a248 <_thumb\+0x44>\)
#------------------------------------------------------------------------------
#------ .got offset for ttf1's .iplt entry
#------------------------------------------------------------------------------
#------ thumb entry to abf1's .iplt entry
#------------------------------------------------------------------------------
a254: f43e af44 beq\.w 90e0 <abf2@plt\+0x2c>
- a258: 4c00 ldr r4, \[pc, #0\] ; \(a25c <_thumb\+0x58>\)
- a25a: 4c01 ldr r4, \[pc, #4\] ; \(a260 <_thumb\+0x5c>\)
+ a258: 4c00 ldr r4, \[pc, #0\] @ \(a25c <_thumb\+0x58>\)
+ a25a: 4c01 ldr r4, \[pc, #4\] @ \(a260 <_thumb\+0x5c>\)
#------------------------------------------------------------------------------
#------ .got offset for abf1's .iplt entry
#------------------------------------------------------------------------------
#------ thumb entry to tbf1's .iplt entry
#------------------------------------------------------------------------------
a26c: f43e af4e beq\.w 910c <abf2@plt\+0x58>
- a270: 4c00 ldr r4, \[pc, #0\] ; \(a274 <_thumb\+0x70>\)
- a272: 4c01 ldr r4, \[pc, #4\] ; \(a278 <_thumb\+0x74>\)
+ a270: 4c00 ldr r4, \[pc, #0\] @ \(a274 <_thumb\+0x70>\)
+ a272: 4c01 ldr r4, \[pc, #4\] @ \(a278 <_thumb\+0x74>\)
#------------------------------------------------------------------------------
#------ .got offset for tbf1's .iplt entry
#------------------------------------------------------------------------------
#------ thumb entry to atf2's .plt entry
#------------------------------------------------------------------------------
a284: f43e aec6 beq\.w 9014 <atf2@plt>
- a288: 4c00 ldr r4, \[pc, #0\] ; \(a28c <_thumb\+0x88>\)
- a28a: 4c01 ldr r4, \[pc, #4\] ; \(a290 <_thumb\+0x8c>\)
+ a288: 4c00 ldr r4, \[pc, #0\] @ \(a28c <_thumb\+0x88>\)
+ a28a: 4c01 ldr r4, \[pc, #4\] @ \(a290 <_thumb\+0x8c>\)
#------------------------------------------------------------------------------
#------ .got offset for atf2
#------------------------------------------------------------------------------
#------ thumb entry to ttf2's .plt entry
#------------------------------------------------------------------------------
a29c: f43e aec8 beq\.w 9030 <ttf2@plt>
- a2a0: 4c00 ldr r4, \[pc, #0\] ; \(a2a4 <_thumb\+0xa0>\)
- a2a2: 4c01 ldr r4, \[pc, #4\] ; \(a2a8 <_thumb\+0xa4>\)
+ a2a0: 4c00 ldr r4, \[pc, #0\] @ \(a2a4 <_thumb\+0xa0>\)
+ a2a2: 4c01 ldr r4, \[pc, #4\] @ \(a2a8 <_thumb\+0xa4>\)
#------------------------------------------------------------------------------
#------ .got offset for ttf2
#------------------------------------------------------------------------------
#------ thumb entry to abf2's .plt entry
#------------------------------------------------------------------------------
a2b4: f43e aefe beq\.w 90b4 <abf2@plt>
- a2b8: 4c00 ldr r4, \[pc, #0\] ; \(a2bc <_thumb\+0xb8>\)
- a2ba: 4c01 ldr r4, \[pc, #4\] ; \(a2c0 <_thumb\+0xbc>\)
+ a2b8: 4c00 ldr r4, \[pc, #0\] @ \(a2bc <_thumb\+0xb8>\)
+ a2ba: 4c01 ldr r4, \[pc, #4\] @ \(a2c0 <_thumb\+0xbc>\)
#------------------------------------------------------------------------------
#------ .got offset for abf2
#------------------------------------------------------------------------------
#------ thumb entry to tbf2's .plt entry
#------------------------------------------------------------------------------
a2cc: f43e aeb8 beq\.w 9040 <tbf2@plt>
- a2d0: 4c00 ldr r4, \[pc, #0\] ; \(a2d4 <_thumb\+0xd0>\)
- a2d2: 4c01 ldr r4, \[pc, #4\] ; \(a2d8 <_thumb\+0xd4>\)
+ a2d0: 4c00 ldr r4, \[pc, #0\] @ \(a2d4 <_thumb\+0xd0>\)
+ a2d2: 4c01 ldr r4, \[pc, #4\] @ \(a2d8 <_thumb\+0xd4>\)
#------------------------------------------------------------------------------
#------ .got offset for tbf2
#------------------------------------------------------------------------------
#------ thumb entry to atf3
#------------------------------------------------------------------------------
a2e4: f43e af1a beq\.w 911c <abf2@plt\+0x68>
- a2e8: 4c00 ldr r4, \[pc, #0\] ; \(a2ec <_thumb\+0xe8>\)
- a2ea: 4c01 ldr r4, \[pc, #4\] ; \(a2f0 <_thumb\+0xec>\)
+ a2e8: 4c00 ldr r4, \[pc, #0\] @ \(a2ec <_thumb\+0xe8>\)
+ a2ea: 4c01 ldr r4, \[pc, #4\] @ \(a2f0 <_thumb\+0xec>\)
#------------------------------------------------------------------------------
#------ .got offset for atf3
#------------------------------------------------------------------------------
#------ thumb entry to ttf3
#------------------------------------------------------------------------------
a2fc: f43e af1e beq\.w 913c <abf3\+0xc>
- a300: 4c00 ldr r4, \[pc, #0\] ; \(a304 <_thumb\+0x100>\)
- a302: 4c01 ldr r4, \[pc, #4\] ; \(a308 <_thumb\+0x104>\)
+ a300: 4c00 ldr r4, \[pc, #0\] @ \(a304 <_thumb\+0x100>\)
+ a302: 4c01 ldr r4, \[pc, #4\] @ \(a308 <_thumb\+0x104>\)
#------------------------------------------------------------------------------
#------ .got offset for ttf3
#------------------------------------------------------------------------------
#------ thumb entry to abf3
#------------------------------------------------------------------------------
a314: f43e af0a beq\.w 912c <atf3\+0xc>
- a318: 4c00 ldr r4, \[pc, #0\] ; \(a31c <_thumb\+0x118>\)
- a31a: 4c01 ldr r4, \[pc, #4\] ; \(a320 <_thumb\+0x11c>\)
+ a318: 4c00 ldr r4, \[pc, #0\] @ \(a31c <_thumb\+0x118>\)
+ a31a: 4c01 ldr r4, \[pc, #4\] @ \(a320 <_thumb\+0x11c>\)
#------------------------------------------------------------------------------
#------ .got offset for abf3
#------------------------------------------------------------------------------
#------ thumb entry to tbf3
#------------------------------------------------------------------------------
a32c: f43e af0e beq\.w 914c <ttf3\+0xc>
- a330: 4c00 ldr r4, \[pc, #0\] ; \(a334 <_thumb\+0x130>\)
- a332: 4c01 ldr r4, \[pc, #4\] ; \(a338 <_thumb\+0x134>\)
+ a330: 4c00 ldr r4, \[pc, #0\] @ \(a334 <_thumb\+0x130>\)
+ a332: 4c01 ldr r4, \[pc, #4\] @ \(a338 <_thumb\+0x134>\)
#------------------------------------------------------------------------------
#------ .got offset for tbf3
#------------------------------------------------------------------------------
#------ thumb entry to atf4's .plt entry
#------------------------------------------------------------------------------
a344: f43e aea8 beq\.w 9098 <atf4@plt>
- a348: 4c00 ldr r4, \[pc, #0\] ; \(a34c <_thumb\+0x148>\)
- a34a: 4c01 ldr r4, \[pc, #4\] ; \(a350 <_thumb\+0x14c>\)
+ a348: 4c00 ldr r4, \[pc, #0\] @ \(a34c <_thumb\+0x148>\)
+ a34a: 4c01 ldr r4, \[pc, #4\] @ \(a350 <_thumb\+0x14c>\)
#------------------------------------------------------------------------------
#------ .got offset for atf4
#------------------------------------------------------------------------------
#------ thumb entry to ttf4's .plt entry
#------------------------------------------------------------------------------
a35c: f43e ae94 beq\.w 9088 <ttf4@plt>
- a360: 4c00 ldr r4, \[pc, #0\] ; \(a364 <_thumb\+0x160>\)
- a362: 4c01 ldr r4, \[pc, #4\] ; \(a368 <_thumb\+0x164>\)
+ a360: 4c00 ldr r4, \[pc, #0\] @ \(a364 <_thumb\+0x160>\)
+ a362: 4c01 ldr r4, \[pc, #4\] @ \(a368 <_thumb\+0x164>\)
#------------------------------------------------------------------------------
#------ .got offset for ttf4
#------------------------------------------------------------------------------
#------ thumb entry to abf4's .plt entry
#------------------------------------------------------------------------------
a374: f43e ae78 beq\.w 9068 <abf4@plt>
- a378: 4c00 ldr r4, \[pc, #0\] ; \(a37c <_thumb\+0x178>\)
- a37a: 4c01 ldr r4, \[pc, #4\] ; \(a380 <_thumb\+0x17c>\)
+ a378: 4c00 ldr r4, \[pc, #0\] @ \(a37c <_thumb\+0x178>\)
+ a37a: 4c01 ldr r4, \[pc, #4\] @ \(a380 <_thumb\+0x17c>\)
#------------------------------------------------------------------------------
#------ .got offset for abf4
#------------------------------------------------------------------------------
#------ thumb entry to tbf4's .plt entry
#------------------------------------------------------------------------------
a38c: f43e ae74 beq\.w 9078 <tbf4@plt>
- a390: 4c00 ldr r4, \[pc, #0\] ; \(a394 <_thumb\+0x190>\)
- a392: 4c01 ldr r4, \[pc, #4\] ; \(a398 <_thumb\+0x194>\)
+ a390: 4c00 ldr r4, \[pc, #0\] @ \(a394 <_thumb\+0x190>\)
+ a392: 4c01 ldr r4, \[pc, #4\] @ \(a398 <_thumb\+0x194>\)
#------------------------------------------------------------------------------
#------ .got offset for tbf4
#------------------------------------------------------------------------------
a010: 46f7 mov pc, lr
0000a012 <_start>:
- a012: f8df 4004 ldr\.w r4, \[pc, #4\] ; a018 <_start\+0x6>
- a016: 4c01 ldr r4, \[pc, #4\] ; \(a01c <_start\+0xa>\)
+ a012: f8df 4004 ldr\.w r4, \[pc, #4\] @ a018 <_start\+0x6>
+ a016: 4c01 ldr r4, \[pc, #4\] @ \(a01c <_start\+0xa>\)
#------------------------------------------------------------------------------
#------ .got offset for foo
#------------------------------------------------------------------------------
#------ PC-relative offset of .got entry for foo
#------------------------------------------------------------------------------
a01c: 00006ff0 \.word 0x00006ff0
- a020: 4c00 ldr r4, \[pc, #0\] ; \(a024 <_start\+0x12>\)
- a022: 4c01 ldr r4, \[pc, #4\] ; \(a028 <_start\+0x16>\)
+ a020: 4c00 ldr r4, \[pc, #0\] @ \(a024 <_start\+0x12>\)
+ a022: 4c01 ldr r4, \[pc, #4\] @ \(a028 <_start\+0x16>\)
#------------------------------------------------------------------------------
#------ .got offset for f1
#------------------------------------------------------------------------------
#------ PC-relative offset of .got entry for f1
#------------------------------------------------------------------------------
a028: 00006fe8 \.word 0x00006fe8
- a02c: 4c00 ldr r4, \[pc, #0\] ; \(a030 <_start\+0x1e>\)
- a02e: 4c01 ldr r4, \[pc, #4\] ; \(a034 <_start\+0x22>\)
+ a02c: 4c00 ldr r4, \[pc, #0\] @ \(a030 <_start\+0x1e>\)
+ a02e: 4c01 ldr r4, \[pc, #4\] @ \(a034 <_start\+0x22>\)
#------------------------------------------------------------------------------
#------ .got offset for f2
#------------------------------------------------------------------------------
#------ PC-relative offset of .got entry for f2
#------------------------------------------------------------------------------
a034: 00006ff0 \.word 0x00006ff0
- a038: 4c00 ldr r4, \[pc, #0\] ; \(a03c <_start\+0x2a>\)
- a03a: 4c01 ldr r4, \[pc, #4\] ; \(a040 <_start\+0x2e>\)
+ a038: 4c00 ldr r4, \[pc, #0\] @ \(a03c <_start\+0x2a>\)
+ a03a: 4c01 ldr r4, \[pc, #4\] @ \(a040 <_start\+0x2e>\)
#------------------------------------------------------------------------------
#------ .got offset for f3
#------------------------------------------------------------------------------
#------ PC-relative offset of .got entry for f3
#------------------------------------------------------------------------------
a040: 00006fe0 \.word 0x00006fe0
- a044: 4c00 ldr r4, \[pc, #0\] ; \(a048 <_start\+0x36>\)
- a046: 4c01 ldr r4, \[pc, #4\] ; \(a04c <_start\+0x3a>\)
+ a044: 4c00 ldr r4, \[pc, #0\] @ \(a048 <_start\+0x36>\)
+ a046: 4c01 ldr r4, \[pc, #4\] @ \(a04c <_start\+0x3a>\)
#------------------------------------------------------------------------------
#------ .got offset for f1t
#------------------------------------------------------------------------------
#------ PC-relative offset of .got entry for f1t
#------------------------------------------------------------------------------
a04c: 00006fc8 \.word 0x00006fc8
- a050: 4c00 ldr r4, \[pc, #0\] ; \(a054 <_start\+0x42>\)
- a052: 4c01 ldr r4, \[pc, #4\] ; \(a058 <_start\+0x46>\)
+ a050: 4c00 ldr r4, \[pc, #0\] @ \(a054 <_start\+0x42>\)
+ a052: 4c01 ldr r4, \[pc, #4\] @ \(a058 <_start\+0x46>\)
#------------------------------------------------------------------------------
#------ .got offset for f2t
#------------------------------------------------------------------------------
#------ PC-relative offset of .got entry for f2t
#------------------------------------------------------------------------------
a058: 00006fc4 \.word 0x00006fc4
- a05c: 4c00 ldr r4, \[pc, #0\] ; \(a060 <_start\+0x4e>\)
- a05e: 4c01 ldr r4, \[pc, #4\] ; \(a064 <_start\+0x52>\)
+ a05c: 4c00 ldr r4, \[pc, #0\] @ \(a060 <_start\+0x4e>\)
+ a05e: 4c01 ldr r4, \[pc, #4\] @ \(a064 <_start\+0x52>\)
#------------------------------------------------------------------------------
#------ .got offset for f3t
#------------------------------------------------------------------------------
a010: 46f7 mov pc, lr
0000a012 <_start>:
- a012: f8df 4004 ldr\.w r4, \[pc, #4\] ; a018 <_start\+0x6>
- a016: 4c01 ldr r4, \[pc, #4\] ; \(a01c <_start\+0xa>\)
+ a012: f8df 4004 ldr\.w r4, \[pc, #4\] @ a018 <_start\+0x6>
+ a016: 4c01 ldr r4, \[pc, #4\] @ \(a01c <_start\+0xa>\)
#------------------------------------------------------------------------------
#------ .got offset for foo
#------------------------------------------------------------------------------
#------ PC-relative offset of .got entry for foo
#------------------------------------------------------------------------------
a01c: 00006ff0 \.word 0x00006ff0
- a020: 4c00 ldr r4, \[pc, #0\] ; \(a024 <_start\+0x12>\)
- a022: 4c01 ldr r4, \[pc, #4\] ; \(a028 <_start\+0x16>\)
+ a020: 4c00 ldr r4, \[pc, #0\] @ \(a024 <_start\+0x12>\)
+ a022: 4c01 ldr r4, \[pc, #4\] @ \(a028 <_start\+0x16>\)
#------------------------------------------------------------------------------
#------ .got offset for f1
#------------------------------------------------------------------------------
#------ PC-relative offset of .got entry for f1
#------------------------------------------------------------------------------
a028: 00006fe8 \.word 0x00006fe8
- a02c: 4c00 ldr r4, \[pc, #0\] ; \(a030 <_start\+0x1e>\)
- a02e: 4c01 ldr r4, \[pc, #4\] ; \(a034 <_start\+0x22>\)
+ a02c: 4c00 ldr r4, \[pc, #0\] @ \(a030 <_start\+0x1e>\)
+ a02e: 4c01 ldr r4, \[pc, #4\] @ \(a034 <_start\+0x22>\)
#------------------------------------------------------------------------------
#------ .got offset for f2
#------------------------------------------------------------------------------
#------ PC-relative offset of .got entry for f2
#------------------------------------------------------------------------------
a034: 00006ff0 \.word 0x00006ff0
- a038: 4c00 ldr r4, \[pc, #0\] ; \(a03c <_start\+0x2a>\)
- a03a: 4c01 ldr r4, \[pc, #4\] ; \(a040 <_start\+0x2e>\)
+ a038: 4c00 ldr r4, \[pc, #0\] @ \(a03c <_start\+0x2a>\)
+ a03a: 4c01 ldr r4, \[pc, #4\] @ \(a040 <_start\+0x2e>\)
#------------------------------------------------------------------------------
#------ .got offset for f3
#------------------------------------------------------------------------------
#------ PC-relative offset of .got entry for f3
#------------------------------------------------------------------------------
a040: 00006fe0 \.word 0x00006fe0
- a044: 4c00 ldr r4, \[pc, #0\] ; \(a048 <_start\+0x36>\)
- a046: 4c01 ldr r4, \[pc, #4\] ; \(a04c <_start\+0x3a>\)
+ a044: 4c00 ldr r4, \[pc, #0\] @ \(a048 <_start\+0x36>\)
+ a046: 4c01 ldr r4, \[pc, #4\] @ \(a04c <_start\+0x3a>\)
#------------------------------------------------------------------------------
#------ .got offset for f1t
#------------------------------------------------------------------------------
#------ PC-relative offset of .got entry for f1t
#------------------------------------------------------------------------------
a04c: 00006fc8 \.word 0x00006fc8
- a050: 4c00 ldr r4, \[pc, #0\] ; \(a054 <_start\+0x42>\)
- a052: 4c01 ldr r4, \[pc, #4\] ; \(a058 <_start\+0x46>\)
+ a050: 4c00 ldr r4, \[pc, #0\] @ \(a054 <_start\+0x42>\)
+ a052: 4c01 ldr r4, \[pc, #4\] @ \(a058 <_start\+0x46>\)
#------------------------------------------------------------------------------
#------ .got offset for f2t
#------------------------------------------------------------------------------
#------ PC-relative offset of .got entry for f2t
#------------------------------------------------------------------------------
a058: 00006fc4 \.word 0x00006fc4
- a05c: 4c00 ldr r4, \[pc, #0\] ; \(a060 <_start\+0x4e>\)
- a05e: 4c01 ldr r4, \[pc, #4\] ; \(a064 <_start\+0x52>\)
+ a05c: 4c00 ldr r4, \[pc, #0\] @ \(a060 <_start\+0x4e>\)
+ a05e: 4c01 ldr r4, \[pc, #4\] @ \(a064 <_start\+0x52>\)
#------------------------------------------------------------------------------
#------ .got offset for f3t
#------------------------------------------------------------------------------
a00a: 46f7 mov pc, lr
0000a00c <_start>:
- a00c: 4c00 ldr r4, \[pc, #0\] ; \(a010 <_start\+0x4>\)
- a00e: 4c01 ldr r4, \[pc, #4\] ; \(a014 <_start\+0x8>\)
+ a00c: 4c00 ldr r4, \[pc, #0\] @ \(a010 <_start\+0x4>\)
+ a00e: 4c01 ldr r4, \[pc, #4\] @ \(a014 <_start\+0x8>\)
#------------------------------------------------------------------------------
#------ .got offset for foo
#------------------------------------------------------------------------------
#------ PC-relative offset of .got entry for foo
#------------------------------------------------------------------------------
a014: 00006ff8 \.word 0x00006ff8
- a018: 4c00 ldr r4, \[pc, #0\] ; \(a01c <_start\+0x10>\)
- a01a: 4c01 ldr r4, \[pc, #4\] ; \(a020 <_start\+0x14>\)
+ a018: 4c00 ldr r4, \[pc, #0\] @ \(a01c <_start\+0x10>\)
+ a01a: 4c01 ldr r4, \[pc, #4\] @ \(a020 <_start\+0x14>\)
#------------------------------------------------------------------------------
#------ .got offset for f1
#------------------------------------------------------------------------------
#------ PC-relative offset of .got entry for f1
#------------------------------------------------------------------------------
a020: 00006ff0 \.word 0x00006ff0
- a024: 4c00 ldr r4, \[pc, #0\] ; \(a028 <_start\+0x1c>\)
- a026: 4c01 ldr r4, \[pc, #4\] ; \(a02c <_start\+0x20>\)
+ a024: 4c00 ldr r4, \[pc, #0\] @ \(a028 <_start\+0x1c>\)
+ a026: 4c01 ldr r4, \[pc, #4\] @ \(a02c <_start\+0x20>\)
#------------------------------------------------------------------------------
#------ .got offset for f2
#------------------------------------------------------------------------------
#------ PC-relative offset of .got entry for f2
#------------------------------------------------------------------------------
a02c: 00006ff8 \.word 0x00006ff8
- a030: 4c00 ldr r4, \[pc, #0\] ; \(a034 <_start\+0x28>\)
- a032: 4c01 ldr r4, \[pc, #4\] ; \(a038 <_start\+0x2c>\)
+ a030: 4c00 ldr r4, \[pc, #0\] @ \(a034 <_start\+0x28>\)
+ a032: 4c01 ldr r4, \[pc, #4\] @ \(a038 <_start\+0x2c>\)
#------------------------------------------------------------------------------
#------ .got offset for f3
#------------------------------------------------------------------------------
#------ PC-relative offset of .got entry for f3
#------------------------------------------------------------------------------
a038: 00006fe8 \.word 0x00006fe8
- a03c: 4c00 ldr r4, \[pc, #0\] ; \(a040 <_start\+0x34>\)
- a03e: 4c01 ldr r4, \[pc, #4\] ; \(a044 <_start\+0x38>\)
+ a03c: 4c00 ldr r4, \[pc, #0\] @ \(a040 <_start\+0x34>\)
+ a03e: 4c01 ldr r4, \[pc, #4\] @ \(a044 <_start\+0x38>\)
#------------------------------------------------------------------------------
#------ .got offset for f1t
#------------------------------------------------------------------------------
#------ PC-relative offset of .got entry for f1t
#------------------------------------------------------------------------------
a044: 00006fd0 \.word 0x00006fd0
- a048: 4c00 ldr r4, \[pc, #0\] ; \(a04c <_start\+0x40>\)
- a04a: 4c01 ldr r4, \[pc, #4\] ; \(a050 <_start\+0x44>\)
+ a048: 4c00 ldr r4, \[pc, #0\] @ \(a04c <_start\+0x40>\)
+ a04a: 4c01 ldr r4, \[pc, #4\] @ \(a050 <_start\+0x44>\)
#------------------------------------------------------------------------------
#------ .got offset for f2t
#------------------------------------------------------------------------------
#------ PC-relative offset of .got entry for f2t
#------------------------------------------------------------------------------
a050: 00006fcc \.word 0x00006fcc
- a054: 4c00 ldr r4, \[pc, #0\] ; \(a058 <_start\+0x4c>\)
- a056: 4c01 ldr r4, \[pc, #4\] ; \(a05c <_start\+0x50>\)
+ a054: 4c00 ldr r4, \[pc, #0\] @ \(a058 <_start\+0x4c>\)
+ a056: 4c01 ldr r4, \[pc, #4\] @ \(a05c <_start\+0x50>\)
#------------------------------------------------------------------------------
#------ .got offset for f3t
#------------------------------------------------------------------------------
Disassembly of section \.plt:
00009000 <.plt>:
- 9000: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
- 9004: e59fe004 ldr lr, \[pc, #4\] ; 9010 <.*>
+ 9000: e52de004 push {lr} @ \(str lr, \[sp, #-4\]!\)
+ 9004: e59fe004 ldr lr, \[pc, #4\] @ 9010 <.*>
9008: e08fe00e add lr, pc, lr
900c: e5bef008 ldr pc, \[lr, #8\]!
#------------------------------------------------------------------------------
#------------------------------------------------------------------------------
00009014 <f2t@plt>:
9014: e28fc600 add ip, pc, #0, 12
- 9018: e28cca07 add ip, ip, #28672 ; 0x7000
- 901c: e5bcfff0 ldr pc, \[ip, #4080\]! ; 0xff0
+ 9018: e28cca07 add ip, ip, #28672 @ 0x7000
+ 901c: e5bcfff0 ldr pc, \[ip, #4080\]! @ 0xff0
#------------------------------------------------------------------------------
#------ f2's .plt entry
#------------------------------------------------------------------------------
00009020 <f2@plt>:
9020: e28fc600 add ip, pc, #0, 12
- 9024: e28cca07 add ip, ip, #28672 ; 0x7000
- 9028: e5bcffe8 ldr pc, \[ip, #4072\]! ; 0xfe8
+ 9024: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9028: e5bcffe8 ldr pc, \[ip, #4072\]! @ 0xfe8
Disassembly of section \.iplt:
#------ f1's .iplt entry
#------------------------------------------------------------------------------
902c: e28fc600 add ip, pc, #0, 12
- 9030: e28cca07 add ip, ip, #28672 ; 0x7000
- 9034: e5bcffe0 ldr pc, \[ip, #4064\]! ; 0xfe0
+ 9030: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9034: e5bcffe0 ldr pc, \[ip, #4064\]! @ 0xfe0
#------------------------------------------------------------------------------
#------ f1t's .iplt entry
#------------------------------------------------------------------------------
9038: e28fc600 add ip, pc, #0, 12
- 903c: e28cca07 add ip, ip, #28672 ; 0x7000
- 9040: e5bcffd8 ldr pc, \[ip, #4056\]! ; 0xfd8
+ 903c: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9040: e5bcffd8 ldr pc, \[ip, #4056\]! @ 0xfd8
00009044 <f3>:
9044: e28fc600 add ip, pc, #0, 12
- 9048: e28cca07 add ip, ip, #28672 ; 0x7000
- 904c: e5bcffd0 ldr pc, \[ip, #4048\]! ; 0xfd0
+ 9048: e28cca07 add ip, ip, #28672 @ 0x7000
+ 904c: e5bcffd0 ldr pc, \[ip, #4048\]! @ 0xfd0
00009050 <f3t>:
9050: e28fc600 add ip, pc, #0, 12
- 9054: e28cca07 add ip, ip, #28672 ; 0x7000
- 9058: e5bcffc8 ldr pc, \[ip, #4040\]! ; 0xfc8
+ 9054: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9058: e5bcffc8 ldr pc, \[ip, #4040\]! @ 0xfc8
Disassembly of section \.text:
a00a: 46f7 mov pc, lr
0000a00c <_start>:
- a00c: f8df 4000 ldr\.w r4, \[pc\] ; a010 <_start\+0x4>
+ a00c: f8df 4000 ldr\.w r4, \[pc\] @ a010 <_start\+0x4>
#------------------------------------------------------------------------------
#------ PC-relative offset of foo
#------------------------------------------------------------------------------
a010: 00005ff0 \.word 0x00005ff0
- a014: f8df 4000 ldr\.w r4, \[pc\] ; a018 <_start\+0xc>
+ a014: f8df 4000 ldr\.w r4, \[pc\] @ a018 <_start\+0xc>
#------------------------------------------------------------------------------
#------ PC-relative offset of f1's .iplt entry
#------------------------------------------------------------------------------
a018: fffff014 \.word 0xfffff014
- a01c: f8df 4000 ldr\.w r4, \[pc\] ; a020 <_start\+0x14>
+ a01c: f8df 4000 ldr\.w r4, \[pc\] @ a020 <_start\+0x14>
#------------------------------------------------------------------------------
#------ PC-relative offset of f2's .plt entry
#------------------------------------------------------------------------------
a020: fffff000 \.word 0xfffff000
- a024: f8df 4000 ldr\.w r4, \[pc\] ; a028 <_start\+0x1c>
+ a024: f8df 4000 ldr\.w r4, \[pc\] @ a028 <_start\+0x1c>
#------------------------------------------------------------------------------
#------ PC-relative offset of f3
#------------------------------------------------------------------------------
a028: fffff01c \.word 0xfffff01c
- a02c: f8df 4000 ldr\.w r4, \[pc\] ; a030 <_start\+0x24>
+ a02c: f8df 4000 ldr\.w r4, \[pc\] @ a030 <_start\+0x24>
#------------------------------------------------------------------------------
#------ PC-relative offset of f1t's .iplt entry
#------------------------------------------------------------------------------
a030: fffff008 \.word 0xfffff008
- a034: f8df 4000 ldr\.w r4, \[pc\] ; a038 <_start\+0x2c>
+ a034: f8df 4000 ldr\.w r4, \[pc\] @ a038 <_start\+0x2c>
#------------------------------------------------------------------------------
#------ PC-relative offset of f2t's .plt entry
#------------------------------------------------------------------------------
a038: ffffefdc \.word 0xffffefdc
- a03c: f8df 4000 ldr\.w r4, \[pc\] ; a040 <_start\+0x34>
+ a03c: f8df 4000 ldr\.w r4, \[pc\] @ a040 <_start\+0x34>
#------------------------------------------------------------------------------
#------ PC-relative offset of f3t
#------------------------------------------------------------------------------
Disassembly of section \.plt:
00009000 <.plt>:
- 9000: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
- 9004: e59fe004 ldr lr, \[pc, #4\] ; 9010 <.*>
+ 9000: e52de004 push {lr} @ \(str lr, \[sp, #-4\]!\)
+ 9004: e59fe004 ldr lr, \[pc, #4\] @ 9010 <.*>
9008: e08fe00e add lr, pc, lr
900c: e5bef008 ldr pc, \[lr, #8\]!
#------------------------------------------------------------------------------
#------------------------------------------------------------------------------
00009014 <f2t@plt>:
9014: e28fc600 add ip, pc, #0, 12
- 9018: e28cca07 add ip, ip, #28672 ; 0x7000
- 901c: e5bcfff0 ldr pc, \[ip, #4080\]! ; 0xff0
+ 9018: e28cca07 add ip, ip, #28672 @ 0x7000
+ 901c: e5bcfff0 ldr pc, \[ip, #4080\]! @ 0xff0
#------------------------------------------------------------------------------
#------ f2's .plt entry
#------------------------------------------------------------------------------
00009020 <f2@plt>:
9020: e28fc600 add ip, pc, #0, 12
- 9024: e28cca07 add ip, ip, #28672 ; 0x7000
- 9028: e5bcffe8 ldr pc, \[ip, #4072\]! ; 0xfe8
+ 9024: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9028: e5bcffe8 ldr pc, \[ip, #4072\]! @ 0xfe8
Disassembly of section \.iplt:
#------ f1's .iplt entry
#------------------------------------------------------------------------------
902c: e28fc600 add ip, pc, #0, 12
- 9030: e28cca07 add ip, ip, #28672 ; 0x7000
- 9034: e5bcffe0 ldr pc, \[ip, #4064\]! ; 0xfe0
+ 9030: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9034: e5bcffe0 ldr pc, \[ip, #4064\]! @ 0xfe0
#------------------------------------------------------------------------------
#------ f1t's .iplt entry
#------------------------------------------------------------------------------
9038: e28fc600 add ip, pc, #0, 12
- 903c: e28cca07 add ip, ip, #28672 ; 0x7000
- 9040: e5bcffd8 ldr pc, \[ip, #4056\]! ; 0xfd8
+ 903c: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9040: e5bcffd8 ldr pc, \[ip, #4056\]! @ 0xfd8
00009044 <f3>:
9044: e28fc600 add ip, pc, #0, 12
- 9048: e28cca07 add ip, ip, #28672 ; 0x7000
- 904c: e5bcffd0 ldr pc, \[ip, #4048\]! ; 0xfd0
+ 9048: e28cca07 add ip, ip, #28672 @ 0x7000
+ 904c: e5bcffd0 ldr pc, \[ip, #4048\]! @ 0xfd0
00009050 <f3t>:
9050: e28fc600 add ip, pc, #0, 12
- 9054: e28cca07 add ip, ip, #28672 ; 0x7000
- 9058: e5bcffc8 ldr pc, \[ip, #4040\]! ; 0xfc8
+ 9054: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9058: e5bcffc8 ldr pc, \[ip, #4040\]! @ 0xfc8
Disassembly of section \.text:
a00a: 46f7 mov pc, lr
0000a00c <_start>:
- a00c: f8df 4000 ldr\.w r4, \[pc\] ; a010 <_start\+0x4>
+ a00c: f8df 4000 ldr\.w r4, \[pc\] @ a010 <_start\+0x4>
#------------------------------------------------------------------------------
#------ foo
#------------------------------------------------------------------------------
a010: 00010000 \.word 0x00010000
- a014: f8df 4000 ldr\.w r4, \[pc\] ; a018 <_start\+0xc>
+ a014: f8df 4000 ldr\.w r4, \[pc\] @ a018 <_start\+0xc>
#------------------------------------------------------------------------------
#------ f1's .iplt entry
#------------------------------------------------------------------------------
a018: 0000902c \.word 0x0000902c
- a01c: f8df 4000 ldr\.w r4, \[pc\] ; a020 <_start\+0x14>
+ a01c: f8df 4000 ldr\.w r4, \[pc\] @ a020 <_start\+0x14>
#------------------------------------------------------------------------------
#------ f2's .plt entry
#------------------------------------------------------------------------------
a020: 00009020 \.word 0x00009020
- a024: f8df 4000 ldr\.w r4, \[pc\] ; a028 <_start\+0x1c>
+ a024: f8df 4000 ldr\.w r4, \[pc\] @ a028 <_start\+0x1c>
#------------------------------------------------------------------------------
#------ f3
#------------------------------------------------------------------------------
a028: 00009044 \.word 0x00009044
- a02c: f8df 4000 ldr\.w r4, \[pc\] ; a030 <_start\+0x24>
+ a02c: f8df 4000 ldr\.w r4, \[pc\] @ a030 <_start\+0x24>
#------------------------------------------------------------------------------
#------ f1t's .iplt entry
#------------------------------------------------------------------------------
a030: 00009038 \.word 0x00009038
- a034: f8df 4000 ldr\.w r4, \[pc\] ; a038 <_start\+0x2c>
+ a034: f8df 4000 ldr\.w r4, \[pc\] @ a038 <_start\+0x2c>
#------------------------------------------------------------------------------
#------ f2t's .plt entry
#------------------------------------------------------------------------------
a038: 00009014 \.word 0x00009014
- a03c: f8df 4000 ldr\.w r4, \[pc\] ; a040 <_start\+0x34>
+ a03c: f8df 4000 ldr\.w r4, \[pc\] @ a040 <_start\+0x34>
#------------------------------------------------------------------------------
#------ f3t
#------------------------------------------------------------------------------
#------ f1's .iplt entry
#------------------------------------------------------------------------------
9000: e28fc600 add ip, pc, #0, 12
- 9004: e28cca08 add ip, ip, #8, 20 ; 0x8000
+ 9004: e28cca08 add ip, ip, #8, 20 @ 0x8000
9008: e5bcf004 ldr pc, \[ip, #4\]!
#------------------------------------------------------------------------------
#------ f1t's .iplt entry
#------------------------------------------------------------------------------
900c: e28fc600 add ip, pc, #0, 12
- 9010: e28cca07 add ip, ip, #28672 ; 0x7000
- 9014: e5bcfffc ldr pc, \[ip, #4092\]! ; 0xffc
+ 9010: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9014: e5bcfffc ldr pc, \[ip, #4092\]! @ 0xffc
00009018 <f2t>:
9018: e28fc600 add ip, pc, #0, 12
- 901c: e28cca07 add ip, ip, #28672 ; 0x7000
- 9020: e5bcfff4 ldr pc, \[ip, #4084\]! ; 0xff4
+ 901c: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9020: e5bcfff4 ldr pc, \[ip, #4084\]! @ 0xff4
00009024 <f3>:
9024: e28fc600 add ip, pc, #0, 12
- 9028: e28cca07 add ip, ip, #28672 ; 0x7000
- 902c: e5bcffec ldr pc, \[ip, #4076\]! ; 0xfec
+ 9028: e28cca07 add ip, ip, #28672 @ 0x7000
+ 902c: e5bcffec ldr pc, \[ip, #4076\]! @ 0xfec
00009030 <f2>:
9030: e28fc600 add ip, pc, #0, 12
- 9034: e28cca07 add ip, ip, #28672 ; 0x7000
- 9038: e5bcffe4 ldr pc, \[ip, #4068\]! ; 0xfe4
+ 9034: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9038: e5bcffe4 ldr pc, \[ip, #4068\]! @ 0xfe4
0000903c <f3t>:
903c: e28fc600 add ip, pc, #0, 12
- 9040: e28cca07 add ip, ip, #28672 ; 0x7000
- 9044: e5bcffdc ldr pc, \[ip, #4060\]! ; 0xfdc
+ 9040: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9044: e5bcffdc ldr pc, \[ip, #4060\]! @ 0xfdc
Disassembly of section \.text:
a010: 46f7 mov pc, lr
0000a012 <_start>:
- a012: 4c00 ldr r4, \[pc, #0\] ; \(a014 <_start\+0x2>\)
+ a012: 4c00 ldr r4, \[pc, #0\] @ \(a014 <_start\+0x2>\)
#------------------------------------------------------------------------------
#------ foo
#------------------------------------------------------------------------------
a014: 00010000 \.word 0x00010000
- a018: f8df 4000 ldr\.w r4, \[pc\] ; a01c <_start\+0xa>
+ a018: f8df 4000 ldr\.w r4, \[pc\] @ a01c <_start\+0xa>
#------------------------------------------------------------------------------
#------ f1's .iplt entry
#------------------------------------------------------------------------------
a01c: 00009000 \.word 0x00009000
- a020: f8df 4000 ldr\.w r4, \[pc\] ; a024 <_start\+0x12>
+ a020: f8df 4000 ldr\.w r4, \[pc\] @ a024 <_start\+0x12>
#------------------------------------------------------------------------------
#------ f2
#------------------------------------------------------------------------------
a024: 00009030 \.word 0x00009030
- a028: f8df 4000 ldr\.w r4, \[pc\] ; a02c <_start\+0x1a>
+ a028: f8df 4000 ldr\.w r4, \[pc\] @ a02c <_start\+0x1a>
#------------------------------------------------------------------------------
#------ f3
#------------------------------------------------------------------------------
a02c: 00009024 \.word 0x00009024
- a030: f8df 4000 ldr\.w r4, \[pc\] ; a034 <_start\+0x22>
+ a030: f8df 4000 ldr\.w r4, \[pc\] @ a034 <_start\+0x22>
#------------------------------------------------------------------------------
#------ f1t's .iplt entry
#------------------------------------------------------------------------------
a034: 0000900c \.word 0x0000900c
- a038: f8df 4000 ldr\.w r4, \[pc\] ; a03c <_start\+0x2a>
+ a038: f8df 4000 ldr\.w r4, \[pc\] @ a03c <_start\+0x2a>
#------------------------------------------------------------------------------
#------ f2t
#------------------------------------------------------------------------------
a03c: 00009018 \.word 0x00009018
- a040: f8df 4000 ldr\.w r4, \[pc\] ; a044 <_start\+0x32>
+ a040: f8df 4000 ldr\.w r4, \[pc\] @ a044 <_start\+0x32>
#------------------------------------------------------------------------------
#------ f3t
#------------------------------------------------------------------------------
#------ appfunc1's .iplt entry
#------------------------------------------------------------------------------
9000: e28fc600 add ip, pc, #0, 12
- 9004: e28cca08 add ip, ip, #8, 20 ; 0x8000
+ 9004: e28cca08 add ip, ip, #8, 20 @ 0x8000
9008: e5bcf004 ldr pc, \[ip, #4\]!
Disassembly of section \.text:
#------ f1's .iplt entry
#------------------------------------------------------------------------------
9000: e28fc600 add ip, pc, #0, 12
- 9004: e28cca08 add ip, ip, #8, 20 ; 0x8000
+ 9004: e28cca08 add ip, ip, #8, 20 @ 0x8000
9008: e5bcf004 ldr pc, \[ip, #4\]!
#------------------------------------------------------------------------------
#------ f2's .iplt entry
#------------------------------------------------------------------------------
900c: e28fc600 add ip, pc, #0, 12
- 9010: e28cca07 add ip, ip, #28672 ; 0x7000
- 9014: e5bcfffc ldr pc, \[ip, #4092\]! ; 0xffc
+ 9010: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9014: e5bcfffc ldr pc, \[ip, #4092\]! @ 0xffc
#------------------------------------------------------------------------------
#------ thumb entry to f3's .iplt entry
#------------------------------------------------------------------------------
#------ f3's .iplt entry
#------------------------------------------------------------------------------
901c: e28fc600 add ip, pc, #0, 12
- 9020: e28cca07 add ip, ip, #28672 ; 0x7000
- 9024: e5bcfff0 ldr pc, \[ip, #4080\]! ; 0xff0
+ 9020: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9024: e5bcfff0 ldr pc, \[ip, #4080\]! @ 0xff0
#------------------------------------------------------------------------------
#------ thumb entry to f4's .iplt entry
#------------------------------------------------------------------------------
#------ f4's .iplt entry
#------------------------------------------------------------------------------
902c: e28fc600 add ip, pc, #0, 12
- 9030: e28cca07 add ip, ip, #28672 ; 0x7000
- 9034: e5bcffe4 ldr pc, \[ip, #4068\]! ; 0xfe4
+ 9030: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9034: e5bcffe4 ldr pc, \[ip, #4068\]! @ 0xfe4
#------------------------------------------------------------------------------
#------ thumb entry to f7
#------------------------------------------------------------------------------
0000903c <f7>:
903c: e28fc600 add ip, pc, #0, 12
- 9040: e28cca07 add ip, ip, #28672 ; 0x7000
- 9044: e5bcffd8 ldr pc, \[ip, #4056\]! ; 0xfd8
+ 9040: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9044: e5bcffd8 ldr pc, \[ip, #4056\]! @ 0xfd8
00009048 <f5>:
9048: e28fc600 add ip, pc, #0, 12
- 904c: e28cca07 add ip, ip, #28672 ; 0x7000
- 9050: e5bcffd0 ldr pc, \[ip, #4048\]! ; 0xfd0
+ 904c: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9050: e5bcffd0 ldr pc, \[ip, #4048\]! @ 0xfd0
#------------------------------------------------------------------------------
#------ thumb entry to f8
#------------------------------------------------------------------------------
00009058 <f8>:
9058: e28fc600 add ip, pc, #0, 12
- 905c: e28cca07 add ip, ip, #28672 ; 0x7000
- 9060: e5bcffc4 ldr pc, \[ip, #4036\]! ; 0xfc4
+ 905c: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9060: e5bcffc4 ldr pc, \[ip, #4036\]! @ 0xfc4
00009064 <f6>:
9064: e28fc600 add ip, pc, #0, 12
- 9068: e28cca07 add ip, ip, #28672 ; 0x7000
- 906c: e5bcffbc ldr pc, \[ip, #4028\]! ; 0xfbc
+ 9068: e28cca07 add ip, ip, #28672 @ 0x7000
+ 906c: e5bcffbc ldr pc, \[ip, #4028\]! @ 0xfbc
Disassembly of section \.text:
a020: eb0017f6 bl 10000 <foo>
a024: ea0017f5 b 10000 <foo>
a028: 0a0017f4 beq 10000 <foo>
- a02c: e59f4014 ldr r4, \[pc, #20\] ; a048 <_start\+0x28>
- a030: e59f4014 ldr r4, \[pc, #20\] ; a04c <_start\+0x2c>
- a034: e59f4014 ldr r4, \[pc, #20\] ; a050 <_start\+0x30>
- a038: e59f4014 ldr r4, \[pc, #20\] ; a054 <_start\+0x34>
- a03c: e59f5014 ldr r5, \[pc, #20\] ; a058 <_start\+0x38>
+ a02c: e59f4014 ldr r4, \[pc, #20\] @ a048 <_start\+0x28>
+ a030: e59f4014 ldr r4, \[pc, #20\] @ a04c <_start\+0x2c>
+ a034: e59f4014 ldr r4, \[pc, #20\] @ a050 <_start\+0x30>
+ a038: e59f4014 ldr r4, \[pc, #20\] @ a054 <_start\+0x34>
+ a03c: e59f5014 ldr r5, \[pc, #20\] @ a058 <_start\+0x38>
a040: e3004000 movw r4, #0
a044: e3404001 movt r4, #1
#------------------------------------------------------------------------------
#------ f1's .iplt entry
#------------------------------------------------------------------------------
a064: 0afffbe5 beq 9000 <f7-0x3c>
- a068: e59f4014 ldr r4, \[pc, #20\] ; a084 <_start\+0x64>
- a06c: e59f4014 ldr r4, \[pc, #20\] ; a088 <_start\+0x68>
- a070: e59f4014 ldr r4, \[pc, #20\] ; a08c <_start\+0x6c>
- a074: e59f4014 ldr r4, \[pc, #20\] ; a090 <_start\+0x70>
- a078: e59f5014 ldr r5, \[pc, #20\] ; a094 <_start\+0x74>
- a07c: e3094000 movw r4, #36864 ; 0x9000
+ a068: e59f4014 ldr r4, \[pc, #20\] @ a084 <_start\+0x64>
+ a06c: e59f4014 ldr r4, \[pc, #20\] @ a088 <_start\+0x68>
+ a070: e59f4014 ldr r4, \[pc, #20\] @ a08c <_start\+0x6c>
+ a074: e59f4014 ldr r4, \[pc, #20\] @ a090 <_start\+0x70>
+ a078: e59f5014 ldr r5, \[pc, #20\] @ a094 <_start\+0x74>
+ a07c: e3094000 movw r4, #36864 @ 0x9000
a080: e3404000 movt r4, #0
#------------------------------------------------------------------------------
#------ f1's .iplt entry
#------ f2's .iplt entry
#------------------------------------------------------------------------------
a0a0: 0afffbd9 beq 900c <f7-0x30>
- a0a4: e59f4014 ldr r4, \[pc, #20\] ; a0c0 <_start\+0xa0>
- a0a8: e59f4014 ldr r4, \[pc, #20\] ; a0c4 <_start\+0xa4>
- a0ac: e59f4014 ldr r4, \[pc, #20\] ; a0c8 <_start\+0xa8>
- a0b0: e59f4014 ldr r4, \[pc, #20\] ; a0cc <_start\+0xac>
- a0b4: e59f5014 ldr r5, \[pc, #20\] ; a0d0 <_start\+0xb0>
- a0b8: e309400c movw r4, #36876 ; 0x900c
+ a0a4: e59f4014 ldr r4, \[pc, #20\] @ a0c0 <_start\+0xa0>
+ a0a8: e59f4014 ldr r4, \[pc, #20\] @ a0c4 <_start\+0xa4>
+ a0ac: e59f4014 ldr r4, \[pc, #20\] @ a0c8 <_start\+0xa8>
+ a0b0: e59f4014 ldr r4, \[pc, #20\] @ a0cc <_start\+0xac>
+ a0b4: e59f5014 ldr r5, \[pc, #20\] @ a0d0 <_start\+0xb0>
+ a0b8: e309400c movw r4, #36876 @ 0x900c
a0bc: e3404000 movt r4, #0
#------------------------------------------------------------------------------
#------ f2's .iplt entry
a0d4: ebfffbdb bl 9048 <f5>
a0d8: eafffbda b 9048 <f5>
a0dc: 0afffbd9 beq 9048 <f5>
- a0e0: e59f4014 ldr r4, \[pc, #20\] ; a0fc <_start\+0xdc>
- a0e4: e59f4014 ldr r4, \[pc, #20\] ; a100 <_start\+0xe0>
- a0e8: e59f4014 ldr r4, \[pc, #20\] ; a104 <_start\+0xe4>
- a0ec: e59f4014 ldr r4, \[pc, #20\] ; a108 <_start\+0xe8>
- a0f0: e59f5014 ldr r5, \[pc, #20\] ; a10c <_start\+0xec>
- a0f4: e3094048 movw r4, #36936 ; 0x9048
+ a0e0: e59f4014 ldr r4, \[pc, #20\] @ a0fc <_start\+0xdc>
+ a0e4: e59f4014 ldr r4, \[pc, #20\] @ a100 <_start\+0xe0>
+ a0e8: e59f4014 ldr r4, \[pc, #20\] @ a104 <_start\+0xe4>
+ a0ec: e59f4014 ldr r4, \[pc, #20\] @ a108 <_start\+0xe8>
+ a0f0: e59f5014 ldr r5, \[pc, #20\] @ a10c <_start\+0xec>
+ a0f4: e3094048 movw r4, #36936 @ 0x9048
a0f8: e3404000 movt r4, #0
#------------------------------------------------------------------------------
#------ f5
a110: ebfffbd3 bl 9064 <f6>
a114: eafffbd2 b 9064 <f6>
a118: 0afffbd1 beq 9064 <f6>
- a11c: e59f4014 ldr r4, \[pc, #20\] ; a138 <_start\+0x118>
- a120: e59f4014 ldr r4, \[pc, #20\] ; a13c <_start\+0x11c>
- a124: e59f4014 ldr r4, \[pc, #20\] ; a140 <_start\+0x120>
- a128: e59f4014 ldr r4, \[pc, #20\] ; a144 <_start\+0x124>
- a12c: e59f5014 ldr r5, \[pc, #20\] ; a148 <_start\+0x128>
- a130: e3094064 movw r4, #36964 ; 0x9064
+ a11c: e59f4014 ldr r4, \[pc, #20\] @ a138 <_start\+0x118>
+ a120: e59f4014 ldr r4, \[pc, #20\] @ a13c <_start\+0x11c>
+ a124: e59f4014 ldr r4, \[pc, #20\] @ a140 <_start\+0x120>
+ a128: e59f4014 ldr r4, \[pc, #20\] @ a144 <_start\+0x124>
+ a12c: e59f5014 ldr r5, \[pc, #20\] @ a148 <_start\+0x128>
+ a130: e3094064 movw r4, #36964 @ 0x9064
a134: e3404000 movt r4, #0
#------------------------------------------------------------------------------
#------ f6
a14c: f005 ff58 bl 10000 <foo>
a150: f005 bf56 b\.w 10000 <foo>
a154: f005 8754 beq\.w 10000 <foo>
- a158: 4c04 ldr r4, \[pc, #16\] ; \(a16c <_thumb\+0x20>\)
- a15a: f8df 4014 ldr\.w r4, \[pc, #20\] ; a170 <_thumb\+0x24>
- a15e: 4c05 ldr r4, \[pc, #20\] ; \(a174 <_thumb\+0x28>\)
- a160: 4c05 ldr r4, \[pc, #20\] ; \(a178 <_thumb\+0x2c>\)
- a162: 4d06 ldr r5, \[pc, #24\] ; \(a17c <_thumb\+0x30>\)
+ a158: 4c04 ldr r4, \[pc, #16\] @ \(a16c <_thumb\+0x20>\)
+ a15a: f8df 4014 ldr\.w r4, \[pc, #20\] @ a170 <_thumb\+0x24>
+ a15e: 4c05 ldr r4, \[pc, #20\] @ \(a174 <_thumb\+0x28>\)
+ a160: 4c05 ldr r4, \[pc, #20\] @ \(a178 <_thumb\+0x2c>\)
+ a162: 4d06 ldr r5, \[pc, #24\] @ \(a17c <_thumb\+0x30>\)
a164: f240 0400 movw r4, #0
a168: f2c0 0401 movt r4, #1
#------------------------------------------------------------------------------
#------ thumb entry to f3's .iplt entry
#------------------------------------------------------------------------------
a188: f43e af46 beq\.w 9018 <f7-0x24>
- a18c: 4c04 ldr r4, \[pc, #16\] ; \(a1a0 <_thumb\+0x54>\)
- a18e: f8df 4014 ldr\.w r4, \[pc, #20\] ; a1a4 <_thumb\+0x58>
- a192: 4c05 ldr r4, \[pc, #20\] ; \(a1a8 <_thumb\+0x5c>\)
- a194: 4c05 ldr r4, \[pc, #20\] ; \(a1ac <_thumb\+0x60>\)
- a196: 4d06 ldr r5, \[pc, #24\] ; \(a1b0 <_thumb\+0x64>\)
- a198: f249 041c movw r4, #36892 ; 0x901c
+ a18c: 4c04 ldr r4, \[pc, #16\] @ \(a1a0 <_thumb\+0x54>\)
+ a18e: f8df 4014 ldr\.w r4, \[pc, #20\] @ a1a4 <_thumb\+0x58>
+ a192: 4c05 ldr r4, \[pc, #20\] @ \(a1a8 <_thumb\+0x5c>\)
+ a194: 4c05 ldr r4, \[pc, #20\] @ \(a1ac <_thumb\+0x60>\)
+ a196: 4d06 ldr r5, \[pc, #24\] @ \(a1b0 <_thumb\+0x64>\)
+ a198: f249 041c movw r4, #36892 @ 0x901c
a19c: f2c0 0400 movt r4, #0
#------------------------------------------------------------------------------
#------ f3's .iplt entry
#------ thumb entry to f4's .iplt entry
#------------------------------------------------------------------------------
a1bc: f43e af34 beq\.w 9028 <f7-0x14>
- a1c0: 4c04 ldr r4, \[pc, #16\] ; \(a1d4 <_thumb\+0x88>\)
- a1c2: f8df 4014 ldr\.w r4, \[pc, #20\] ; a1d8 <_thumb\+0x8c>
- a1c6: 4c05 ldr r4, \[pc, #20\] ; \(a1dc <_thumb\+0x90>\)
- a1c8: 4c05 ldr r4, \[pc, #20\] ; \(a1e0 <_thumb\+0x94>\)
- a1ca: 4d06 ldr r5, \[pc, #24\] ; \(a1e4 <_thumb\+0x98>\)
- a1cc: f249 042c movw r4, #36908 ; 0x902c
+ a1c0: 4c04 ldr r4, \[pc, #16\] @ \(a1d4 <_thumb\+0x88>\)
+ a1c2: f8df 4014 ldr\.w r4, \[pc, #20\] @ a1d8 <_thumb\+0x8c>
+ a1c6: 4c05 ldr r4, \[pc, #20\] @ \(a1dc <_thumb\+0x90>\)
+ a1c8: 4c05 ldr r4, \[pc, #20\] @ \(a1e0 <_thumb\+0x94>\)
+ a1ca: 4d06 ldr r5, \[pc, #24\] @ \(a1e4 <_thumb\+0x98>\)
+ a1cc: f249 042c movw r4, #36908 @ 0x902c
a1d0: f2c0 0400 movt r4, #0
#------------------------------------------------------------------------------
#------ f4's .iplt entry
#------ thumb entry to f7
#------------------------------------------------------------------------------
a1f0: f43e af22 beq\.w 9038 <f7-0x4>
- a1f4: 4c04 ldr r4, \[pc, #16\] ; \(a208 <_thumb\+0xbc>\)
- a1f6: f8df 4014 ldr\.w r4, \[pc, #20\] ; a20c <_thumb\+0xc0>
- a1fa: 4c05 ldr r4, \[pc, #20\] ; \(a210 <_thumb\+0xc4>\)
- a1fc: 4c05 ldr r4, \[pc, #20\] ; \(a214 <_thumb\+0xc8>\)
- a1fe: 4d06 ldr r5, \[pc, #24\] ; \(a218 <_thumb\+0xcc>\)
- a200: f249 043c movw r4, #36924 ; 0x903c
+ a1f4: 4c04 ldr r4, \[pc, #16\] @ \(a208 <_thumb\+0xbc>\)
+ a1f6: f8df 4014 ldr\.w r4, \[pc, #20\] @ a20c <_thumb\+0xc0>
+ a1fa: 4c05 ldr r4, \[pc, #20\] @ \(a210 <_thumb\+0xc4>\)
+ a1fc: 4c05 ldr r4, \[pc, #20\] @ \(a214 <_thumb\+0xc8>\)
+ a1fe: 4d06 ldr r5, \[pc, #24\] @ \(a218 <_thumb\+0xcc>\)
+ a200: f249 043c movw r4, #36924 @ 0x903c
a204: f2c0 0400 movt r4, #0
#------------------------------------------------------------------------------
#------ f7
#------ thumb entry to f8
#------------------------------------------------------------------------------
a224: f43e af16 beq\.w 9054 <f5\+0xc>
- a228: 4c04 ldr r4, \[pc, #16\] ; \(a23c <_thumb\+0xf0>\)
- a22a: f8df 4014 ldr\.w r4, \[pc, #20\] ; a240 <_thumb\+0xf4>
- a22e: 4c05 ldr r4, \[pc, #20\] ; \(a244 <_thumb\+0xf8>\)
- a230: 4c05 ldr r4, \[pc, #20\] ; \(a248 <_thumb\+0xfc>\)
- a232: 4d06 ldr r5, \[pc, #24\] ; \(a24c <_thumb\+0x100>\)
- a234: f249 0458 movw r4, #36952 ; 0x9058
+ a228: 4c04 ldr r4, \[pc, #16\] @ \(a23c <_thumb\+0xf0>\)
+ a22a: f8df 4014 ldr\.w r4, \[pc, #20\] @ a240 <_thumb\+0xf4>
+ a22e: 4c05 ldr r4, \[pc, #20\] @ \(a244 <_thumb\+0xf8>\)
+ a230: 4c05 ldr r4, \[pc, #20\] @ \(a248 <_thumb\+0xfc>\)
+ a232: 4d06 ldr r5, \[pc, #24\] @ \(a24c <_thumb\+0x100>\)
+ a234: f249 0458 movw r4, #36952 @ 0x9058
a238: f2c0 0400 movt r4, #0
#------------------------------------------------------------------------------
#------ f8
Disassembly of section \.plt:
00009000 <.plt>:
- 9000: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
- 9004: e59fe004 ldr lr, \[pc, #4\] ; 9010 <.*>
+ 9000: e52de004 push {lr} @ \(str lr, \[sp, #-4\]!\)
+ 9004: e59fe004 ldr lr, \[pc, #4\] @ 9010 <.*>
9008: e08fe00e add lr, pc, lr
900c: e5bef008 ldr pc, \[lr, #8\]!
#------------------------------------------------------------------------------
#------------------------------------------------------------------------------
00009014 <f2@plt>:
9014: e28fc600 add ip, pc, #0, 12
- 9018: e28cca07 add ip, ip, #28672 ; 0x7000
- 901c: e5bcfff0 ldr pc, \[ip, #4080\]! ; 0xff0
+ 9018: e28cca07 add ip, ip, #28672 @ 0x7000
+ 901c: e5bcfff0 ldr pc, \[ip, #4080\]! @ 0xff0
Disassembly of section \.iplt:
#------ f1's .iplt entry
#------------------------------------------------------------------------------
9020: e28fc600 add ip, pc, #0, 12
- 9024: e28cca07 add ip, ip, #28672 ; 0x7000
- 9028: e5bcffe8 ldr pc, \[ip, #4072\]! ; 0xfe8
+ 9024: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9028: e5bcffe8 ldr pc, \[ip, #4072\]! @ 0xfe8
#------------------------------------------------------------------------------
#------ f3's .iplt entry
#------------------------------------------------------------------------------
902c: e28fc600 add ip, pc, #0, 12
- 9030: e28cca07 add ip, ip, #28672 ; 0x7000
- 9034: e5bcffe0 ldr pc, \[ip, #4064\]! ; 0xfe0
+ 9030: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9034: e5bcffe0 ldr pc, \[ip, #4064\]! @ 0xfe0
#------------------------------------------------------------------------------
#------ f4's .iplt entry
#------------------------------------------------------------------------------
9038: e28fc600 add ip, pc, #0, 12
- 903c: e28cca07 add ip, ip, #28672 ; 0x7000
- 9040: e5bcffd8 ldr pc, \[ip, #4056\]! ; 0xfd8
+ 903c: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9040: e5bcffd8 ldr pc, \[ip, #4056\]! @ 0xfd8
Disassembly of section \.text:
0000a010 <arm>:
a010: eb0017fa bl 10000 <foo>
- a014: e59f4000 ldr r4, \[pc\]
; a01c <arm\+0xc>
- a018: e59f4000 ldr r4, \[pc\]
; a020 <arm\+0x10>
+ a014: e59f4000 ldr r4, \[pc\]
@ a01c <arm\+0xc>
+ a018: e59f4000 ldr r4, \[pc\]
@ a020 <arm\+0x10>
#------------------------------------------------------------------------------
#------ .got offset for foo
#------------------------------------------------------------------------------
#------ f1's .iplt entry
#------------------------------------------------------------------------------
a024: ebfffbfd bl 9020 <f2@plt\+0xc>
- a028: e59f4000 ldr r4, \[pc\]
; a030 <arm\+0x20>
- a02c: e59f4000 ldr r4, \[pc\]
; a034 <arm\+0x24>
+ a028: e59f4000 ldr r4, \[pc\]
@ a030 <arm\+0x20>
+ a02c: e59f4000 ldr r4, \[pc\]
@ a034 <arm\+0x24>
#------------------------------------------------------------------------------
#------ GP-relative offset of f1's .igot.plt entry
#------------------------------------------------------------------------------
#------ f2's .plt entry
#------------------------------------------------------------------------------
a038: ebfffbf5 bl 9014 <f2@plt>
- a03c: e59f4000 ldr r4, \[pc\]
; a044 <arm\+0x34>
- a040: e59f4000 ldr r4, \[pc\]
; a048 <arm\+0x38>
+ a03c: e59f4000 ldr r4, \[pc\]
@ a044 <arm\+0x34>
+ a040: e59f4000 ldr r4, \[pc\]
@ a048 <arm\+0x38>
#------------------------------------------------------------------------------
#------ .got offset for f2
#------------------------------------------------------------------------------
#------ f3's .iplt entry
#------------------------------------------------------------------------------
a04c: ebfffbf6 bl 902c <f2@plt\+0x18>
- a050: e59f4000 ldr r4, \[pc\]
; a058 <arm\+0x48>
- a054: e59f4000 ldr r4, \[pc\]
; a05c <arm\+0x4c>
+ a050: e59f4000 ldr r4, \[pc\]
@ a058 <arm\+0x48>
+ a054: e59f4000 ldr r4, \[pc\]
@ a05c <arm\+0x4c>
#------------------------------------------------------------------------------
#------ GP-relative offset of f3's .igot.plt entry
#------------------------------------------------------------------------------
#------ f4's .iplt entry
#------------------------------------------------------------------------------
a060: ebfffbf4 bl 9038 <f2@plt\+0x24>
- a064: e59f4000 ldr r4, \[pc\]
; a06c <arm\+0x5c>
- a068: e59f4000 ldr r4, \[pc\]
; a070 <arm\+0x60>
+ a064: e59f4000 ldr r4, \[pc\]
@ a06c <arm\+0x5c>
+ a068: e59f4000 ldr r4, \[pc\]
@ a070 <arm\+0x60>
#------------------------------------------------------------------------------
#------ .got offset for f4
#------------------------------------------------------------------------------
Disassembly of section \.plt:
00009000 <.plt>:
- 9000: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
- 9004: e59fe004 ldr lr, \[pc, #4\] ; 9010 <.*>
+ 9000: e52de004 push {lr} @ \(str lr, \[sp, #-4\]!\)
+ 9004: e59fe004 ldr lr, \[pc, #4\] @ 9010 <.*>
9008: e08fe00e add lr, pc, lr
900c: e5bef008 ldr pc, \[lr, #8\]!
#------------------------------------------------------------------------------
#------ atf2's .plt entry
#------------------------------------------------------------------------------
9018: e28fc600 add ip, pc, #0, 12
- 901c: e28cca07 add ip, ip, #28672 ; 0x7000
- 9020: e5bcffec ldr pc, \[ip, #4076\]! ; 0xfec
+ 901c: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9020: e5bcffec ldr pc, \[ip, #4076\]! @ 0xfec
#------------------------------------------------------------------------------
#------ thumb entry to ttf2's .plt entry
#------------------------------------------------------------------------------
#------ ttf2's .plt entry
#------------------------------------------------------------------------------
9028: e28fc600 add ip, pc, #0, 12
- 902c: e28cca07 add ip, ip, #28672 ; 0x7000
- 9030: e5bcffe0 ldr pc, \[ip, #4064\]! ; 0xfe0
+ 902c: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9030: e5bcffe0 ldr pc, \[ip, #4064\]! @ 0xfe0
#------------------------------------------------------------------------------
#------ thumb entry to tbf2's .plt entry
#------------------------------------------------------------------------------
#------ tbf2's .plt entry
#------------------------------------------------------------------------------
9038: e28fc600 add ip, pc, #0, 12
- 903c: e28cca07 add ip, ip, #28672 ; 0x7000
- 9040: e5bcffd4 ldr pc, \[ip, #4052\]! ; 0xfd4
+ 903c: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9040: e5bcffd4 ldr pc, \[ip, #4052\]! @ 0xfd4
#------------------------------------------------------------------------------
#------ taf2's .plt entry
#------------------------------------------------------------------------------
00009044 <taf2@plt>:
9044: e28fc600 add ip, pc, #0, 12
- 9048: e28cca07 add ip, ip, #28672 ; 0x7000
- 904c: e5bcffcc ldr pc, \[ip, #4044\]! ; 0xfcc
+ 9048: e28cca07 add ip, ip, #28672 @ 0x7000
+ 904c: e5bcffcc ldr pc, \[ip, #4044\]! @ 0xfcc
#------------------------------------------------------------------------------
#------ aaf2's .plt entry
#------------------------------------------------------------------------------
00009050 <aaf2@plt>:
9050: e28fc600 add ip, pc, #0, 12
- 9054: e28cca07 add ip, ip, #28672 ; 0x7000
- 9058: e5bcffc4 ldr pc, \[ip, #4036\]! ; 0xfc4
+ 9054: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9058: e5bcffc4 ldr pc, \[ip, #4036\]! @ 0xfc4
#------------------------------------------------------------------------------
#------ thumb entry to abf2's .plt entry
#------------------------------------------------------------------------------
#------ abf2's .plt entry
#------------------------------------------------------------------------------
9060: e28fc600 add ip, pc, #0, 12
- 9064: e28cca07 add ip, ip, #28672 ; 0x7000
- 9068: e5bcffb8 ldr pc, \[ip, #4024\]! ; 0xfb8
+ 9064: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9068: e5bcffb8 ldr pc, \[ip, #4024\]! @ 0xfb8
Disassembly of section \.iplt:
#------ aaf1's .iplt entry
#------------------------------------------------------------------------------
906c: e28fc600 add ip, pc, #0, 12
- 9070: e28cca07 add ip, ip, #28672 ; 0x7000
- 9074: e5bcffb0 ldr pc, \[ip, #4016\]! ; 0xfb0
+ 9070: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9074: e5bcffb0 ldr pc, \[ip, #4016\]! @ 0xfb0
#------------------------------------------------------------------------------
#------ thumb entry to atf1's .iplt entry
#------------------------------------------------------------------------------
#------ atf1's .iplt entry
#------------------------------------------------------------------------------
907c: e28fc600 add ip, pc, #0, 12
- 9080: e28cca07 add ip, ip, #28672 ; 0x7000
- 9084: e5bcffa4 ldr pc, \[ip, #4004\]! ; 0xfa4
+ 9080: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9084: e5bcffa4 ldr pc, \[ip, #4004\]! @ 0xfa4
#------------------------------------------------------------------------------
#------ thumb entry to abf1's .iplt entry
#------------------------------------------------------------------------------
#------ abf1's .iplt entry
#------------------------------------------------------------------------------
908c: e28fc600 add ip, pc, #0, 12
- 9090: e28cca07 add ip, ip, #28672 ; 0x7000
- 9094: e5bcff98 ldr pc, \[ip, #3992\]! ; 0xf98
+ 9090: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9094: e5bcff98 ldr pc, \[ip, #3992\]! @ 0xf98
#------------------------------------------------------------------------------
#------ taf1's .iplt entry
#------------------------------------------------------------------------------
9098: e28fc600 add ip, pc, #0, 12
- 909c: e28cca07 add ip, ip, #28672 ; 0x7000
- 90a0: e5bcff90 ldr pc, \[ip, #3984\]! ; 0xf90
+ 909c: e28cca07 add ip, ip, #28672 @ 0x7000
+ 90a0: e5bcff90 ldr pc, \[ip, #3984\]! @ 0xf90
#------------------------------------------------------------------------------
#------ thumb entry to ttf1's .iplt entry
#------------------------------------------------------------------------------
#------ ttf1's .iplt entry
#------------------------------------------------------------------------------
90a8: e28fc600 add ip, pc, #0, 12
- 90ac: e28cca07 add ip, ip, #28672 ; 0x7000
- 90b0: e5bcff84 ldr pc, \[ip, #3972\]! ; 0xf84
+ 90ac: e28cca07 add ip, ip, #28672 @ 0x7000
+ 90b0: e5bcff84 ldr pc, \[ip, #3972\]! @ 0xf84
#------------------------------------------------------------------------------
#------ thumb entry to tbf1's .iplt entry
#------------------------------------------------------------------------------
#------ tbf1's .iplt entry
#------------------------------------------------------------------------------
90b8: e28fc600 add ip, pc, #0, 12
- 90bc: e28cca07 add ip, ip, #28672 ; 0x7000
- 90c0: e5bcff78 ldr pc, \[ip, #3960\]! ; 0xf78
+ 90bc: e28cca07 add ip, ip, #28672 @ 0x7000
+ 90c0: e5bcff78 ldr pc, \[ip, #3960\]! @ 0xf78
#------------------------------------------------------------------------------
#------ aaf4's .iplt entry
#------------------------------------------------------------------------------
90c4: e28fc600 add ip, pc, #0, 12
- 90c8: e28cca07 add ip, ip, #28672 ; 0x7000
- 90cc: e5bcff70 ldr pc, \[ip, #3952\]! ; 0xf70
+ 90c8: e28cca07 add ip, ip, #28672 @ 0x7000
+ 90cc: e5bcff70 ldr pc, \[ip, #3952\]! @ 0xf70
#------------------------------------------------------------------------------
#------ thumb entry to atf3's .iplt entry
#------------------------------------------------------------------------------
#------ atf3's .iplt entry
#------------------------------------------------------------------------------
90d4: e28fc600 add ip, pc, #0, 12
- 90d8: e28cca07 add ip, ip, #28672 ; 0x7000
- 90dc: e5bcff64 ldr pc, \[ip, #3940\]! ; 0xf64
+ 90d8: e28cca07 add ip, ip, #28672 @ 0x7000
+ 90dc: e5bcff64 ldr pc, \[ip, #3940\]! @ 0xf64
#------------------------------------------------------------------------------
#------ thumb entry to abf3's .iplt entry
#------------------------------------------------------------------------------
#------ abf3's .iplt entry
#------------------------------------------------------------------------------
90e4: e28fc600 add ip, pc, #0, 12
- 90e8: e28cca07 add ip, ip, #28672 ; 0x7000
- 90ec: e5bcff58 ldr pc, \[ip, #3928\]! ; 0xf58
+ 90e8: e28cca07 add ip, ip, #28672 @ 0x7000
+ 90ec: e5bcff58 ldr pc, \[ip, #3928\]! @ 0xf58
#------------------------------------------------------------------------------
#------ thumb entry to ttf3's .iplt entry
#------------------------------------------------------------------------------
#------ ttf3's .iplt entry
#------------------------------------------------------------------------------
90f4: e28fc600 add ip, pc, #0, 12
- 90f8: e28cca07 add ip, ip, #28672 ; 0x7000
- 90fc: e5bcff4c ldr pc, \[ip, #3916\]! ; 0xf4c
+ 90f8: e28cca07 add ip, ip, #28672 @ 0x7000
+ 90fc: e5bcff4c ldr pc, \[ip, #3916\]! @ 0xf4c
#------------------------------------------------------------------------------
#------ thumb entry to tbf3's .iplt entry
#------------------------------------------------------------------------------
#------ tbf3's .iplt entry
#------------------------------------------------------------------------------
9104: e28fc600 add ip, pc, #0, 12
- 9108: e28cca07 add ip, ip, #28672 ; 0x7000
- 910c: e5bcff40 ldr pc, \[ip, #3904\]! ; 0xf40
+ 9108: e28cca07 add ip, ip, #28672 @ 0x7000
+ 910c: e5bcff40 ldr pc, \[ip, #3904\]! @ 0xf40
#------------------------------------------------------------------------------
#------ taf3's .iplt entry
#------------------------------------------------------------------------------
9110: e28fc600 add ip, pc, #0, 12
- 9114: e28cca07 add ip, ip, #28672 ; 0x7000
- 9118: e5bcff38 ldr pc, \[ip, #3896\]! ; 0xf38
+ 9114: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9118: e5bcff38 ldr pc, \[ip, #3896\]! @ 0xf38
#------------------------------------------------------------------------------
#------ thumb entry to abf4's .iplt entry
#------------------------------------------------------------------------------
#------ abf4's .iplt entry
#------------------------------------------------------------------------------
9120: e28fc600 add ip, pc, #0, 12
- 9124: e28cca07 add ip, ip, #28672 ; 0x7000
- 9128: e5bcff2c ldr pc, \[ip, #3884\]! ; 0xf2c
+ 9124: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9128: e5bcff2c ldr pc, \[ip, #3884\]! @ 0xf2c
#------------------------------------------------------------------------------
#------ thumb entry to tbf4's .iplt entry
#------------------------------------------------------------------------------
#------ tbf4's .iplt entry
#------------------------------------------------------------------------------
9130: e28fc600 add ip, pc, #0, 12
- 9134: e28cca07 add ip, ip, #28672 ; 0x7000
- 9138: e5bcff20 ldr pc, \[ip, #3872\]! ; 0xf20
+ 9134: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9138: e5bcff20 ldr pc, \[ip, #3872\]! @ 0xf20
#------------------------------------------------------------------------------
#------ thumb entry to ttf4's .iplt entry
#------------------------------------------------------------------------------
#------ ttf4's .iplt entry
#------------------------------------------------------------------------------
9140: e28fc600 add ip, pc, #0, 12
- 9144: e28cca07 add ip, ip, #28672 ; 0x7000
- 9148: e5bcff14 ldr pc, \[ip, #3860\]! ; 0xf14
+ 9144: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9148: e5bcff14 ldr pc, \[ip, #3860\]! @ 0xf14
#------------------------------------------------------------------------------
#------ aaf3's .iplt entry
#------------------------------------------------------------------------------
914c: e28fc600 add ip, pc, #0, 12
- 9150: e28cca07 add ip, ip, #28672 ; 0x7000
- 9154: e5bcff0c ldr pc, \[ip, #3852\]! ; 0xf0c
+ 9150: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9154: e5bcff0c ldr pc, \[ip, #3852\]! @ 0xf0c
#------------------------------------------------------------------------------
#------ thumb entry to atf4's .iplt entry
#------------------------------------------------------------------------------
#------ atf4's .iplt entry
#------------------------------------------------------------------------------
915c: e28fc600 add ip, pc, #0, 12
- 9160: e28cca07 add ip, ip, #28672 ; 0x7000
- 9164: e5bcff00 ldr pc, \[ip, #3840\]! ; 0xf00
+ 9160: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9164: e5bcff00 ldr pc, \[ip, #3840\]! @ 0xf00
#------------------------------------------------------------------------------
#------ taf4's .iplt entry
#------------------------------------------------------------------------------
9168: e28fc600 add ip, pc, #0, 12
- 916c: e28cca07 add ip, ip, #28672 ; 0x7000
- 9170: e5bcfef8 ldr pc, \[ip, #3832\]! ; 0xef8
+ 916c: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9170: e5bcfef8 ldr pc, \[ip, #3832\]! @ 0xef8
Disassembly of section \.text:
a050: eb0017ea bl 10000 <foo>
a054: ea0017e9 b 10000 <foo>
a058: 0a0017e8 beq 10000 <foo>
- a05c: e59f4000 ldr r4, \[pc\]
; a064 <arm\+0x14>
- a060: e59f4000 ldr r4, \[pc\]
; a068 <arm\+0x18>
+ a05c: e59f4000 ldr r4, \[pc\]
@ a064 <arm\+0x14>
+ a060: e59f4000 ldr r4, \[pc\]
@ a068 <arm\+0x18>
#------------------------------------------------------------------------------
#------ .got offset for foo
#------------------------------------------------------------------------------
#------ aaf1's .iplt entry
#------------------------------------------------------------------------------
a074: 0afffbfc beq 906c <abf2@plt\+0x10>
- a078: e59f4000 ldr r4, \[pc\]
; a080 <arm\+0x30>
- a07c: e59f4000 ldr r4, \[pc\]
; a084 <arm\+0x34>
+ a078: e59f4000 ldr r4, \[pc\]
@ a080 <arm\+0x30>
+ a07c: e59f4000 ldr r4, \[pc\]
@ a084 <arm\+0x34>
#------------------------------------------------------------------------------
#------ GP-relative offset of aaf1's .igot.plt entry
#------------------------------------------------------------------------------
#------ taf1's .iplt entry
#------------------------------------------------------------------------------
a090: 0afffc00 beq 9098 <abf2@plt\+0x3c>
- a094: e59f4000 ldr r4, \[pc\]
; a09c <arm\+0x4c>
- a098: e59f4000 ldr r4, \[pc\]
; a0a0 <arm\+0x50>
+ a094: e59f4000 ldr r4, \[pc\]
@ a09c <arm\+0x4c>
+ a098: e59f4000 ldr r4, \[pc\]
@ a0a0 <arm\+0x50>
#------------------------------------------------------------------------------
#------ GP-relative offset of taf1's .igot.plt entry
#------------------------------------------------------------------------------
#------ abf1's .iplt entry
#------------------------------------------------------------------------------
a0ac: 0afffbf6 beq 908c <abf2@plt\+0x30>
- a0b0: e59f4000 ldr r4, \[pc\]
; a0b8 <arm\+0x68>
- a0b4: e59f4000 ldr r4, \[pc\]
; a0bc <arm\+0x6c>
+ a0b0: e59f4000 ldr r4, \[pc\]
@ a0b8 <arm\+0x68>
+ a0b4: e59f4000 ldr r4, \[pc\]
@ a0bc <arm\+0x6c>
#------------------------------------------------------------------------------
#------ GP-relative offset of abf1's .igot.plt entry
#------------------------------------------------------------------------------
#------ tbf1's .iplt entry
#------------------------------------------------------------------------------
a0c8: 0afffbfa beq 90b8 <abf2@plt\+0x5c>
- a0cc: e59f4000 ldr r4, \[pc\]
; a0d4 <arm\+0x84>
- a0d0: e59f4000 ldr r4, \[pc\]
; a0d8 <arm\+0x88>
+ a0cc: e59f4000 ldr r4, \[pc\]
@ a0d4 <arm\+0x84>
+ a0d0: e59f4000 ldr r4, \[pc\]
@ a0d8 <arm\+0x88>
#------------------------------------------------------------------------------
#------ GP-relative offset of tbf1's .igot.plt entry
#------------------------------------------------------------------------------
#------ aaf2's .plt entry
#------------------------------------------------------------------------------
a0e4: 0afffbd9 beq 9050 <aaf2@plt>
- a0e8: e59f4000 ldr r4, \[pc\]
; a0f0 <arm\+0xa0>
- a0ec: e59f4000 ldr r4, \[pc\]
; a0f4 <arm\+0xa4>
+ a0e8: e59f4000 ldr r4, \[pc\]
@ a0f0 <arm\+0xa0>
+ a0ec: e59f4000 ldr r4, \[pc\]
@ a0f4 <arm\+0xa4>
#------------------------------------------------------------------------------
#------ .got offset for aaf2
#------------------------------------------------------------------------------
#------ taf2's .plt entry
#------------------------------------------------------------------------------
a100: 0afffbcf beq 9044 <taf2@plt>
- a104: e59f4000 ldr r4, \[pc\]
; a10c <arm\+0xbc>
- a108: e59f4000 ldr r4, \[pc\]
; a110 <arm\+0xc0>
+ a104: e59f4000 ldr r4, \[pc\]
@ a10c <arm\+0xbc>
+ a108: e59f4000 ldr r4, \[pc\]
@ a110 <arm\+0xc0>
#------------------------------------------------------------------------------
#------ .got offset for taf2
#------------------------------------------------------------------------------
#------ abf2's .plt entry
#------------------------------------------------------------------------------
a11c: 0afffbcf beq 9060 <abf2@plt\+0x4>
- a120: e59f4000 ldr r4, \[pc\]
; a128 <arm\+0xd8>
- a124: e59f4000 ldr r4, \[pc\]
; a12c <arm\+0xdc>
+ a120: e59f4000 ldr r4, \[pc\]
@ a128 <arm\+0xd8>
+ a124: e59f4000 ldr r4, \[pc\]
@ a12c <arm\+0xdc>
#------------------------------------------------------------------------------
#------ .got offset for abf2
#------------------------------------------------------------------------------
#------ tbf2's .plt entry
#------------------------------------------------------------------------------
a138: 0afffbbe beq 9038 <tbf2@plt\+0x4>
- a13c: e59f4000 ldr r4, \[pc\]
; a144 <arm\+0xf4>
- a140: e59f4000 ldr r4, \[pc\]
; a148 <arm\+0xf8>
+ a13c: e59f4000 ldr r4, \[pc\]
@ a144 <arm\+0xf4>
+ a140: e59f4000 ldr r4, \[pc\]
@ a148 <arm\+0xf8>
#------------------------------------------------------------------------------
#------ .got offset for tbf2
#------------------------------------------------------------------------------
#------ aaf3's .iplt entry
#------------------------------------------------------------------------------
a154: 0afffbfc beq 914c <abf2@plt\+0xf0>
- a158: e59f4000 ldr r4, \[pc\]
; a160 <arm\+0x110>
- a15c: e59f4000 ldr r4, \[pc\]
; a164 <arm\+0x114>
+ a158: e59f4000 ldr r4, \[pc\]
@ a160 <arm\+0x110>
+ a15c: e59f4000 ldr r4, \[pc\]
@ a164 <arm\+0x114>
#------------------------------------------------------------------------------
#------ GP-relative offset of aaf3's .igot.plt entry
#------------------------------------------------------------------------------
#------ taf3's .iplt entry
#------------------------------------------------------------------------------
a170: 0afffbe6 beq 9110 <abf2@plt\+0xb4>
- a174: e59f4000 ldr r4, \[pc\]
; a17c <arm\+0x12c>
- a178: e59f4000 ldr r4, \[pc\]
; a180 <arm\+0x130>
+ a174: e59f4000 ldr r4, \[pc\]
@ a17c <arm\+0x12c>
+ a178: e59f4000 ldr r4, \[pc\]
@ a180 <arm\+0x130>
#------------------------------------------------------------------------------
#------ GP-relative offset of taf3's .igot.plt entry
#------------------------------------------------------------------------------
#------ abf3's .iplt entry
#------------------------------------------------------------------------------
a18c: 0afffbd4 beq 90e4 <abf2@plt\+0x88>
- a190: e59f4000 ldr r4, \[pc\]
; a198 <arm\+0x148>
- a194: e59f4000 ldr r4, \[pc\]
; a19c <arm\+0x14c>
+ a190: e59f4000 ldr r4, \[pc\]
@ a198 <arm\+0x148>
+ a194: e59f4000 ldr r4, \[pc\]
@ a19c <arm\+0x14c>
#------------------------------------------------------------------------------
#------ GP-relative offset of abf3's .igot.plt entry
#------------------------------------------------------------------------------
#------ tbf3's .iplt entry
#------------------------------------------------------------------------------
a1a8: 0afffbd5 beq 9104 <abf2@plt\+0xa8>
- a1ac: e59f4000 ldr r4, \[pc\]
; a1b4 <arm\+0x164>
- a1b0: e59f4000 ldr r4, \[pc\]
; a1b8 <arm\+0x168>
+ a1ac: e59f4000 ldr r4, \[pc\]
@ a1b4 <arm\+0x164>
+ a1b0: e59f4000 ldr r4, \[pc\]
@ a1b8 <arm\+0x168>
#------------------------------------------------------------------------------
#------ GP-relative offset of tbf3's .igot.plt entry
#------------------------------------------------------------------------------
#------ aaf4's .iplt entry
#------------------------------------------------------------------------------
a1c4: 0afffbbe beq 90c4 <abf2@plt\+0x68>
- a1c8: e59f4000 ldr r4, \[pc\]
; a1d0 <arm\+0x180>
- a1cc: e59f4000 ldr r4, \[pc\]
; a1d4 <arm\+0x184>
+ a1c8: e59f4000 ldr r4, \[pc\]
@ a1d0 <arm\+0x180>
+ a1cc: e59f4000 ldr r4, \[pc\]
@ a1d4 <arm\+0x184>
#------------------------------------------------------------------------------
#------ .got offset for aaf4
#------------------------------------------------------------------------------
#------ taf4's .iplt entry
#------------------------------------------------------------------------------
a1e0: 0afffbe0 beq 9168 <abf2@plt\+0x10c>
- a1e4: e59f4000 ldr r4, \[pc\]
; a1ec <arm\+0x19c>
- a1e8: e59f4000 ldr r4, \[pc\]
; a1f0 <arm\+0x1a0>
+ a1e4: e59f4000 ldr r4, \[pc\]
@ a1ec <arm\+0x19c>
+ a1e8: e59f4000 ldr r4, \[pc\]
@ a1f0 <arm\+0x1a0>
#------------------------------------------------------------------------------
#------ .got offset for taf4
#------------------------------------------------------------------------------
#------ abf4's .iplt entry
#------------------------------------------------------------------------------
a1fc: 0afffbc7 beq 9120 <abf2@plt\+0xc4>
- a200: e59f4000 ldr r4, \[pc\]
; a208 <arm\+0x1b8>
- a204: e59f4000 ldr r4, \[pc\]
; a20c <arm\+0x1bc>
+ a200: e59f4000 ldr r4, \[pc\]
@ a208 <arm\+0x1b8>
+ a204: e59f4000 ldr r4, \[pc\]
@ a20c <arm\+0x1bc>
#------------------------------------------------------------------------------
#------ .got offset for abf4
#------------------------------------------------------------------------------
#------ tbf4's .iplt entry
#------------------------------------------------------------------------------
a218: 0afffbc4 beq 9130 <abf2@plt\+0xd4>
- a21c: e59f4000 ldr r4, \[pc\]
; a224 <arm\+0x1d4>
- a220: e59f4000 ldr r4, \[pc\]
; a228 <arm\+0x1d8>
+ a21c: e59f4000 ldr r4, \[pc\]
@ a224 <arm\+0x1d4>
+ a220: e59f4000 ldr r4, \[pc\]
@ a228 <arm\+0x1d8>
#------------------------------------------------------------------------------
#------ .got offset for tbf4
#------------------------------------------------------------------------------
a22c: f005 fee8 bl 10000 <foo>
a230: f005 bee6 b\.w 10000 <foo>
a234: f005 86e4 beq\.w 10000 <foo>
- a238: 4c00 ldr r4, \[pc, #0\] ; \(a23c <_thumb\+0x10>\)
- a23a: 4c01 ldr r4, \[pc, #4\] ; \(a240 <_thumb\+0x14>\)
+ a238: 4c00 ldr r4, \[pc, #0\] @ \(a23c <_thumb\+0x10>\)
+ a23a: 4c01 ldr r4, \[pc, #4\] @ \(a240 <_thumb\+0x14>\)
#------------------------------------------------------------------------------
#------ .got offset for foo
#------------------------------------------------------------------------------
#------ thumb entry to atf1's .iplt entry
#------------------------------------------------------------------------------
a24c: f43e af14 beq\.w 9078 <abf2@plt\+0x1c>
- a250: 4c00 ldr r4, \[pc, #0\] ; \(a254 <_thumb\+0x28>\)
- a252: 4c01 ldr r4, \[pc, #4\] ; \(a258 <_thumb\+0x2c>\)
+ a250: 4c00 ldr r4, \[pc, #0\] @ \(a254 <_thumb\+0x28>\)
+ a252: 4c01 ldr r4, \[pc, #4\] @ \(a258 <_thumb\+0x2c>\)
#------------------------------------------------------------------------------
#------ GP-relative offset of atf1's .igot.plt entry
#------------------------------------------------------------------------------
#------ thumb entry to ttf1's .iplt entry
#------------------------------------------------------------------------------
a264: f43e af1e beq\.w 90a4 <abf2@plt\+0x48>
- a268: 4c00 ldr r4, \[pc, #0\] ; \(a26c <_thumb\+0x40>\)
- a26a: 4c01 ldr r4, \[pc, #4\] ; \(a270 <_thumb\+0x44>\)
+ a268: 4c00 ldr r4, \[pc, #0\] @ \(a26c <_thumb\+0x40>\)
+ a26a: 4c01 ldr r4, \[pc, #4\] @ \(a270 <_thumb\+0x44>\)
#------------------------------------------------------------------------------
#------ GP-relative offset of ttf1's .igot.plt entry
#------------------------------------------------------------------------------
#------ thumb entry to abf1's .iplt entry
#------------------------------------------------------------------------------
a27c: f43e af04 beq\.w 9088 <abf2@plt\+0x2c>
- a280: 4c00 ldr r4, \[pc, #0\] ; \(a284 <_thumb\+0x58>\)
- a282: 4c01 ldr r4, \[pc, #4\] ; \(a288 <_thumb\+0x5c>\)
+ a280: 4c00 ldr r4, \[pc, #0\] @ \(a284 <_thumb\+0x58>\)
+ a282: 4c01 ldr r4, \[pc, #4\] @ \(a288 <_thumb\+0x5c>\)
#------------------------------------------------------------------------------
#------ GP-relative offset of abf1's .igot.plt entry
#------------------------------------------------------------------------------
#------ thumb entry to tbf1's .iplt entry
#------------------------------------------------------------------------------
a294: f43e af0e beq\.w 90b4 <abf2@plt\+0x58>
- a298: 4c00 ldr r4, \[pc, #0\] ; \(a29c <_thumb\+0x70>\)
- a29a: 4c01 ldr r4, \[pc, #4\] ; \(a2a0 <_thumb\+0x74>\)
+ a298: 4c00 ldr r4, \[pc, #0\] @ \(a29c <_thumb\+0x70>\)
+ a29a: 4c01 ldr r4, \[pc, #4\] @ \(a2a0 <_thumb\+0x74>\)
#------------------------------------------------------------------------------
#------ GP-relative offset of tbf1's .igot.plt entry
#------------------------------------------------------------------------------
#------ thumb entry to atf2's .plt entry
#------------------------------------------------------------------------------
a2ac: f43e aeb2 beq\.w 9014 <atf2@plt>
- a2b0: 4c00 ldr r4, \[pc, #0\] ; \(a2b4 <_thumb\+0x88>\)
- a2b2: 4c01 ldr r4, \[pc, #4\] ; \(a2b8 <_thumb\+0x8c>\)
+ a2b0: 4c00 ldr r4, \[pc, #0\] @ \(a2b4 <_thumb\+0x88>\)
+ a2b2: 4c01 ldr r4, \[pc, #4\] @ \(a2b8 <_thumb\+0x8c>\)
#------------------------------------------------------------------------------
#------ .got offset for atf2
#------------------------------------------------------------------------------
#------ thumb entry to ttf2's .plt entry
#------------------------------------------------------------------------------
a2c4: f43e aeae beq\.w 9024 <ttf2@plt>
- a2c8: 4c00 ldr r4, \[pc, #0\] ; \(a2cc <_thumb\+0xa0>\)
- a2ca: 4c01 ldr r4, \[pc, #4\] ; \(a2d0 <_thumb\+0xa4>\)
+ a2c8: 4c00 ldr r4, \[pc, #0\] @ \(a2cc <_thumb\+0xa0>\)
+ a2ca: 4c01 ldr r4, \[pc, #4\] @ \(a2d0 <_thumb\+0xa4>\)
#------------------------------------------------------------------------------
#------ .got offset for ttf2
#------------------------------------------------------------------------------
#------ thumb entry to abf2's .plt entry
#------------------------------------------------------------------------------
a2dc: f43e aebe beq\.w 905c <abf2@plt>
- a2e0: 4c00 ldr r4, \[pc, #0\] ; \(a2e4 <_thumb\+0xb8>\)
- a2e2: 4c01 ldr r4, \[pc, #4\] ; \(a2e8 <_thumb\+0xbc>\)
+ a2e0: 4c00 ldr r4, \[pc, #0\] @ \(a2e4 <_thumb\+0xb8>\)
+ a2e2: 4c01 ldr r4, \[pc, #4\] @ \(a2e8 <_thumb\+0xbc>\)
#------------------------------------------------------------------------------
#------ .got offset for abf2
#------------------------------------------------------------------------------
#------ thumb entry to tbf2's .plt entry
#------------------------------------------------------------------------------
a2f4: f43e ae9e beq\.w 9034 <tbf2@plt>
- a2f8: 4c00 ldr r4, \[pc, #0\] ; \(a2fc <_thumb\+0xd0>\)
- a2fa: 4c01 ldr r4, \[pc, #4\] ; \(a300 <_thumb\+0xd4>\)
+ a2f8: 4c00 ldr r4, \[pc, #0\] @ \(a2fc <_thumb\+0xd0>\)
+ a2fa: 4c01 ldr r4, \[pc, #4\] @ \(a300 <_thumb\+0xd4>\)
#------------------------------------------------------------------------------
#------ .got offset for tbf2
#------------------------------------------------------------------------------
#------ thumb entry to atf3's .iplt entry
#------------------------------------------------------------------------------
a30c: f43e aee0 beq\.w 90d0 <abf2@plt\+0x74>
- a310: 4c00 ldr r4, \[pc, #0\] ; \(a314 <_thumb\+0xe8>\)
- a312: 4c01 ldr r4, \[pc, #4\] ; \(a318 <_thumb\+0xec>\)
+ a310: 4c00 ldr r4, \[pc, #0\] @ \(a314 <_thumb\+0xe8>\)
+ a312: 4c01 ldr r4, \[pc, #4\] @ \(a318 <_thumb\+0xec>\)
#------------------------------------------------------------------------------
#------ GP-relative offset of atf3's .igot.plt entry
#------------------------------------------------------------------------------
#------ thumb entry to ttf3's .iplt entry
#------------------------------------------------------------------------------
a324: f43e aee4 beq\.w 90f0 <abf2@plt\+0x94>
- a328: 4c00 ldr r4, \[pc, #0\] ; \(a32c <_thumb\+0x100>\)
- a32a: 4c01 ldr r4, \[pc, #4\] ; \(a330 <_thumb\+0x104>\)
+ a328: 4c00 ldr r4, \[pc, #0\] @ \(a32c <_thumb\+0x100>\)
+ a32a: 4c01 ldr r4, \[pc, #4\] @ \(a330 <_thumb\+0x104>\)
#------------------------------------------------------------------------------
#------ GP-relative offset of ttf3's .igot.plt entry
#------------------------------------------------------------------------------
#------ thumb entry to abf3's .iplt entry
#------------------------------------------------------------------------------
a33c: f43e aed0 beq\.w 90e0 <abf2@plt\+0x84>
- a340: 4c00 ldr r4, \[pc, #0\] ; \(a344 <_thumb\+0x118>\)
- a342: 4c01 ldr r4, \[pc, #4\] ; \(a348 <_thumb\+0x11c>\)
+ a340: 4c00 ldr r4, \[pc, #0\] @ \(a344 <_thumb\+0x118>\)
+ a342: 4c01 ldr r4, \[pc, #4\] @ \(a348 <_thumb\+0x11c>\)
#------------------------------------------------------------------------------
#------ GP-relative offset of abf3's .igot.plt entry
#------------------------------------------------------------------------------
#------ thumb entry to tbf3's .iplt entry
#------------------------------------------------------------------------------
a354: f43e aed4 beq\.w 9100 <abf2@plt\+0xa4>
- a358: 4c00 ldr r4, \[pc, #0\] ; \(a35c <_thumb\+0x130>\)
- a35a: 4c01 ldr r4, \[pc, #4\] ; \(a360 <_thumb\+0x134>\)
+ a358: 4c00 ldr r4, \[pc, #0\] @ \(a35c <_thumb\+0x130>\)
+ a35a: 4c01 ldr r4, \[pc, #4\] @ \(a360 <_thumb\+0x134>\)
#------------------------------------------------------------------------------
#------ GP-relative offset of tbf3's .igot.plt entry
#------------------------------------------------------------------------------
#------ thumb entry to atf4's .iplt entry
#------------------------------------------------------------------------------
a36c: f43e aef4 beq\.w 9158 <abf2@plt\+0xfc>
- a370: 4c00 ldr r4, \[pc, #0\] ; \(a374 <_thumb\+0x148>\)
- a372: 4c01 ldr r4, \[pc, #4\] ; \(a378 <_thumb\+0x14c>\)
+ a370: 4c00 ldr r4, \[pc, #0\] @ \(a374 <_thumb\+0x148>\)
+ a372: 4c01 ldr r4, \[pc, #4\] @ \(a378 <_thumb\+0x14c>\)
#------------------------------------------------------------------------------
#------ .got offset for atf4
#------------------------------------------------------------------------------
#------ thumb entry to ttf4's .iplt entry
#------------------------------------------------------------------------------
a384: f43e aeda beq\.w 913c <abf2@plt\+0xe0>
- a388: 4c00 ldr r4, \[pc, #0\] ; \(a38c <_thumb\+0x160>\)
- a38a: 4c01 ldr r4, \[pc, #4\] ; \(a390 <_thumb\+0x164>\)
+ a388: 4c00 ldr r4, \[pc, #0\] @ \(a38c <_thumb\+0x160>\)
+ a38a: 4c01 ldr r4, \[pc, #4\] @ \(a390 <_thumb\+0x164>\)
#------------------------------------------------------------------------------
#------ .got offset for ttf4
#------------------------------------------------------------------------------
#------ thumb entry to abf4's .iplt entry
#------------------------------------------------------------------------------
a39c: f43e aebe beq\.w 911c <abf2@plt\+0xc0>
- a3a0: 4c00 ldr r4, \[pc, #0\] ; \(a3a4 <_thumb\+0x178>\)
- a3a2: 4c01 ldr r4, \[pc, #4\] ; \(a3a8 <_thumb\+0x17c>\)
+ a3a0: 4c00 ldr r4, \[pc, #0\] @ \(a3a4 <_thumb\+0x178>\)
+ a3a2: 4c01 ldr r4, \[pc, #4\] @ \(a3a8 <_thumb\+0x17c>\)
#------------------------------------------------------------------------------
#------ .got offset for abf4
#------------------------------------------------------------------------------
#------ thumb entry to tbf4's .iplt entry
#------------------------------------------------------------------------------
a3b4: f43e aeba beq\.w 912c <abf2@plt\+0xd0>
- a3b8: 4c00 ldr r4, \[pc, #0\] ; \(a3bc <_thumb\+0x190>\)
- a3ba: 4c01 ldr r4, \[pc, #4\] ; \(a3c0 <_thumb\+0x194>\)
+ a3b8: 4c00 ldr r4, \[pc, #0\] @ \(a3bc <_thumb\+0x190>\)
+ a3ba: 4c01 ldr r4, \[pc, #4\] @ \(a3c0 <_thumb\+0x194>\)
#------------------------------------------------------------------------------
#------ .got offset for tbf4
#------------------------------------------------------------------------------
#------ f1's .iplt entry
#------------------------------------------------------------------------------
9000: e28fc600 add ip, pc, #0, 12
- 9004: e28cca08 add ip, ip, #8, 20 ; 0x8000
+ 9004: e28cca08 add ip, ip, #8, 20 @ 0x8000
9008: e5bcf004 ldr pc, \[ip, #4\]!
#------------------------------------------------------------------------------
#------ f3's .iplt entry
#------------------------------------------------------------------------------
900c: e28fc600 add ip, pc, #0, 12
- 9010: e28cca07 add ip, ip, #28672 ; 0x7000
- 9014: e5bcfffc ldr pc, \[ip, #4092\]! ; 0xffc
+ 9010: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9014: e5bcfffc ldr pc, \[ip, #4092\]! @ 0xffc
#------------------------------------------------------------------------------
#------ f2's .iplt entry
#------------------------------------------------------------------------------
9018: e28fc600 add ip, pc, #0, 12
- 901c: e28cca07 add ip, ip, #28672 ; 0x7000
- 9020: e5bcfff4 ldr pc, \[ip, #4084\]! ; 0xff4
+ 901c: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9020: e5bcfff4 ldr pc, \[ip, #4084\]! @ 0xff4
Disassembly of section \.text:
0000a00c <_start>:
a00c: eb0017fb bl 10000 <foo>
- a010: e59f4000 ldr r4, \[pc\] ; a018 <_start\+0xc>
- a014: e59f4000 ldr r4, \[pc\] ; a01c <_start\+0x10>
+ a010: e59f4000 ldr r4, \[pc\] @ a018 <_start\+0xc>
+ a014: e59f4000 ldr r4, \[pc\] @ a01c <_start\+0x10>
#------------------------------------------------------------------------------
#------ .got offset for foo
#------------------------------------------------------------------------------
#------ f1's .iplt entry
#------------------------------------------------------------------------------
a020: ebfffbf6 bl 9000 <__irel_end\+0xfe8>
- a024: e59f4000 ldr r4, \[pc\] ; a02c <_start\+0x20>
- a028: e59f4000 ldr r4, \[pc\] ; a030 <_start\+0x24>
+ a024: e59f4000 ldr r4, \[pc\] @ a02c <_start\+0x20>
+ a028: e59f4000 ldr r4, \[pc\] @ a030 <_start\+0x24>
#------------------------------------------------------------------------------
#------ GP-relative offset of f1's .igot.plt entry
#------------------------------------------------------------------------------
#------ f2's .iplt entry
#------------------------------------------------------------------------------
a034: ebfffbf7 bl 9018 <__irel_end\+0x1000>
- a038: e59f4000 ldr r4, \[pc\] ; a040 <_start\+0x34>
- a03c: e59f4000 ldr r4, \[pc\] ; a044 <_start\+0x38>
+ a038: e59f4000 ldr r4, \[pc\] @ a040 <_start\+0x34>
+ a03c: e59f4000 ldr r4, \[pc\] @ a044 <_start\+0x38>
#------------------------------------------------------------------------------
#------ GP-relative offset of f2's .igot.plt entry
#------------------------------------------------------------------------------
#------ f3's .iplt entry
#------------------------------------------------------------------------------
a048: ebfffbef bl 900c <__irel_end\+0xff4>
- a04c: e59f4000 ldr r4, \[pc\] ; a054 <_start\+0x48>
- a050: e59f4000 ldr r4, \[pc\] ; a058 <_start\+0x4c>
+ a04c: e59f4000 ldr r4, \[pc\] @ a054 <_start\+0x48>
+ a050: e59f4000 ldr r4, \[pc\] @ a058 <_start\+0x4c>
#------------------------------------------------------------------------------
#------ GP-relative offset of f3's .igot.plt entry
#------------------------------------------------------------------------------
#------ f3's .iplt entry
#------------------------------------------------------------------------------
9004: e28fc600 add ip, pc, #0, 12
- 9008: e28cca08 add ip, ip, #8, 20 ; 0x8000
+ 9008: e28cca08 add ip, ip, #8, 20 @ 0x8000
900c: e5bcf000 ldr pc, \[ip, #0\]!
#------------------------------------------------------------------------------
#------ f2's .iplt entry
#------------------------------------------------------------------------------
9010: e28fc600 add ip, pc, #0, 12
- 9014: e28cca07 add ip, ip, #28672 ; 0x7000
- 9018: e5bcfff8 ldr pc, \[ip, #4088\]! ; 0xff8
+ 9014: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9018: e5bcfff8 ldr pc, \[ip, #4088\]! @ 0xff8
#------------------------------------------------------------------------------
#------ thumb entry to f4's .iplt entry
#------------------------------------------------------------------------------
#------ f4's .iplt entry
#------------------------------------------------------------------------------
9020: e28fc600 add ip, pc, #0, 12
- 9024: e28cca07 add ip, ip, #28672 ; 0x7000
- 9028: e5bcffec ldr pc, \[ip, #4076\]! ; 0xfec
+ 9024: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9028: e5bcffec ldr pc, \[ip, #4076\]! @ 0xfec
#------------------------------------------------------------------------------
#------ f1's .iplt entry
#------------------------------------------------------------------------------
902c: e28fc600 add ip, pc, #0, 12
- 9030: e28cca07 add ip, ip, #28672 ; 0x7000
- 9034: e5bcffe4 ldr pc, \[ip, #4068\]! ; 0xfe4
+ 9030: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9034: e5bcffe4 ldr pc, \[ip, #4068\]! @ 0xfe4
Disassembly of section \.text:
a010: eb0017fa bl 10000 <foo>
a014: ea0017f9 b 10000 <foo>
a018: 0a0017f8 beq 10000 <foo>
- a01c: e59f4000 ldr r4, \[pc\] ; a024 <_start\+0x14>
- a020: e59f4000 ldr r4, \[pc\] ; a028 <_start\+0x18>
+ a01c: e59f4000 ldr r4, \[pc\] @ a024 <_start\+0x14>
+ a020: e59f4000 ldr r4, \[pc\] @ a028 <_start\+0x18>
#------------------------------------------------------------------------------
#------ .got offset for foo
#------------------------------------------------------------------------------
#------ f1's .iplt entry
#------------------------------------------------------------------------------
a034: 0afffbfc beq 902c <__irel_end\+0x100c>
- a038: e59f4000 ldr r4, \[pc\] ; a040 <_start\+0x30>
- a03c: e59f4000 ldr r4, \[pc\] ; a044 <_start\+0x34>
+ a038: e59f4000 ldr r4, \[pc\] @ a040 <_start\+0x30>
+ a03c: e59f4000 ldr r4, \[pc\] @ a044 <_start\+0x34>
#------------------------------------------------------------------------------
#------ GP-relative offset of f1's .igot.plt entry
#------------------------------------------------------------------------------
#------ f2's .iplt entry
#------------------------------------------------------------------------------
a050: 0afffbee beq 9010 <__irel_end\+0xff0>
- a054: e59f4000 ldr r4, \[pc\] ; a05c <_start\+0x4c>
- a058: e59f4000 ldr r4, \[pc\] ; a060 <_start\+0x50>
+ a054: e59f4000 ldr r4, \[pc\] @ a05c <_start\+0x4c>
+ a058: e59f4000 ldr r4, \[pc\] @ a060 <_start\+0x50>
#------------------------------------------------------------------------------
#------ GP-relative offset of f2's .igot.plt entry
#------------------------------------------------------------------------------
a064: f005 ffcc bl 10000 <foo>
a068: f005 bfca b\.w 10000 <foo>
a06c: f005 87c8 beq\.w 10000 <foo>
- a070: 4c00 ldr r4, \[pc, #0\] ; \(a074 <_thumb\+0x10>\)
- a072: 4c01 ldr r4, \[pc, #4\] ; \(a078 <_thumb\+0x14>\)
+ a070: 4c00 ldr r4, \[pc, #0\] @ \(a074 <_thumb\+0x10>\)
+ a072: 4c01 ldr r4, \[pc, #4\] @ \(a078 <_thumb\+0x14>\)
#------------------------------------------------------------------------------
#------ .got offset for foo
#------------------------------------------------------------------------------
#------ thumb entry to f3's .iplt entry
#------------------------------------------------------------------------------
a084: f43e afbc beq\.w 9000 <__irel_end\+0xfe0>
- a088: 4c00 ldr r4, \[pc, #0\] ; \(a08c <_thumb\+0x28>\)
- a08a: 4c01 ldr r4, \[pc, #4\] ; \(a090 <_thumb\+0x2c>\)
+ a088: 4c00 ldr r4, \[pc, #0\] @ \(a08c <_thumb\+0x28>\)
+ a08a: 4c01 ldr r4, \[pc, #4\] @ \(a090 <_thumb\+0x2c>\)
#------------------------------------------------------------------------------
#------ GP-relative offset of f3's .igot.plt entry
#------------------------------------------------------------------------------
#------ thumb entry to f4's .iplt entry
#------------------------------------------------------------------------------
a09c: f43e afbe beq\.w 901c <__irel_end\+0xffc>
- a0a0: 4c00 ldr r4, \[pc, #0\] ; \(a0a4 <_thumb\+0x40>\)
- a0a2: 4c01 ldr r4, \[pc, #4\] ; \(a0a8 <_thumb\+0x44>\)
+ a0a0: 4c00 ldr r4, \[pc, #0\] @ \(a0a4 <_thumb\+0x40>\)
+ a0a2: 4c01 ldr r4, \[pc, #4\] @ \(a0a8 <_thumb\+0x44>\)
#------------------------------------------------------------------------------
#------ GP-relative offset of f4's .igot.plt entry
#------------------------------------------------------------------------------
#------ f1's .iplt entry
#------------------------------------------------------------------------------
9000: e28fc600 add ip, pc, #0, 12
- 9004: e28cca08 add ip, ip, #8, 20 ; 0x8000
+ 9004: e28cca08 add ip, ip, #8, 20 @ 0x8000
9008: e5bcf004 ldr pc, \[ip, #4\]!
#------------------------------------------------------------------------------
#------ f3's .iplt entry
#------------------------------------------------------------------------------
900c: e28fc600 add ip, pc, #0, 12
- 9010: e28cca07 add ip, ip, #28672 ; 0x7000
- 9014: e5bcfffc ldr pc, \[ip, #4092\]! ; 0xffc
+ 9010: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9014: e5bcfffc ldr pc, \[ip, #4092\]! @ 0xffc
Disassembly of section \.text:
0000a008 <arm>:
a008: eb0017fc bl 10000 <foo>
- a00c: e59f4000 ldr r4, \[pc\]
; a014 <arm\+0xc>
- a010: e59f4000 ldr r4, \[pc\]
; a018 <arm\+0x10>
+ a00c: e59f4000 ldr r4, \[pc\]
@ a014 <arm\+0xc>
+ a010: e59f4000 ldr r4, \[pc\]
@ a018 <arm\+0x10>
#------------------------------------------------------------------------------
#------ .got offset for foo
#------------------------------------------------------------------------------
#------ f1's .iplt entry
#------------------------------------------------------------------------------
a01c: ebfffbf7 bl 9000 <f1-0x1000>
- a020: e59f4000 ldr r4, \[pc\]
; a028 <arm\+0x20>
- a024: e59f4000 ldr r4, \[pc\]
; a02c <arm\+0x24>
+ a020: e59f4000 ldr r4, \[pc\]
@ a028 <arm\+0x20>
+ a024: e59f4000 ldr r4, \[pc\]
@ a02c <arm\+0x24>
#------------------------------------------------------------------------------
#------ GP-relative offset of f1's .igot.plt entry
#------------------------------------------------------------------------------
#------ f3's .iplt entry
#------------------------------------------------------------------------------
a030: ebfffbf5 bl 900c <f1-0xff4>
- a034: e59f4000 ldr r4, \[pc\]
; a03c <arm\+0x34>
- a038: e59f4000 ldr r4, \[pc\]
; a040 <arm\+0x38>
+ a034: e59f4000 ldr r4, \[pc\]
@ a03c <arm\+0x34>
+ a038: e59f4000 ldr r4, \[pc\]
@ a040 <arm\+0x38>
#------------------------------------------------------------------------------
#------ GP-relative offset of f3's .igot.plt entry
#------------------------------------------------------------------------------
#------ aaf1's .iplt entry
#------------------------------------------------------------------------------
9000: e28fc600 add ip, pc, #0, 12
- 9004: e28cca08 add ip, ip, #8, 20 ; 0x8000
+ 9004: e28cca08 add ip, ip, #8, 20 @ 0x8000
9008: e5bcf004 ldr pc, \[ip, #4\]!
#------------------------------------------------------------------------------
#------ thumb entry to atf1's .iplt entry
#------ atf1's .iplt entry
#------------------------------------------------------------------------------
9010: e28fc600 add ip, pc, #0, 12
- 9014: e28cca07 add ip, ip, #28672 ; 0x7000
- 9018: e5bcfff8 ldr pc, \[ip, #4088\]! ; 0xff8
+ 9014: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9018: e5bcfff8 ldr pc, \[ip, #4088\]! @ 0xff8
#------------------------------------------------------------------------------
#------ thumb entry to abf1's .iplt entry
#------------------------------------------------------------------------------
#------ abf1's .iplt entry
#------------------------------------------------------------------------------
9020: e28fc600 add ip, pc, #0, 12
- 9024: e28cca07 add ip, ip, #28672 ; 0x7000
- 9028: e5bcffec ldr pc, \[ip, #4076\]! ; 0xfec
+ 9024: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9028: e5bcffec ldr pc, \[ip, #4076\]! @ 0xfec
#------------------------------------------------------------------------------
#------ taf1's .iplt entry
#------------------------------------------------------------------------------
902c: e28fc600 add ip, pc, #0, 12
- 9030: e28cca07 add ip, ip, #28672 ; 0x7000
- 9034: e5bcffe4 ldr pc, \[ip, #4068\]! ; 0xfe4
+ 9030: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9034: e5bcffe4 ldr pc, \[ip, #4068\]! @ 0xfe4
#------------------------------------------------------------------------------
#------ thumb entry to ttf1's .iplt entry
#------------------------------------------------------------------------------
#------ ttf1's .iplt entry
#------------------------------------------------------------------------------
903c: e28fc600 add ip, pc, #0, 12
- 9040: e28cca07 add ip, ip, #28672 ; 0x7000
- 9044: e5bcffd8 ldr pc, \[ip, #4056\]! ; 0xfd8
+ 9040: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9044: e5bcffd8 ldr pc, \[ip, #4056\]! @ 0xfd8
#------------------------------------------------------------------------------
#------ thumb entry to tbf1's .iplt entry
#------------------------------------------------------------------------------
#------ tbf1's .iplt entry
#------------------------------------------------------------------------------
904c: e28fc600 add ip, pc, #0, 12
- 9050: e28cca07 add ip, ip, #28672 ; 0x7000
- 9054: e5bcffcc ldr pc, \[ip, #4044\]! ; 0xfcc
+ 9050: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9054: e5bcffcc ldr pc, \[ip, #4044\]! @ 0xfcc
#------------------------------------------------------------------------------
#------ thumb entry to atf3's .iplt entry
#------------------------------------------------------------------------------
#------ atf3's .iplt entry
#------------------------------------------------------------------------------
905c: e28fc600 add ip, pc, #0, 12
- 9060: e28cca07 add ip, ip, #28672 ; 0x7000
- 9064: e5bcffc0 ldr pc, \[ip, #4032\]! ; 0xfc0
+ 9060: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9064: e5bcffc0 ldr pc, \[ip, #4032\]! @ 0xfc0
#------------------------------------------------------------------------------
#------ thumb entry to abf3's .iplt entry
#------------------------------------------------------------------------------
#------ abf3's .iplt entry
#------------------------------------------------------------------------------
906c: e28fc600 add ip, pc, #0, 12
- 9070: e28cca07 add ip, ip, #28672 ; 0x7000
- 9074: e5bcffb4 ldr pc, \[ip, #4020\]! ; 0xfb4
+ 9070: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9074: e5bcffb4 ldr pc, \[ip, #4020\]! @ 0xfb4
#------------------------------------------------------------------------------
#------ thumb entry to ttf3's .iplt entry
#------------------------------------------------------------------------------
#------ ttf3's .iplt entry
#------------------------------------------------------------------------------
907c: e28fc600 add ip, pc, #0, 12
- 9080: e28cca07 add ip, ip, #28672 ; 0x7000
- 9084: e5bcffa8 ldr pc, \[ip, #4008\]! ; 0xfa8
+ 9080: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9084: e5bcffa8 ldr pc, \[ip, #4008\]! @ 0xfa8
#------------------------------------------------------------------------------
#------ thumb entry to tbf3's .iplt entry
#------------------------------------------------------------------------------
#------ tbf3's .iplt entry
#------------------------------------------------------------------------------
908c: e28fc600 add ip, pc, #0, 12
- 9090: e28cca07 add ip, ip, #28672 ; 0x7000
- 9094: e5bcff9c ldr pc, \[ip, #3996\]! ; 0xf9c
+ 9090: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9094: e5bcff9c ldr pc, \[ip, #3996\]! @ 0xf9c
#------------------------------------------------------------------------------
#------ taf3's .iplt entry
#------------------------------------------------------------------------------
9098: e28fc600 add ip, pc, #0, 12
- 909c: e28cca07 add ip, ip, #28672 ; 0x7000
- 90a0: e5bcff94 ldr pc, \[ip, #3988\]! ; 0xf94
+ 909c: e28cca07 add ip, ip, #28672 @ 0x7000
+ 90a0: e5bcff94 ldr pc, \[ip, #3988\]! @ 0xf94
#------------------------------------------------------------------------------
#------ aaf3's .iplt entry
#------------------------------------------------------------------------------
90a4: e28fc600 add ip, pc, #0, 12
- 90a8: e28cca07 add ip, ip, #28672 ; 0x7000
- 90ac: e5bcff8c ldr pc, \[ip, #3980\]! ; 0xf8c
+ 90a8: e28cca07 add ip, ip, #28672 @ 0x7000
+ 90ac: e5bcff8c ldr pc, \[ip, #3980\]! @ 0xf8c
Disassembly of section \.text:
a028: eb0017f4 bl 10000 <foo>
a02c: ea0017f3 b 10000 <foo>
a030: 0a0017f2 beq 10000 <foo>
- a034: e59f4000 ldr r4, \[pc\]
; a03c <arm\+0x14>
- a038: e59f4000 ldr r4, \[pc\]
; a040 <arm\+0x18>
+ a034: e59f4000 ldr r4, \[pc\]
@ a03c <arm\+0x14>
+ a038: e59f4000 ldr r4, \[pc\]
@ a040 <arm\+0x18>
#------------------------------------------------------------------------------
#------ .got offset for foo
#------------------------------------------------------------------------------
#------ aaf1's .iplt entry
#------------------------------------------------------------------------------
a04c: 0afffbeb beq 9000 <aaf1-0x1000>
- a050: e59f4000 ldr r4, \[pc\]
; a058 <arm\+0x30>
- a054: e59f4000 ldr r4, \[pc\]
; a05c <arm\+0x34>
+ a050: e59f4000 ldr r4, \[pc\]
@ a058 <arm\+0x30>
+ a054: e59f4000 ldr r4, \[pc\]
@ a05c <arm\+0x34>
#------------------------------------------------------------------------------
#------ GP-relative offset of aaf1's .igot.plt entry
#------------------------------------------------------------------------------
#------ taf1's .iplt entry
#------------------------------------------------------------------------------
a068: 0afffbef beq 902c <aaf1-0xfd4>
- a06c: e59f4000 ldr r4, \[pc\]
; a074 <arm\+0x4c>
- a070: e59f4000 ldr r4, \[pc\]
; a078 <arm\+0x50>
+ a06c: e59f4000 ldr r4, \[pc\]
@ a074 <arm\+0x4c>
+ a070: e59f4000 ldr r4, \[pc\]
@ a078 <arm\+0x50>
#------------------------------------------------------------------------------
#------ GP-relative offset of taf1's .igot.plt entry
#------------------------------------------------------------------------------
#------ abf1's .iplt entry
#------------------------------------------------------------------------------
a084: 0afffbe5 beq 9020 <aaf1-0xfe0>
- a088: e59f4000 ldr r4, \[pc\]
; a090 <arm\+0x68>
- a08c: e59f4000 ldr r4, \[pc\]
; a094 <arm\+0x6c>
+ a088: e59f4000 ldr r4, \[pc\]
@ a090 <arm\+0x68>
+ a08c: e59f4000 ldr r4, \[pc\]
@ a094 <arm\+0x6c>
#------------------------------------------------------------------------------
#------ GP-relative offset of abf1's .igot.plt entry
#------------------------------------------------------------------------------
#------ tbf1's .iplt entry
#------------------------------------------------------------------------------
a0a0: 0afffbe9 beq 904c <aaf1-0xfb4>
- a0a4: e59f4000 ldr r4, \[pc\]
; a0ac <arm\+0x84>
- a0a8: e59f4000 ldr r4, \[pc\]
; a0b0 <arm\+0x88>
+ a0a4: e59f4000 ldr r4, \[pc\]
@ a0ac <arm\+0x84>
+ a0a8: e59f4000 ldr r4, \[pc\]
@ a0b0 <arm\+0x88>
#------------------------------------------------------------------------------
#------ GP-relative offset of tbf1's .igot.plt entry
#------------------------------------------------------------------------------
#------ aaf3's .plt entry
#------------------------------------------------------------------------------
a0bc: 0afffbf8 beq 90a4 <aaf1-0xf5c>
- a0c0: e59f4000 ldr r4, \[pc\]
; a0c8 <arm\+0xa0>
- a0c4: e59f4000 ldr r4, \[pc\]
; a0cc <arm\+0xa4>
+ a0c0: e59f4000 ldr r4, \[pc\]
@ a0c8 <arm\+0xa0>
+ a0c4: e59f4000 ldr r4, \[pc\]
@ a0cc <arm\+0xa4>
#------------------------------------------------------------------------------
#------ GP-relative offset of aaf3's .igot.plt entry
#------------------------------------------------------------------------------
#------ taf3's .iplt entry
#------------------------------------------------------------------------------
a0d8: 0afffbee beq 9098 <aaf1-0xf68>
- a0dc: e59f4000 ldr r4, \[pc\]
; a0e4 <arm\+0xbc>
- a0e0: e59f4000 ldr r4, \[pc\]
; a0e8 <arm\+0xc0>
+ a0dc: e59f4000 ldr r4, \[pc\]
@ a0e4 <arm\+0xbc>
+ a0e0: e59f4000 ldr r4, \[pc\]
@ a0e8 <arm\+0xc0>
#------------------------------------------------------------------------------
#------ GP-relative offset of taf3's .igot.plt entry
#------------------------------------------------------------------------------
#------ abf3's .iplt entry
#------------------------------------------------------------------------------
a0f4: 0afffbdc beq 906c <aaf1-0xf94>
- a0f8: e59f4000 ldr r4, \[pc\]
; a100 <arm\+0xd8>
- a0fc: e59f4000 ldr r4, \[pc\]
; a104 <arm\+0xdc>
+ a0f8: e59f4000 ldr r4, \[pc\]
@ a100 <arm\+0xd8>
+ a0fc: e59f4000 ldr r4, \[pc\]
@ a104 <arm\+0xdc>
#------------------------------------------------------------------------------
#------ GP-relative offset of abf3's .igot.plt entry
#------------------------------------------------------------------------------
#------ tbf3's .iplt entry
#------------------------------------------------------------------------------
a110: 0afffbdd beq 908c <aaf1-0xf74>
- a114: e59f4000 ldr r4, \[pc\]
; a11c <arm\+0xf4>
- a118: e59f4000 ldr r4, \[pc\]
; a120 <arm\+0xf8>
+ a114: e59f4000 ldr r4, \[pc\]
@ a11c <arm\+0xf4>
+ a118: e59f4000 ldr r4, \[pc\]
@ a120 <arm\+0xf8>
#------------------------------------------------------------------------------
#------ GP-relative offset of tbf3's .igot.plt entry
#------------------------------------------------------------------------------
a124: f005 ff6c bl 10000 <foo>
a128: f005 bf6a b\.w 10000 <foo>
a12c: f005 8768 beq\.w 10000 <foo>
- a130: 4c00 ldr r4, \[pc, #0\] ; \(a134 <_thumb\+0x10>\)
- a132: 4c01 ldr r4, \[pc, #4\] ; \(a138 <_thumb\+0x14>\)
+ a130: 4c00 ldr r4, \[pc, #0\] @ \(a134 <_thumb\+0x10>\)
+ a132: 4c01 ldr r4, \[pc, #4\] @ \(a138 <_thumb\+0x14>\)
#------------------------------------------------------------------------------
#------ .got offset for foo
#------------------------------------------------------------------------------
#------ thumb entry to atf1's .iplt entry
#------------------------------------------------------------------------------
a144: f43e af62 beq\.w 900c <aaf1-0xff4>
- a148: 4c00 ldr r4, \[pc, #0\] ; \(a14c <_thumb\+0x28>\)
- a14a: 4c01 ldr r4, \[pc, #4\] ; \(a150 <_thumb\+0x2c>\)
+ a148: 4c00 ldr r4, \[pc, #0\] @ \(a14c <_thumb\+0x28>\)
+ a14a: 4c01 ldr r4, \[pc, #4\] @ \(a150 <_thumb\+0x2c>\)
#------------------------------------------------------------------------------
#------ GP-relative offset of atf1's .igot.plt entry
#------------------------------------------------------------------------------
#------ thumb entry to ttf1's .iplt entry
#------------------------------------------------------------------------------
a15c: f43e af6c beq\.w 9038 <aaf1-0xfc8>
- a160: 4c00 ldr r4, \[pc, #0\] ; \(a164 <_thumb\+0x40>\)
- a162: 4c01 ldr r4, \[pc, #4\] ; \(a168 <_thumb\+0x44>\)
+ a160: 4c00 ldr r4, \[pc, #0\] @ \(a164 <_thumb\+0x40>\)
+ a162: 4c01 ldr r4, \[pc, #4\] @ \(a168 <_thumb\+0x44>\)
#------------------------------------------------------------------------------
#------ GP-relative offset of ttf1's .igot.plt entry
#------------------------------------------------------------------------------
#------ thumb entry to abf1's .iplt entry
#------------------------------------------------------------------------------
a174: f43e af52 beq\.w 901c <aaf1-0xfe4>
- a178: 4c00 ldr r4, \[pc, #0\] ; \(a17c <_thumb\+0x58>\)
- a17a: 4c01 ldr r4, \[pc, #4\] ; \(a180 <_thumb\+0x5c>\)
+ a178: 4c00 ldr r4, \[pc, #0\] @ \(a17c <_thumb\+0x58>\)
+ a17a: 4c01 ldr r4, \[pc, #4\] @ \(a180 <_thumb\+0x5c>\)
#------------------------------------------------------------------------------
#------ GP-relative offset of abf1's .igot.plt entry
#------------------------------------------------------------------------------
#------ thumb entry to tbf1's .iplt entry
#------------------------------------------------------------------------------
a18c: f43e af5c beq\.w 9048 <aaf1-0xfb8>
- a190: 4c00 ldr r4, \[pc, #0\] ; \(a194 <_thumb\+0x70>\)
- a192: 4c01 ldr r4, \[pc, #4\] ; \(a198 <_thumb\+0x74>\)
+ a190: 4c00 ldr r4, \[pc, #0\] @ \(a194 <_thumb\+0x70>\)
+ a192: 4c01 ldr r4, \[pc, #4\] @ \(a198 <_thumb\+0x74>\)
#------------------------------------------------------------------------------
#------ GP-relative offset of tbf1's .igot.plt entry
#------------------------------------------------------------------------------
#------ thumb entry to atf3's .iplt entry
#------------------------------------------------------------------------------
a1a4: f43e af58 beq\.w 9058 <aaf1-0xfa8>
- a1a8: 4c00 ldr r4, \[pc, #0\] ; \(a1ac <_thumb\+0x88>\)
- a1aa: 4c01 ldr r4, \[pc, #4\] ; \(a1b0 <_thumb\+0x8c>\)
+ a1a8: 4c00 ldr r4, \[pc, #0\] @ \(a1ac <_thumb\+0x88>\)
+ a1aa: 4c01 ldr r4, \[pc, #4\] @ \(a1b0 <_thumb\+0x8c>\)
#------------------------------------------------------------------------------
#------ GP-relative offset of atf3's .igot.plt entry
#------------------------------------------------------------------------------
#------ thumb entry to ttf3's .iplt entry
#------------------------------------------------------------------------------
a1bc: f43e af5c beq\.w 9078 <aaf1-0xf88>
- a1c0: 4c00 ldr r4, \[pc, #0\] ; \(a1c4 <_thumb\+0xa0>\)
- a1c2: 4c01 ldr r4, \[pc, #4\] ; \(a1c8 <_thumb\+0xa4>\)
+ a1c0: 4c00 ldr r4, \[pc, #0\] @ \(a1c4 <_thumb\+0xa0>\)
+ a1c2: 4c01 ldr r4, \[pc, #4\] @ \(a1c8 <_thumb\+0xa4>\)
#------------------------------------------------------------------------------
#------ GP-relative offset of ttf3's .igot.plt entry
#------------------------------------------------------------------------------
#------ thumb entry to abf3's .iplt entry
#------------------------------------------------------------------------------
a1d4: f43e af48 beq\.w 9068 <aaf1-0xf98>
- a1d8: 4c00 ldr r4, \[pc, #0\] ; \(a1dc <_thumb\+0xb8>\)
- a1da: 4c01 ldr r4, \[pc, #4\] ; \(a1e0 <_thumb\+0xbc>\)
+ a1d8: 4c00 ldr r4, \[pc, #0\] @ \(a1dc <_thumb\+0xb8>\)
+ a1da: 4c01 ldr r4, \[pc, #4\] @ \(a1e0 <_thumb\+0xbc>\)
#------------------------------------------------------------------------------
#------ GP-relative offset of abf3's .igot.plt entry
#------------------------------------------------------------------------------
#------ thumb entry to tbf3's .iplt entry
#------------------------------------------------------------------------------
a1ec: f43e af4c beq\.w 9088 <aaf1-0xf78>
- a1f0: 4c00 ldr r4, \[pc, #0\] ; \(a1f4 <_thumb\+0xd0>\)
- a1f2: 4c01 ldr r4, \[pc, #4\] ; \(a1f8 <_thumb\+0xd4>\)
+ a1f0: 4c00 ldr r4, \[pc, #0\] @ \(a1f4 <_thumb\+0xd0>\)
+ a1f2: 4c01 ldr r4, \[pc, #4\] @ \(a1f8 <_thumb\+0xd4>\)
#------------------------------------------------------------------------------
#------ GP-relative offset of tbf3's .igot.plt entry
#------------------------------------------------------------------------------
Disassembly of section \.plt:
00009000 <.plt>:
- 9000: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
- 9004: e59fe004 ldr lr, \[pc, #4\] ; 9010 <.*>
+ 9000: e52de004 push {lr} @ \(str lr, \[sp, #-4\]!\)
+ 9004: e59fe004 ldr lr, \[pc, #4\] @ 9010 <.*>
9008: e08fe00e add lr, pc, lr
900c: e5bef008 ldr pc, \[lr, #8\]!
#------------------------------------------------------------------------------
#------------------------------------------------------------------------------
00009014 <f2@plt>:
9014: e28fc600 add ip, pc, #0, 12
- 9018: e28cca07 add ip, ip, #28672 ; 0x7000
- 901c: e5bcfff0 ldr pc, \[ip, #4080\]! ; 0xff0
+ 9018: e28cca07 add ip, ip, #28672 @ 0x7000
+ 901c: e5bcfff0 ldr pc, \[ip, #4080\]! @ 0xff0
Disassembly of section \.iplt:
#------ f1's .iplt entry
#------------------------------------------------------------------------------
9020: e28fc600 add ip, pc, #0, 12
- 9024: e28cca07 add ip, ip, #28672 ; 0x7000
- 9028: e5bcffe8 ldr pc, \[ip, #4072\]! ; 0xfe8
+ 9024: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9028: e5bcffe8 ldr pc, \[ip, #4072\]! @ 0xfe8
0000902c <f3>:
902c: e28fc600 add ip, pc, #0, 12
- 9030: e28cca07 add ip, ip, #28672 ; 0x7000
- 9034: e5bcffe0 ldr pc, \[ip, #4064\]! ; 0xfe0
+ 9030: e28cca07 add ip, ip, #28672 @ 0x7000
+ 9034: e5bcffe0 ldr pc, \[ip, #4064\]! @ 0xfe0
Disassembly of section \.text:
0000a008 <_start>:
a008: eb0017fc bl 10000 <foo>
- a00c: e59f400c ldr r4, \[pc, #12\] ; a020 <_start\+0x18>
- a010: e59f400c ldr r4, \[pc, #12\] ; a024 <_start\+0x1c>
- a014: e59f400c ldr r4, \[pc, #12\] ; a028 <_start\+0x20>
- a018: e59f400c ldr r4, \[pc, #12\] ; a02c <_start\+0x24>
- a01c: e59f500c ldr r5, \[pc, #12\] ; a030 <_start\+0x28>
+ a00c: e59f400c ldr r4, \[pc, #12\] @ a020 <_start\+0x18>
+ a010: e59f400c ldr r4, \[pc, #12\] @ a024 <_start\+0x1c>
+ a014: e59f400c ldr r4, \[pc, #12\] @ a028 <_start\+0x20>
+ a018: e59f400c ldr r4, \[pc, #12\] @ a02c <_start\+0x24>
+ a01c: e59f500c ldr r5, \[pc, #12\] @ a030 <_start\+0x28>
#------------------------------------------------------------------------------
#------ foo
#------------------------------------------------------------------------------
#------ f1's .iplt entry
#------------------------------------------------------------------------------
a034: ebfffbf9 bl 9020 <f2@plt\+0xc>
- a038: e59f400c ldr r4, \[pc, #12\] ; a04c <_start\+0x44>
- a03c: e59f400c ldr r4, \[pc, #12\] ; a050 <_start\+0x48>
- a040: e59f400c ldr r4, \[pc, #12\] ; a054 <_start\+0x4c>
- a044: e59f400c ldr r4, \[pc, #12\] ; a058 <_start\+0x50>
- a048: e59f500c ldr r5, \[pc, #12\] ; a05c <_start\+0x54>
+ a038: e59f400c ldr r4, \[pc, #12\] @ a04c <_start\+0x44>
+ a03c: e59f400c ldr r4, \[pc, #12\] @ a050 <_start\+0x48>
+ a040: e59f400c ldr r4, \[pc, #12\] @ a054 <_start\+0x4c>
+ a044: e59f400c ldr r4, \[pc, #12\] @ a058 <_start\+0x50>
+ a048: e59f500c ldr r5, \[pc, #12\] @ a05c <_start\+0x54>
#------------------------------------------------------------------------------
#------ f1's .iplt entry
#------------------------------------------------------------------------------
#------ f2's .plt entry
#------------------------------------------------------------------------------
a060: ebfffbeb bl 9014 <f2@plt>
- a064: e59f400c ldr r4, \[pc, #12\] ; a078 <_start\+0x70>
- a068: e59f400c ldr r4, \[pc, #12\] ; a07c <_start\+0x74>
- a06c: e59f400c ldr r4, \[pc, #12\] ; a080 <_start\+0x78>
- a070: e59f400c ldr r4, \[pc, #12\] ; a084 <_start\+0x7c>
- a074: e59f500c ldr r5, \[pc, #12\] ; a088 <_start\+0x80>
+ a064: e59f400c ldr r4, \[pc, #12\] @ a078 <_start\+0x70>
+ a068: e59f400c ldr r4, \[pc, #12\] @ a07c <_start\+0x74>
+ a06c: e59f400c ldr r4, \[pc, #12\] @ a080 <_start\+0x78>
+ a070: e59f400c ldr r4, \[pc, #12\] @ a084 <_start\+0x7c>
+ a074: e59f500c ldr r5, \[pc, #12\] @ a088 <_start\+0x80>
#------------------------------------------------------------------------------
#------ f2's .plt entry
#------------------------------------------------------------------------------
#------------------------------------------------------------------------------
a088: 00006fa0 \.word 0x00006fa0
a08c: ebfffbe6 bl 902c <f3>
- a090: e59f400c ldr r4, \[pc, #12\] ; a0a4 <_start\+0x9c>
- a094: e59f400c ldr r4, \[pc, #12\] ; a0a8 <_start\+0xa0>
- a098: e59f400c ldr r4, \[pc, #12\] ; a0ac <_start\+0xa4>
- a09c: e59f400c ldr r4, \[pc, #12\] ; a0b0 <_start\+0xa8>
- a0a0: e59f500c ldr r5, \[pc, #12\] ; a0b4 <_start\+0xac>
+ a090: e59f400c ldr r4, \[pc, #12\] @ a0a4 <_start\+0x9c>
+ a094: e59f400c ldr r4, \[pc, #12\] @ a0a8 <_start\+0xa0>
+ a098: e59f400c ldr r4, \[pc, #12\] @ a0ac <_start\+0xa4>
+ a09c: e59f400c ldr r4, \[pc, #12\] @ a0b0 <_start\+0xa8>
+ a0a0: e59f500c ldr r5, \[pc, #12\] @ a0b4 <_start\+0xac>
#------------------------------------------------------------------------------
#------ f3
#------------------------------------------------------------------------------
...
001080.. <[^>]*>:
- 1080..: f85f f000 ldr.w pc, \[pc\] ; 10800c <__dest_veneer\+0x4>
+ 1080..: f85f f000 ldr.w pc, \[pc\] @ 10800c <__dest_veneer\+0x4>
1080..: 00008003 .word 0x00008003
...
000080.. <[^>]*>:
- 80..: f85f f000 ldr.w pc, \[pc\] ; 800c <__dest_veneer\+0x4>
+ 80..: f85f f000 ldr.w pc, \[pc\] @ 800c <__dest_veneer\+0x4>
80..: 00108005 .word 0x00108005
000080.. <[^>]*>:
80..: 4778 bx pc
80..: e7fd b.n .+ <.+>
- 80..: e59fc000 ldr ip, \[pc\] ; 80.. <__dest_veneer\+0xc>
+ 80..: e59fc000 ldr ip, \[pc\] @ 80.. <__dest_veneer\+0xc>
80..: e12fff1c bx ip
80..: 09000001 .word 0x09000001
.*: .*
.*: .* .word .*
.* <foo@plt>:
- .*: .* add ip, pc, #-268435456 ; 0xf0000000
+ .*: .* add ip, pc, #-268435456 @ 0xf0000000
.*: .* add ip, ip, #0, 12
.*: .* add ip, ip, #0, 20
- .*: .* ldr pc, [ip, #[0-9]*]! ; 0x.*
+ .*: .* ldr pc, [ip, #[0-9]*]! @ 0x.*
Disassembly of section .plt:
.* <.plt>:
- .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
- .*: e59fe004 ldr lr, \[pc, #4\] ; .* <.*>
+ .*: e52de004 push {lr} @ \(str lr, \[sp, #-4\]!\)
+ .*: e59fe004 ldr lr, \[pc, #4\] @ .* <.*>
.*: e08fe00e add lr, pc, lr
.*: e5bef008 ldr pc, \[lr, #8\]!
.*: .*
.* <lib_func2@plt>:
.*: e28fc6.* add ip, pc, #.*
- .*: e28cca.* add ip, ip, #.* ; 0x.*
+ .*: e28cca.* add ip, ip, #.* @ 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
.* <lib_func1@plt>:
.*: e28fc6.* add ip, pc, #.*
- .*: e28cca.* add ip, ip, #.* ; 0x.*
+ .*: e28cca.* add ip, ip, #.* @ 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
Disassembly of section .text:
.*: eb000004 bl .* <app_func>
.*: e89d6800 ldm sp, {fp, sp, lr}
.*: e12fff1e bx lr
- .*: e1a00000 nop ; \(mov r0, r0\)
- .*: e1a00000 nop ; \(mov r0, r0\)
- .*: e1a00000 nop ; \(mov r0, r0\)
+ .*: e1a00000 nop @ \(mov r0, r0\)
+ .*: e1a00000 nop @ \(mov r0, r0\)
+ .*: e1a00000 nop @ \(mov r0, r0\)
.* <app_func>:
.*: e1a0c00d mov ip, sp
.*: ebffffee bl .*
.*: e89d6800 ldm sp, {fp, sp, lr}
.*: e12fff1e bx lr
- .*: e1a00000 nop ; \(mov r0, r0\)
- .*: e1a00000 nop ; \(mov r0, r0\)
- .*: e1a00000 nop ; \(mov r0, r0\)
+ .*: e1a00000 nop @ \(mov r0, r0\)
+ .*: e1a00000 nop @ \(mov r0, r0\)
+ .*: e1a00000 nop @ \(mov r0, r0\)
.* <app_func2>:
.*: e12fff1e bx lr
- .*: e1a00000 nop ; \(mov r0, r0\)
- .*: e1a00000 nop ; \(mov r0, r0\)
- .*: e1a00000 nop ; \(mov r0, r0\)
+ .*: e1a00000 nop @ \(mov r0, r0\)
+ .*: e1a00000 nop @ \(mov r0, r0\)
+ .*: e1a00000 nop @ \(mov r0, r0\)
.* <app_tfunc>:
.*: b500 push {lr}
Disassembly of section .plt:
.* <.plt>:
- .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
- .*: e59fe004 ldr lr, \[pc, #4\] ; .* <.*>
+ .*: e52de004 push {lr} @ \(str lr, \[sp, #-4\]!\)
+ .*: e59fe004 ldr lr, \[pc, #4\] @ .* <.*>
.*: e08fe00e add lr, pc, lr
.*: e5bef008 ldr pc, \[lr, #8\]!
.*: .*
.*: 4778 bx pc
.*: e7fd b.n .+ <.+>
.*: e28fc6.* add ip, pc, #.*
- .*: e28cca.* add ip, ip, #.* ; 0x.*
+ .*: e28cca.* add ip, ip, #.* @ 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
.* <lib_func1@plt>:
.*: e28fc6.* add ip, pc, #.*
- .*: e28cca.* add ip, ip, #.* ; 0x.*
+ .*: e28cca.* add ip, ip, #.* @ 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
Disassembly of section .text:
.*: eb000004 bl .* <app_func>
.*: e89d6800 ldm sp, {fp, sp, lr}
.*: e12fff1e bx lr
- .*: e1a00000 nop ; \(mov r0, r0\)
- .*: e1a00000 nop ; \(mov r0, r0\)
- .*: e1a00000 nop ; \(mov r0, r0\)
+ .*: e1a00000 nop @ \(mov r0, r0\)
+ .*: e1a00000 nop @ \(mov r0, r0\)
+ .*: e1a00000 nop @ \(mov r0, r0\)
.* <app_func>:
.*: e1a0c00d mov ip, sp
.*: ebffff.. bl .*
.*: e89d6800 ldm sp, {fp, sp, lr}
.*: e12fff1e bx lr
- .*: e1a00000 nop ; \(mov r0, r0\)
- .*: e1a00000 nop ; \(mov r0, r0\)
- .*: e1a00000 nop ; \(mov r0, r0\)
+ .*: e1a00000 nop @ \(mov r0, r0\)
+ .*: e1a00000 nop @ \(mov r0, r0\)
+ .*: e1a00000 nop @ \(mov r0, r0\)
.* <app_func2>:
.*: e12fff1e bx lr
- .*: e1a00000 nop ; \(mov r0, r0\)
- .*: e1a00000 nop ; \(mov r0, r0\)
- .*: e1a00000 nop ; \(mov r0, r0\)
+ .*: e1a00000 nop @ \(mov r0, r0\)
+ .*: e1a00000 nop @ \(mov r0, r0\)
+ .*: e1a00000 nop @ \(mov r0, r0\)
.* <app_tfunc>:
.*: b500 push {lr}
Disassembly of section .plt:
.* <.plt>:
- .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
- .*: e59fe004 ldr lr, \[pc, #4\] ; .* <.*>
+ .*: e52de004 push {lr} @ \(str lr, \[sp, #-4\]!\)
+ .*: e59fe004 ldr lr, \[pc, #4\] @ .* <.*>
.*: e08fe00e add lr, pc, lr
.*: e5bef008 ldr pc, \[lr, #8\]!
.*: .*
.* <app_func2@plt>:
.*: e28fc6.* add ip, pc, #.*
- .*: e28cca.* add ip, ip, #.* ; 0x.*
+ .*: e28cca.* add ip, ip, #.* @ 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
Disassembly of section .text:
.*: ebfffff. bl .* <app_func2@plt>
.*: e89d6800 ldm sp, {fp, sp, lr}
.*: e12fff1e bx lr
- .*: e1a00000 nop ; \(mov r0, r0\)
- .*: e1a00000 nop ; \(mov r0, r0\)
- .*: e1a00000 nop ; \(mov r0, r0\)
+ .*: e1a00000 nop @ \(mov r0, r0\)
+ .*: e1a00000 nop @ \(mov r0, r0\)
+ .*: e1a00000 nop @ \(mov r0, r0\)
.* <lib_func2>:
.*: 4770 bx lr
Disassembly of section .text:
00008000 <[^>]*>:
- 8000: e3080013 movw r0, #32787 ; 0x8013
+ 8000: e3080013 movw r0, #32787 @ 0x8013
8004: e3400000 movt r0, #0
00008008 <[^>]*>:
- 8008: f248 0013 movw r0, #32787 ; 0x8013
+ 8008: f248 0013 movw r0, #32787 @ 0x8013
800c: f2c0 0000 movt r0, #0
Disassembly of section .raml:
1fff0000 \<code1\>:
-1fff0000: e1a00000 nop ; \(mov r0, r0\)
-1fff0004: e1a00000 nop ; \(mov r0, r0\)
+1fff0000: e1a00000 nop @ \(mov r0, r0\)
+1fff0004: e1a00000 nop @ \(mov r0, r0\)
1fff0008: ebffffff bl 1fff000c \<code2\>
1fff000c \<code2\>:
-1fff000c: e1a00000 nop ; \(mov r0, r0\)
-1fff0010: e1a00000 nop ; \(mov r0, r0\)
+1fff000c: e1a00000 nop @ \(mov r0, r0\)
+1fff0010: e1a00000 nop @ \(mov r0, r0\)
1fff0014: eb003ff9 bl 20000000 \<code3\>
Disassembly of section .ramu:
20000000 \<code3\>:
-20000000: e1a00000 nop ; \(mov r0, r0\)
+20000000: e1a00000 nop @ \(mov r0, r0\)
20000004: eb00fffd bl 20040000 \<code4\>
Disassembly of section .ramz:
Disassembly of section .raml:
1fff0000 \<code1\>:
-1fff0000: e1a00000 nop ; \(mov r0, r0\)
-1fff0004: e1a00000 nop ; \(mov r0, r0\)
+1fff0000: e1a00000 nop @ \(mov r0, r0\)
+1fff0004: e1a00000 nop @ \(mov r0, r0\)
1fff0008: ebffffff bl 1fff000c \<code2\>
1fff000c \<code2\>:
-1fff000c: e1a00000 nop ; \(mov r0, r0\)
-1fff0010: e1a00000 nop ; \(mov r0, r0\)
+1fff000c: e1a00000 nop @ \(mov r0, r0\)
+1fff0010: e1a00000 nop @ \(mov r0, r0\)
1fff0014: eb003ff9 bl 20000000 \<code3\>
Disassembly of section .ramu:
20000000 \<code3\>:
-20000000: e1a00000 nop ; \(mov r0, r0\)
+20000000: e1a00000 nop @ \(mov r0, r0\)
20000004: ebffffff bl 20000008 \<__code4_veneer\>
20000008 \<__code4_veneer\>:
-20000008: e51ff004 ldr pc, \[pc, #-4\] ; 2000000c \<__code4_veneer\+0x4\>
+20000008: e51ff004 ldr pc, \[pc, #-4\] @ 2000000c \<__code4_veneer\+0x4\>
2000000c: 30040000 .word 0x30040000
Disassembly of section .ramz:
Disassembly of section .raml:
1fff0000 \<code1\>:
-1fff0000: e1a00000 nop ; \(mov r0, r0\)
-1fff0004: e1a00000 nop ; \(mov r0, r0\)
+1fff0000: e1a00000 nop @ \(mov r0, r0\)
+1fff0004: e1a00000 nop @ \(mov r0, r0\)
1fff0008: eb003ffc bl 20000000 \<code2\>
Disassembly of section .ramu:
20000000 \<code2\>:
-20000000: e1a00000 nop ; \(mov r0, r0\)
-20000004: e1a00000 nop ; \(mov r0, r0\)
+20000000: e1a00000 nop @ \(mov r0, r0\)
+20000004: e1a00000 nop @ \(mov r0, r0\)
20000008: ebffffff bl 2000000c \<code3\>
2000000c \<code3\>:
-2000000c: e1a00000 nop ; \(mov r0, r0\)
+2000000c: e1a00000 nop @ \(mov r0, r0\)
20000010: eb00fffa bl 20040000 \<code4\>
Disassembly of section .ramz:
Disassembly of section .raml:
1fff0000 \<code1\>:
-1fff0000: e1a00000 nop ; \(mov r0, r0\)
-1fff0004: e1a00000 nop ; \(mov r0, r0\)
+1fff0000: e1a00000 nop @ \(mov r0, r0\)
+1fff0004: e1a00000 nop @ \(mov r0, r0\)
1fff0008: ebffffff bl 1fff000c \<code2\>
1fff000c \<code2\>:
-1fff000c: e1a00000 nop ; \(mov r0, r0\)
-1fff0010: e1a00000 nop ; \(mov r0, r0\)
+1fff000c: e1a00000 nop @ \(mov r0, r0\)
+1fff0010: e1a00000 nop @ \(mov r0, r0\)
1fff0014: ebffffff bl 1fff0018 \<code3\>
1fff0018 \<code3\>:
-1fff0018: e1a00000 nop ; \(mov r0, r0\)
+1fff0018: e1a00000 nop @ \(mov r0, r0\)
1fff001c: ebffffff bl 1fff0020 \<__code4_veneer\>
1fff0020 \<__code4_veneer\>:
-1fff0020: e51ff004 ldr pc, \[pc, #-4\] ; 1fff0024 \<__code4_veneer\+0x4\>
+1fff0020: e51ff004 ldr pc, \[pc, #-4\] @ 1fff0024 \<__code4_veneer\+0x4\>
1fff0024: 40040000 .word 0x40040000
Disassembly of section .ramz:
#ld:-EL --fix-stm32l4xx-629360 -Ttext=0x80000
#objdump: -dr --prefix-addresses --show-raw-insn
#name: STM32L4XX erratum : LDM cannot be patched when LDM is too far from veneer section
-#warning: .*cannot create STM32L4XX veneer; jump out of range by 24 bytes; cannot encode branch instruction.*
+#warning: .*cannot create STM32L4XX veneer@ jump out of range by 24 bytes; cannot encode branch instruction.*
# Test the `LDM*' instructions when too far from the veneer section
# They cannot, thus should not, be patched
80ae: de00 udf #0
000080b0 <__stm32l4xx_veneer_b>:
- 80b0: f1a9 0928 sub\.w r9, r9, #40 ; 0x28
+ 80b0: f1a9 0928 sub\.w r9, r9, #40 @ 0x28
80b4: e8b9 007e ldmia\.w r9!, {r1, r2, r3, r4, r5, r6}
80b8: e899 8380 ldmia\.w r9, {r7, r8, r9, pc}
80bc: f7f0 a000 udf\.w #0
000080c0 <__stm32l4xx_veneer_c>:
- 80c0: f1a1 0728 sub\.w r7, r1, #40 ; 0x28
+ 80c0: f1a1 0728 sub\.w r7, r1, #40 @ 0x28
80c4: e8b7 007e ldmia\.w r7!, {r1, r2, r3, r4, r5, r6}
80c8: e897 8380 ldmia\.w r7, {r7, r8, r9, pc}
80cc: f7f0 a000 udf\.w #0
000080d0 <__stm32l4xx_veneer_d>:
- 80d0: f1a0 0728 sub\.w r7, r0, #40 ; 0x28
+ 80d0: f1a0 0728 sub\.w r7, r0, #40 @ 0x28
80d4: e8b7 007e ldmia\.w r7!, {r1, r2, r3, r4, r5, r6}
80d8: e897 8380 ldmia\.w r7, {r7, r8, r9, pc}
80dc: f7f0 a000 udf\.w #0
80ec: f7f0 a000 udf\.w #0
000080f0 <__stm32l4xx_veneer_f>:
- 80f0: f1a0 0028 sub\.w r0, r0, #40 ; 0x28
+ 80f0: f1a0 0028 sub\.w r0, r0, #40 @ 0x28
80f4: 4607 mov r7, r0
80f6: e8b7 007e ldmia\.w r7!, {r1, r2, r3, r4, r5, r6}
80fa: e897 8380 ldmia\.w r7, {r7, r8, r9, pc}
8004: ecba 5b08 vldmia sl!, {d5-d8}
8008: ecba 9b08 vldmia sl!, {d9-d12}
800c: ecba db06 vldmia sl!, {d13-d15}
- 8010: f1aa 0a78 sub\.w sl, sl, #120 ; 0x78
+ 8010: f1aa 0a78 sub\.w sl, sl, #120 @ 0x78
8014: f000 b826 b\.w 8064 <__stm32l4xx_veneer_0_r>
00008018 <__stm32l4xx_veneer_1>:
8004: ecf9 4a08 vldmia r9!, {s9-s16}
8008: ecf9 8a08 vldmia r9!, {s17-s24}
800c: ecf9 ca07 vldmia r9!, {s25-s31}
- 8010: f1a9 097c sub\.w r9, r9, #124 ; 0x7c
+ 8010: f1a9 097c sub\.w r9, r9, #124 @ 0x7c
8014: f000 b826 b\.w 8064 <__stm32l4xx_veneer_0_r>
00008018 <__stm32l4xx_veneer_1>:
00000110 <\.plt>:
110: b500 push {lr}
- 112: f8df e008 ldr.w lr, \[pc, #8\] ; 11c <\.plt\+0xc>
+ 112: f8df e008 ldr.w lr, \[pc, #8\] @ 11c <\.plt\+0xc>
116: 44fe add lr, pc
118: f85e ff08 ldr.w pc, \[lr, #8\]!
11c: 000100(.+) \.word 0x000100\1
00000120 <foo@plt>:
- 120: f240 0c.+ movw ip, #[0-9]+ ; 0x.+
+ 120: f240 0c.+ movw ip, #[0-9]+ @ 0x.+
124: f2c0 0c01 movt ip, #1
128: 44fc add ip, pc
12a: f8dc f000 ldr.w pc, \[ip\]
00008000 <[^>]*>:
8000: 3012 adds r0, #18
- 8002: 3134 adds r1, #52 ; 0x34
- 8004: 3280 adds r2, #128 ; 0x80
+ 8002: 3134 adds r1, #52 @ 0x34
+ 8004: 3280 adds r2, #128 @ 0x80
8006: 3301 adds r3, #1
8008: 3401 adds r4, #1
800a: 3500 adds r5, #0
8010: 3012 adds r0, #18
8012: 3100 adds r1, #0
8014: 3200 adds r2, #0
- 8016: 33ca adds r3, #202 ; 0xca
+ 8016: 33ca adds r3, #202 @ 0xca
8018: 3700 adds r7, #0
- 801a: 3634 adds r6, #52 ; 0x34
- 801c: 3581 adds r5, #129 ; 0x81
- 801e: 3423 adds r4, #35 ; 0x23
+ 801a: 3634 adds r6, #52 @ 0x34
+ 801c: 3581 adds r5, #129 @ 0x81
+ 801e: 3423 adds r4, #35 @ 0x23
00008020 <[^>]*>:
8020: 01 .byte 0x01
00008000 <[^>]*>:
8000: 2012 movs r0, #18
- 8002: 2134 movs r1, #52 ; 0x34
- 8004: 2280 movs r2, #128 ; 0x80
+ 8002: 2134 movs r1, #52 @ 0x34
+ 8004: 2280 movs r2, #128 @ 0x80
8006: 2301 movs r3, #1
8008: 2401 movs r4, #1
800a: 2500 movs r5, #0
00008010 <[^>]*>:
8010: 2012 movs r0, #18
8012: 2100 movs r1, #0
- 8014: 2281 movs r2, #129 ; 0x81
+ 8014: 2281 movs r2, #129 @ 0x81
8016: 2320 movs r3, #32
8018: 2700 movs r7, #0
801a: 2600 movs r6, #0
- 801c: 2581 movs r5, #129 ; 0x81
- 801e: 2422 movs r4, #34 ; 0x22
+ 801c: 2581 movs r5, #129 @ 0x81
+ 801e: 2422 movs r4, #34 @ 0x22
00008020 <[^>]*>:
8020: 01 .byte 0x01
\.\.\.
00001008 <__bar_veneer>:
- 1008: e51ff004 ldr pc, \[pc, #-4\] ; 100c <__bar_veneer\+0x4>
+ 1008: e51ff004 ldr pc, \[pc, #-4\] @ 100c <__bar_veneer\+0x4>
100c: 0100100d .word 0x0100100d
Disassembly of section .foo:
\.\.\.
00001008 <__bar_veneer>:
- 1008: e51ff004 ldr pc, \[pc, #-4\] ; 100c <__bar_veneer\+0x4>
+ 1008: e51ff004 ldr pc, \[pc, #-4\] @ 100c <__bar_veneer\+0x4>
100c: 0100100d .word 0x0100100d
Disassembly of section .foo:
Disassembly of section .text:
00008[0-9a-f]+ <foo>:
- 8[0-9a-f]+: e1a00000 nop ; \(mov r0, r0\)
- 8[0-9a-f]+: e1a00000 nop ; \(mov r0, r0\)
+ 8[0-9a-f]+: e1a00000 nop @ \(mov r0, r0\)
+ 8[0-9a-f]+: e1a00000 nop @ \(mov r0, r0\)
8[0-9a-f]+: e1a0f00e mov pc, lr
8[0-9a-f]+: 000080bc .word 0x000080bc
8[0-9a-f]+: 000080b4 .word 0x000080b4
Disassembly of section .text:
00008000 <foo>:
- 8000: e59f0004 ldr r0, \[pc, #4\] ; 800c <foo\+0xc>
+ 8000: e59f0004 ldr r0, \[pc, #4\] @ 800c <foo\+0xc>
8004: e79f0000 ldr r0, \[pc, r0\]
- 8008: e1a00000 nop ; .*
+ 8008: e1a00000 nop @ .*
800c: 00008138 .word 0x00008138
- 8010: e59f0004 ldr r0, \[pc, #4\] ; 801c <foo\+0x1c>
+ 8010: e59f0004 ldr r0, \[pc, #4\] @ 801c <foo\+0x1c>
8014: e79f0000 ldr r0, \[pc, r0\]
- 8018: e1a00000 nop ; .*
+ 8018: e1a00000 nop @ .*
801c: 00008128 .word 0x00008128
- 8020: e59f0004 ldr r0, \[pc, #4\] ; 802c <foo\+0x2c>
- 8024: e1a00000 nop ; .*
- 8028: e1a00000 nop ; .*
+ 8020: e59f0004 ldr r0, \[pc, #4\] @ 802c <foo\+0x2c>
+ 8024: e1a00000 nop @ .*
+ 8028: e1a00000 nop @ .*
802c: 0000000c .word 0x0000000c
- 8030: e59f0004 ldr r0, \[pc, #4\] ; 803c <foo\+0x3c>
- 8034: e1a00000 nop ; .*
- 8038: e1a00000 nop ; .*
+ 8030: e59f0004 ldr r0, \[pc, #4\] @ 803c <foo\+0x3c>
+ 8034: e1a00000 nop @ .*
+ 8038: e1a00000 nop @ .*
803c: 0000000c .word 0x0000000c
- 8040: e59f000c ldr r0, \[pc, #12\] ; 8054 <foo\+0x54>
+ 8040: e59f000c ldr r0, \[pc, #12\] @ 8054 <foo\+0x54>
8044: e08f0000 add r0, pc, r0
8048: e5901000 ldr r1, \[r0\]
804c: e1a00001 mov r0, r1
- 8050: e1a00000 nop ; .*
+ 8050: e1a00000 nop @ .*
8054: 000080f8 .word 0x000080f8
- 8058: e59f000c ldr r0, \[pc, #12\] ; 806c <foo\+0x6c>
+ 8058: e59f000c ldr r0, \[pc, #12\] @ 806c <foo\+0x6c>
805c: e08f0000 add r0, pc, r0
8060: e5901000 ldr r1, \[r0\]
8064: e1a00001 mov r0, r1
- 8068: e1a00000 nop ; .*
+ 8068: e1a00000 nop @ .*
806c: 000080e0 .word 0x000080e0
- 8070: e59f000c ldr r0, \[pc, #12\] ; 8084 <foo\+0x84>
- 8074: e1a00000 nop ; .*
- 8078: e1a00000 nop ; .*
- 807c: e1a00000 nop ; .*
- 8080: e1a00000 nop ; .*
+ 8070: e59f000c ldr r0, \[pc, #12\] @ 8084 <foo\+0x84>
+ 8074: e1a00000 nop @ .*
+ 8078: e1a00000 nop @ .*
+ 807c: e1a00000 nop @ .*
+ 8080: e1a00000 nop @ .*
8084: 0000000c .word 0x0000000c
- 8088: e59f000c ldr r0, \[pc, #12\] ; 809c <foo\+0x9c>
- 808c: e1a00000 nop ; .*
- 8090: e1a00000 nop ; .*
- 8094: e1a00000 nop ; .*
- 8098: e1a00000 nop ; .*
+ 8088: e59f000c ldr r0, \[pc, #12\] @ 809c <foo\+0x9c>
+ 808c: e1a00000 nop @ .*
+ 8090: e1a00000 nop @ .*
+ 8094: e1a00000 nop @ .*
+ 8098: e1a00000 nop @ .*
809c: 0000000c .word 0x0000000c
000080a0 <bar>:
- 80a0: 4801 ldr r0, \[pc, #4\] ; \(80a8 <bar\+0x8>\)
+ 80a0: 4801 ldr r0, \[pc, #4\] @ \(80a8 <bar\+0x8>\)
80a2: 4478 add r0, pc
80a4: 6800 ldr r0, \[r0, #0\]
- 80a6: 46c0 nop ; .*
+ 80a6: 46c0 nop @ .*
80a8: 0000809e .word 0x0000809e
- 80ac: 4801 ldr r0, \[pc, #4\] ; \(80b4 <bar\+0x14>\)
+ 80ac: 4801 ldr r0, \[pc, #4\] @ \(80b4 <bar\+0x14>\)
80ae: 4478 add r0, pc
80b0: 6800 ldr r0, \[r0, #0\]
- 80b2: 46c0 nop ; .*
+ 80b2: 46c0 nop @ .*
80b4: 00008092 .word 0x00008092
- 80b8: 4801 ldr r0, \[pc, #4\] ; \(80c0 <bar\+0x20>\)
+ 80b8: 4801 ldr r0, \[pc, #4\] @ \(80c0 <bar\+0x20>\)
80ba: 4478 add r0, pc
80bc: 6800 ldr r0, \[r0, #0\]
- 80be: 46c0 nop ; .*
+ 80be: 46c0 nop @ .*
80c0: 0000808a .word 0x0000808a
- 80c4: 4801 ldr r0, \[pc, #4\] ; \(80cc <bar\+0x2c>\)
- 80c6: 46c0 nop ; .*
- 80c8: 46c0 nop ; .*
- 80ca: 46c0 nop ; .*
+ 80c4: 4801 ldr r0, \[pc, #4\] @ \(80cc <bar\+0x2c>\)
+ 80c6: 46c0 nop @ .*
+ 80c8: 46c0 nop @ .*
+ 80ca: 46c0 nop @ .*
80cc: 0000000c .word 0x0000000c
- 80d0: 4801 ldr r0, \[pc, #4\] ; \(80d8 <bar\+0x38>\)
+ 80d0: 4801 ldr r0, \[pc, #4\] @ \(80d8 <bar\+0x38>\)
80d2: bf00 nop
80d4: bf00 nop
- 80d6: 46c0 nop ; .*
+ 80d6: 46c0 nop @ .*
80d8: 0000000c .word 0x0000000c
- 80dc: 4801 ldr r0, \[pc, #4\] ; \(80e4 <bar\+0x44>\)
+ 80dc: 4801 ldr r0, \[pc, #4\] @ \(80e4 <bar\+0x44>\)
80de: bf00 nop
80e0: bf00 nop
- 80e2: 46c0 nop ; .*
+ 80e2: 46c0 nop @ .*
80e4: 00000014 .word 0x00000014
- 80e8: 4802 ldr r0, \[pc, #8\] ; \(80f4 <bar\+0x54>\)
+ 80e8: 4802 ldr r0, \[pc, #8\] @ \(80f4 <bar\+0x54>\)
80ea: 4478 add r0, pc
80ec: 6801 ldr r1, \[r0, #0\]
80ee: 1c08 adds r0, r1, #0
- 80f0: 46c0 nop ; .*
- 80f2: 46c0 nop ; .*
+ 80f0: 46c0 nop @ .*
+ 80f2: 46c0 nop @ .*
80f4: 00008056 .word 0x00008056
- 80f8: 4802 ldr r0, \[pc, #8\] ; \(8104 <bar\+0x64>\)
+ 80f8: 4802 ldr r0, \[pc, #8\] @ \(8104 <bar\+0x64>\)
80fa: 4478 add r0, pc
80fc: 6801 ldr r1, \[r0, #0\]
80fe: 4608 mov r0, r1
- 8100: 46c0 nop ; .*
- 8102: 46c0 nop ; .*
+ 8100: 46c0 nop @ .*
+ 8102: 46c0 nop @ .*
8104: 00008046 .word 0x00008046
- 8108: 4802 ldr r0, \[pc, #8\] ; \(8114 <bar\+0x74>\)
- 810a: 46c0 nop ; .*
- 810c: 46c0 nop ; .*
- 810e: 46c0 nop ; .*
- 8110: 46c0 nop ; .*
- 8112: 46c0 nop ; .*
+ 8108: 4802 ldr r0, \[pc, #8\] @ \(8114 <bar\+0x74>\)
+ 810a: 46c0 nop @ .*
+ 810c: 46c0 nop @ .*
+ 810e: 46c0 nop @ .*
+ 8110: 46c0 nop @ .*
+ 8112: 46c0 nop @ .*
8114: 0000000c .word 0x0000000c
- 8118: 4802 ldr r0, \[pc, #8\] ; \(8124 <bar\+0x84>\)
- 811a: 46c0 nop ; .*
- 811c: 46c0 nop ; .*
- 811e: 46c0 nop ; .*
- 8120: 46c0 nop ; .*
- 8122: 46c0 nop ; .*
+ 8118: 4802 ldr r0, \[pc, #8\] @ \(8124 <bar\+0x84>\)
+ 811a: 46c0 nop @ .*
+ 811c: 46c0 nop @ .*
+ 811e: 46c0 nop @ .*
+ 8120: 46c0 nop @ .*
+ 8122: 46c0 nop @ .*
8124: 0000000c .word 0x0000000c
Disassembly of section .text:
00008000 <foo>:
- 8000: e59f0004 ldr r0, \[pc, #4\] ; 800c <foo\+0xc>
+ 8000: e59f0004 ldr r0, \[pc, #4\] @ 800c <foo\+0xc>
8004: e79f0000 ldr r0, \[pc, r0\]
8008: e320f000 nop \{0\}
800c: 00008138 .word 0x00008138
- 8010: e59f0004 ldr r0, \[pc, #4\] ; 801c <foo\+0x1c>
+ 8010: e59f0004 ldr r0, \[pc, #4\] @ 801c <foo\+0x1c>
8014: e79f0000 ldr r0, \[pc, r0\]
8018: e320f000 nop \{0\}
801c: 00008128 .word 0x00008128
- 8020: e59f0004 ldr r0, \[pc, #4\] ; 802c <foo\+0x2c>
+ 8020: e59f0004 ldr r0, \[pc, #4\] @ 802c <foo\+0x2c>
8024: e320f000 nop \{0\}
8028: e320f000 nop \{0\}
802c: 0000000c .word 0x0000000c
- 8030: e59f0004 ldr r0, \[pc, #4\] ; 803c <foo\+0x3c>
- 8034: e1a00000 nop ; .*
+ 8030: e59f0004 ldr r0, \[pc, #4\] @ 803c <foo\+0x3c>
+ 8034: e1a00000 nop @ .*
8038: e320f000 nop \{0\}
803c: 0000000c .word 0x0000000c
- 8040: e59f000c ldr r0, \[pc, #12\] ; 8054 <foo\+0x54>
+ 8040: e59f000c ldr r0, \[pc, #12\] @ 8054 <foo\+0x54>
8044: e08f0000 add r0, pc, r0
8048: e5901000 ldr r1, \[r0\]
804c: e1a00001 mov r0, r1
8050: e320f000 nop \{0\}
8054: 000080f8 .word 0x000080f8
- 8058: e59f000c ldr r0, \[pc, #12\] ; 806c <foo\+0x6c>
+ 8058: e59f000c ldr r0, \[pc, #12\] @ 806c <foo\+0x6c>
805c: e08f0000 add r0, pc, r0
8060: e5901000 ldr r1, \[r0\]
8064: e1a00001 mov r0, r1
8068: e320f000 nop \{0\}
806c: 000080e0 .word 0x000080e0
- 8070: e59f000c ldr r0, \[pc, #12\] ; 8084 <foo\+0x84>
+ 8070: e59f000c ldr r0, \[pc, #12\] @ 8084 <foo\+0x84>
8074: e320f000 nop \{0\}
8078: e320f000 nop \{0\}
807c: e320f000 nop \{0\}
8080: e320f000 nop \{0\}
8084: 0000000c .word 0x0000000c
- 8088: e59f000c ldr r0, \[pc, #12\] ; 809c <foo\+0x9c>
- 808c: e1a00000 nop ; .*
- 8090: e1a00000 nop ; .*
- 8094: e1a00000 nop ; .*
+ 8088: e59f000c ldr r0, \[pc, #12\] @ 809c <foo\+0x9c>
+ 808c: e1a00000 nop @ .*
+ 8090: e1a00000 nop @ .*
+ 8094: e1a00000 nop @ .*
8098: e320f000 nop \{0\}
809c: 0000000c .word 0x0000000c
000080a0 <bar>:
- 80a0: 4801 ldr r0, \[pc, #4\] ; \(80a8 <bar\+0x8>\)
+ 80a0: 4801 ldr r0, \[pc, #4\] @ \(80a8 <bar\+0x8>\)
80a2: 4478 add r0, pc
80a4: 6800 ldr r0, \[r0, #0\]
- 80a6: 46c0 nop ; .*
+ 80a6: 46c0 nop @ .*
80a8: 0000809e .word 0x0000809e
- 80ac: 4801 ldr r0, \[pc, #4\] ; \(80b4 <bar\+0x14>\)
+ 80ac: 4801 ldr r0, \[pc, #4\] @ \(80b4 <bar\+0x14>\)
80ae: 4478 add r0, pc
80b0: 6800 ldr r0, \[r0, #0\]
- 80b2: 46c0 nop ; \(mov r8, r8\)
+ 80b2: 46c0 nop @ \(mov r8, r8\)
80b4: 00008092 .word 0x00008092
- 80b8: 4801 ldr r0, \[pc, #4\] ; \(80c0 <bar\+0x20>\)
+ 80b8: 4801 ldr r0, \[pc, #4\] @ \(80c0 <bar\+0x20>\)
80ba: 4478 add r0, pc
80bc: 6800 ldr r0, \[r0, #0\]
- 80be: 46c0 nop ; \(mov r8, r8\)
+ 80be: 46c0 nop @ \(mov r8, r8\)
80c0: 0000808a .word 0x0000808a
- 80c4: 4801 ldr r0, \[pc, #4\] ; \(80cc <bar\+0x2c>\)
- 80c6: 46c0 nop ; \(mov r8, r8\)
- 80c8: 46c0 nop ; \(mov r8, r8\)
+ 80c4: 4801 ldr r0, \[pc, #4\] @ \(80cc <bar\+0x2c>\)
+ 80c6: 46c0 nop @ \(mov r8, r8\)
+ 80c8: 46c0 nop @ \(mov r8, r8\)
80ca: bf00 nop
80cc: 0000000c .word 0x0000000c
- 80d0: 4801 ldr r0, \[pc, #4\] ; \(80d8 <bar\+0x38>\)
+ 80d0: 4801 ldr r0, \[pc, #4\] @ \(80d8 <bar\+0x38>\)
80d2: (f3af 8000)|(bf00 ) nop(.w)?
#...
- 80d6: 46c0 nop ; \(mov r8, r8\)
+ 80d6: 46c0 nop @ \(mov r8, r8\)
80d8: 0000000c .word 0x0000000c
- 80dc: 4801 ldr r0, \[pc, #4\] ; \(80e4 <bar\+0x44>\)
+ 80dc: 4801 ldr r0, \[pc, #4\] @ \(80e4 <bar\+0x44>\)
80de: (f3af 8000)|(bf00 ) nop(.w)?
#...
- 80e2: 46c0 nop ; \(mov r8, r8\)
+ 80e2: 46c0 nop @ \(mov r8, r8\)
80e4: 00000014 .word 0x00000014
- 80e8: 4802 ldr r0, \[pc, #8\] ; \(80f4 <bar\+0x54>\)
+ 80e8: 4802 ldr r0, \[pc, #8\] @ \(80f4 <bar\+0x54>\)
80ea: 4478 add r0, pc
80ec: 6801 ldr r1, \[r0, #0\]
80ee: 1c08 adds r0, r1, #0
- 80f0: 46c0 nop ; \(mov r8, r8\)
+ 80f0: 46c0 nop @ \(mov r8, r8\)
80f2: bf00 nop
80f4: 00008056 .word 0x00008056
- 80f8: 4802 ldr r0, \[pc, #8\] ; \(8104 <bar\+0x64>\)
+ 80f8: 4802 ldr r0, \[pc, #8\] @ \(8104 <bar\+0x64>\)
80fa: 4478 add r0, pc
80fc: 6801 ldr r1, \[r0, #0\]
80fe: 4608 mov r0, r1
- 8100: 46c0 nop ; \(mov r8, r8\)
+ 8100: 46c0 nop @ \(mov r8, r8\)
8102: bf00 nop
8104: 00008046 .word 0x00008046
- 8108: 4802 ldr r0, \[pc, #8\] ; \(8114 <bar\+0x74>\)
- 810a: 46c0 nop ; \(mov r8, r8\)
- 810c: 46c0 nop ; \(mov r8, r8\)
- 810e: 46c0 nop ; \(mov r8, r8\)
- 8110: 46c0 nop ; \(mov r8, r8\)
+ 8108: 4802 ldr r0, \[pc, #8\] @ \(8114 <bar\+0x74>\)
+ 810a: 46c0 nop @ \(mov r8, r8\)
+ 810c: 46c0 nop @ \(mov r8, r8\)
+ 810e: 46c0 nop @ \(mov r8, r8\)
+ 8110: 46c0 nop @ \(mov r8, r8\)
8112: bf00 nop
8114: 0000000c .word 0x0000000c
- 8118: 4802 ldr r0, \[pc, #8\] ; \(8124 <bar\+0x84>\)
- 811a: 46c0 nop ; \(mov r8, r8\)
- 811c: 46c0 nop ; \(mov r8, r8\)
- 811e: 46c0 nop ; \(mov r8, r8\)
- 8120: 46c0 nop ; \(mov r8, r8\)
+ 8118: 4802 ldr r0, \[pc, #8\] @ \(8124 <bar\+0x84>\)
+ 811a: 46c0 nop @ \(mov r8, r8\)
+ 811c: 46c0 nop @ \(mov r8, r8\)
+ 811e: 46c0 nop @ \(mov r8, r8\)
+ 8120: 46c0 nop @ \(mov r8, r8\)
8122: bf00 nop
8124: 0000000c .word 0x0000000c
Disassembly of section .text:
00008000 <foo>:
- 8000: e59f0004 ldr r0, \[pc, #4\] ; 800c <foo\+0xc>
+ 8000: e59f0004 ldr r0, \[pc, #4\] @ 800c <foo\+0xc>
8004: e79f0000 ldr r0, \[pc, r0\]
8008: e320f000 nop \{0\}
800c: 00008138 .word 0x00008138
- 8010: e59f0004 ldr r0, \[pc, #4\] ; 801c <foo\+0x1c>
+ 8010: e59f0004 ldr r0, \[pc, #4\] @ 801c <foo\+0x1c>
8014: e79f0000 ldr r0, \[pc, r0\]
8018: e320f000 nop \{0\}
801c: 00008128 .word 0x00008128
- 8020: e59f0004 ldr r0, \[pc, #4\] ; 802c <foo\+0x2c>
+ 8020: e59f0004 ldr r0, \[pc, #4\] @ 802c <foo\+0x2c>
8024: e320f000 nop \{0\}
8028: e320f000 nop \{0\}
802c: 0000000c .word 0x0000000c
- 8030: e59f0004 ldr r0, \[pc, #4\] ; 803c <foo\+0x3c>
- 8034: e1a00000 nop ; .*
+ 8030: e59f0004 ldr r0, \[pc, #4\] @ 803c <foo\+0x3c>
+ 8034: e1a00000 nop @ .*
8038: e320f000 nop \{0\}
803c: 0000000c .word 0x0000000c
- 8040: e59f000c ldr r0, \[pc, #12\] ; 8054 <foo\+0x54>
+ 8040: e59f000c ldr r0, \[pc, #12\] @ 8054 <foo\+0x54>
8044: e08f0000 add r0, pc, r0
8048: e5901000 ldr r1, \[r0\]
804c: e1a00001 mov r0, r1
8050: e320f000 nop \{0\}
8054: 000080f8 .word 0x000080f8
- 8058: e59f000c ldr r0, \[pc, #12\] ; 806c <foo\+0x6c>
+ 8058: e59f000c ldr r0, \[pc, #12\] @ 806c <foo\+0x6c>
805c: e08f0000 add r0, pc, r0
8060: e5901000 ldr r1, \[r0\]
8064: e1a00001 mov r0, r1
8068: e320f000 nop \{0\}
806c: 000080e0 .word 0x000080e0
- 8070: e59f000c ldr r0, \[pc, #12\] ; 8084 <foo\+0x84>
+ 8070: e59f000c ldr r0, \[pc, #12\] @ 8084 <foo\+0x84>
8074: e320f000 nop \{0\}
8078: e320f000 nop \{0\}
807c: e320f000 nop \{0\}
8080: e320f000 nop \{0\}
8084: 0000000c .word 0x0000000c
- 8088: e59f000c ldr r0, \[pc, #12\] ; 809c <foo\+0x9c>
- 808c: e1a00000 nop ; .*
- 8090: e1a00000 nop ; .*
- 8094: e1a00000 nop ; .*
+ 8088: e59f000c ldr r0, \[pc, #12\] @ 809c <foo\+0x9c>
+ 808c: e1a00000 nop @ .*
+ 8090: e1a00000 nop @ .*
+ 8094: e1a00000 nop @ .*
8098: e320f000 nop \{0\}
809c: 0000000c .word 0x0000000c
000080a0 <bar>:
- 80a0: 4801 ldr r0, \[pc, #4\] ; \(80a8 <bar\+0x8>\)
+ 80a0: 4801 ldr r0, \[pc, #4\] @ \(80a8 <bar\+0x8>\)
80a2: 4478 add r0, pc
80a4: 6800 ldr r0, \[r0, #0\]
- 80a6: 46c0 nop ; .*
+ 80a6: 46c0 nop @ .*
80a8: 0000809e .word 0x0000809e
- 80ac: 4801 ldr r0, \[pc, #4\] ; \(80b4 <bar\+0x14>\)
+ 80ac: 4801 ldr r0, \[pc, #4\] @ \(80b4 <bar\+0x14>\)
80ae: 4478 add r0, pc
80b0: 6800 ldr r0, \[r0, #0\]
- 80b2: 46c0 nop ; \(mov r8, r8\)
+ 80b2: 46c0 nop @ \(mov r8, r8\)
80b4: 00008092 .word 0x00008092
- 80b8: 4801 ldr r0, \[pc, #4\] ; \(80c0 <bar\+0x20>\)
+ 80b8: 4801 ldr r0, \[pc, #4\] @ \(80c0 <bar\+0x20>\)
80ba: 4478 add r0, pc
80bc: 6800 ldr r0, \[r0, #0\]
- 80be: 46c0 nop ; \(mov r8, r8\)
+ 80be: 46c0 nop @ \(mov r8, r8\)
80c0: 0000808a .word 0x0000808a
- 80c4: 4801 ldr r0, \[pc, #4\] ; \(80cc <bar\+0x2c>\)
- 80c6: 46c0 nop ; \(mov r8, r8\)
- 80c8: 46c0 nop ; \(mov r8, r8\)
+ 80c4: 4801 ldr r0, \[pc, #4\] @ \(80cc <bar\+0x2c>\)
+ 80c6: 46c0 nop @ \(mov r8, r8\)
+ 80c8: 46c0 nop @ \(mov r8, r8\)
80ca: bf00 nop
80cc: 0000000c .word 0x0000000c
- 80d0: 4801 ldr r0, \[pc, #4\] ; \(80d8 <bar\+0x38>\)
+ 80d0: 4801 ldr r0, \[pc, #4\] @ \(80d8 <bar\+0x38>\)
80d2: (f3af 8000)|(bf00 ) nop(.w)?
#...
- 80d6: 46c0 nop ; \(mov r8, r8\)
+ 80d6: 46c0 nop @ \(mov r8, r8\)
80d8: 0000000c .word 0x0000000c
- 80dc: 4801 ldr r0, \[pc, #4\] ; \(80e4 <bar\+0x44>\)
+ 80dc: 4801 ldr r0, \[pc, #4\] @ \(80e4 <bar\+0x44>\)
80de: (f3af 8000)|(bf00 ) nop(.w)?
#...
- 80e2: 46c0 nop ; \(mov r8, r8\)
+ 80e2: 46c0 nop @ \(mov r8, r8\)
80e4: 00000014 .word 0x00000014
- 80e8: 4802 ldr r0, \[pc, #8\] ; \(80f4 <bar\+0x54>\)
+ 80e8: 4802 ldr r0, \[pc, #8\] @ \(80f4 <bar\+0x54>\)
80ea: 4478 add r0, pc
80ec: 6801 ldr r1, \[r0, #0\]
80ee: 1c08 adds r0, r1, #0
- 80f0: 46c0 nop ; \(mov r8, r8\)
+ 80f0: 46c0 nop @ \(mov r8, r8\)
80f2: bf00 nop
80f4: 00008056 .word 0x00008056
- 80f8: 4802 ldr r0, \[pc, #8\] ; \(8104 <bar\+0x64>\)
+ 80f8: 4802 ldr r0, \[pc, #8\] @ \(8104 <bar\+0x64>\)
80fa: 4478 add r0, pc
80fc: 6801 ldr r1, \[r0, #0\]
80fe: 4608 mov r0, r1
- 8100: 46c0 nop ; \(mov r8, r8\)
+ 8100: 46c0 nop @ \(mov r8, r8\)
8102: bf00 nop
8104: 00008046 .word 0x00008046
- 8108: 4802 ldr r0, \[pc, #8\] ; \(8114 <bar\+0x74>\)
- 810a: 46c0 nop ; \(mov r8, r8\)
- 810c: 46c0 nop ; \(mov r8, r8\)
- 810e: 46c0 nop ; \(mov r8, r8\)
- 8110: 46c0 nop ; \(mov r8, r8\)
+ 8108: 4802 ldr r0, \[pc, #8\] @ \(8114 <bar\+0x74>\)
+ 810a: 46c0 nop @ \(mov r8, r8\)
+ 810c: 46c0 nop @ \(mov r8, r8\)
+ 810e: 46c0 nop @ \(mov r8, r8\)
+ 8110: 46c0 nop @ \(mov r8, r8\)
8112: bf00 nop
8114: 0000000c .word 0x0000000c
- 8118: 4802 ldr r0, \[pc, #8\] ; \(8124 <bar\+0x84>\)
- 811a: 46c0 nop ; \(mov r8, r8\)
- 811c: 46c0 nop ; \(mov r8, r8\)
- 811e: 46c0 nop ; \(mov r8, r8\)
- 8120: 46c0 nop ; \(mov r8, r8\)
+ 8118: 4802 ldr r0, \[pc, #8\] @ \(8124 <bar\+0x84>\)
+ 811a: 46c0 nop @ \(mov r8, r8\)
+ 811c: 46c0 nop @ \(mov r8, r8\)
+ 811e: 46c0 nop @ \(mov r8, r8\)
+ 8120: 46c0 nop @ \(mov r8, r8\)
8122: bf00 nop
8124: 0000000c .word 0x0000000c
Disassembly of section .text:
00008000 <foo>:
- 8000: e59f0004 ldr r0, \[pc, #4\] ; 800c <foo\+0xc>
+ 8000: e59f0004 ldr r0, \[pc, #4\] @ 800c <foo\+0xc>
8004: e79f0000 ldr r0, \[pc, r0\]
- 8008: e1a00000 nop ; \(mov r0, r0\)
+ 8008: e1a00000 nop @ \(mov r0, r0\)
800c: 00008138 .word 0x00008138
- 8010: e59f0004 ldr r0, \[pc, #4\] ; 801c <foo\+0x1c>
+ 8010: e59f0004 ldr r0, \[pc, #4\] @ 801c <foo\+0x1c>
8014: e79f0000 ldr r0, \[pc, r0\]
- 8018: e1a00000 nop ; \(mov r0, r0\)
+ 8018: e1a00000 nop @ \(mov r0, r0\)
801c: 00008128 .word 0x00008128
- 8020: e59f0004 ldr r0, \[pc, #4\] ; 802c <foo\+0x2c>
- 8024: e1a00000 nop ; \(mov r0, r0\)
- 8028: e1a00000 nop ; \(mov r0, r0\)
+ 8020: e59f0004 ldr r0, \[pc, #4\] @ 802c <foo\+0x2c>
+ 8024: e1a00000 nop @ \(mov r0, r0\)
+ 8028: e1a00000 nop @ \(mov r0, r0\)
802c: 0000000c .word 0x0000000c
- 8030: e59f0004 ldr r0, \[pc, #4\] ; 803c <foo\+0x3c>
- 8034: e1a00000 nop ; \(mov r0, r0\)
- 8038: e1a00000 nop ; \(mov r0, r0\)
+ 8030: e59f0004 ldr r0, \[pc, #4\] @ 803c <foo\+0x3c>
+ 8034: e1a00000 nop @ \(mov r0, r0\)
+ 8038: e1a00000 nop @ \(mov r0, r0\)
803c: 0000000c .word 0x0000000c
- 8040: e59f000c ldr r0, \[pc, #12\] ; 8054 <foo\+0x54>
+ 8040: e59f000c ldr r0, \[pc, #12\] @ 8054 <foo\+0x54>
8044: e08f0000 add r0, pc, r0
8048: e5901000 ldr r1, \[r0\]
804c: e1a00001 mov r0, r1
- 8050: e1a00000 nop ; \(mov r0, r0\)
+ 8050: e1a00000 nop @ \(mov r0, r0\)
8054: 000080f8 .word 0x000080f8
- 8058: e59f000c ldr r0, \[pc, #12\] ; 806c <foo\+0x6c>
+ 8058: e59f000c ldr r0, \[pc, #12\] @ 806c <foo\+0x6c>
805c: e08f0000 add r0, pc, r0
8060: e5901000 ldr r1, \[r0\]
8064: e1a00001 mov r0, r1
- 8068: e1a00000 nop ; \(mov r0, r0\)
+ 8068: e1a00000 nop @ \(mov r0, r0\)
806c: 000080e0 .word 0x000080e0
- 8070: e59f000c ldr r0, \[pc, #12\] ; 8084 <foo\+0x84>
- 8074: e1a00000 nop ; \(mov r0, r0\)
- 8078: e1a00000 nop ; \(mov r0, r0\)
- 807c: e1a00000 nop ; \(mov r0, r0\)
- 8080: e1a00000 nop ; \(mov r0, r0\)
+ 8070: e59f000c ldr r0, \[pc, #12\] @ 8084 <foo\+0x84>
+ 8074: e1a00000 nop @ \(mov r0, r0\)
+ 8078: e1a00000 nop @ \(mov r0, r0\)
+ 807c: e1a00000 nop @ \(mov r0, r0\)
+ 8080: e1a00000 nop @ \(mov r0, r0\)
8084: 0000000c .word 0x0000000c
- 8088: e59f000c ldr r0, \[pc, #12\] ; 809c <foo\+0x9c>
- 808c: e1a00000 nop ; \(mov r0, r0\)
- 8090: e1a00000 nop ; \(mov r0, r0\)
- 8094: e1a00000 nop ; \(mov r0, r0\)
- 8098: e1a00000 nop ; \(mov r0, r0\)
+ 8088: e59f000c ldr r0, \[pc, #12\] @ 809c <foo\+0x9c>
+ 808c: e1a00000 nop @ \(mov r0, r0\)
+ 8090: e1a00000 nop @ \(mov r0, r0\)
+ 8094: e1a00000 nop @ \(mov r0, r0\)
+ 8098: e1a00000 nop @ \(mov r0, r0\)
809c: 0000000c .word 0x0000000c
000080a0 <bar>:
- 80a0: 4801 ldr r0, \[pc, #4\] ; \(80a8 <bar\+0x8>\)
+ 80a0: 4801 ldr r0, \[pc, #4\] @ \(80a8 <bar\+0x8>\)
80a2: 4478 add r0, pc
80a4: 6800 ldr r0, \[r0, #0\]
- 80a6: 46c0 nop ; \(mov r8, r8\)
+ 80a6: 46c0 nop @ \(mov r8, r8\)
80a8: 0000809e .word 0x0000809e
- 80ac: 4801 ldr r0, \[pc, #4\] ; \(80b4 <bar\+0x14>\)
+ 80ac: 4801 ldr r0, \[pc, #4\] @ \(80b4 <bar\+0x14>\)
80ae: 4478 add r0, pc
80b0: 6800 ldr r0, \[r0, #0\]
- 80b2: 46c0 nop ; \(mov r8, r8\)
+ 80b2: 46c0 nop @ \(mov r8, r8\)
80b4: 00008092 .word 0x00008092
- 80b8: 4801 ldr r0, \[pc, #4\] ; \(80c0 <bar\+0x20>\)
+ 80b8: 4801 ldr r0, \[pc, #4\] @ \(80c0 <bar\+0x20>\)
80ba: 4478 add r0, pc
80bc: 6800 ldr r0, \[r0, #0\]
- 80be: 46c0 nop ; \(mov r8, r8\)
+ 80be: 46c0 nop @ \(mov r8, r8\)
80c0: 0000808a .word 0x0000808a
- 80c4: 4801 ldr r0, \[pc, #4\] ; \(80cc <bar\+0x2c>\)
- 80c6: 46c0 nop ; \(mov r8, r8\)
- 80c8: 46c0 nop ; \(mov r8, r8\)
- 80ca: 46c0 nop ; \(mov r8, r8\)
+ 80c4: 4801 ldr r0, \[pc, #4\] @ \(80cc <bar\+0x2c>\)
+ 80c6: 46c0 nop @ \(mov r8, r8\)
+ 80c8: 46c0 nop @ \(mov r8, r8\)
+ 80ca: 46c0 nop @ \(mov r8, r8\)
80cc: 0000000c .word 0x0000000c
- 80d0: 4801 ldr r0, \[pc, #4\] ; \(80d8 <bar\+0x38>\)
+ 80d0: 4801 ldr r0, \[pc, #4\] @ \(80d8 <bar\+0x38>\)
80d2: bf00 nop
80d4: bf00 nop
- 80d6: 46c0 nop ; \(mov r8, r8\)
+ 80d6: 46c0 nop @ \(mov r8, r8\)
80d8: 0000000c .word 0x0000000c
- 80dc: 4801 ldr r0, \[pc, #4\] ; \(80e4 <bar\+0x44>\)
+ 80dc: 4801 ldr r0, \[pc, #4\] @ \(80e4 <bar\+0x44>\)
80de: bf00 nop
80e0: bf00 nop
- 80e2: 46c0 nop ; \(mov r8, r8\)
+ 80e2: 46c0 nop @ \(mov r8, r8\)
80e4: 00000014 .word 0x00000014
- 80e8: 4802 ldr r0, \[pc, #8\] ; \(80f4 <bar\+0x54>\)
+ 80e8: 4802 ldr r0, \[pc, #8\] @ \(80f4 <bar\+0x54>\)
80ea: 4478 add r0, pc
80ec: 6801 ldr r1, \[r0, #0\]
80ee: 1c08 adds r0, r1, #0
- 80f0: 46c0 nop ; \(mov r8, r8\)
- 80f2: 46c0 nop ; \(mov r8, r8\)
+ 80f0: 46c0 nop @ \(mov r8, r8\)
+ 80f2: 46c0 nop @ \(mov r8, r8\)
80f4: 00008056 .word 0x00008056
- 80f8: 4802 ldr r0, \[pc, #8\] ; \(8104 <bar\+0x64>\)
+ 80f8: 4802 ldr r0, \[pc, #8\] @ \(8104 <bar\+0x64>\)
80fa: 4478 add r0, pc
80fc: 6801 ldr r1, \[r0, #0\]
80fe: 4608 mov r0, r1
- 8100: 46c0 nop ; \(mov r8, r8\)
- 8102: 46c0 nop ; \(mov r8, r8\)
+ 8100: 46c0 nop @ \(mov r8, r8\)
+ 8102: 46c0 nop @ \(mov r8, r8\)
8104: 00008046 .word 0x00008046
- 8108: 4802 ldr r0, \[pc, #8\] ; \(8114 <bar\+0x74>\)
- 810a: 46c0 nop ; \(mov r8, r8\)
- 810c: 46c0 nop ; \(mov r8, r8\)
- 810e: 46c0 nop ; \(mov r8, r8\)
- 8110: 46c0 nop ; \(mov r8, r8\)
- 8112: 46c0 nop ; \(mov r8, r8\)
+ 8108: 4802 ldr r0, \[pc, #8\] @ \(8114 <bar\+0x74>\)
+ 810a: 46c0 nop @ \(mov r8, r8\)
+ 810c: 46c0 nop @ \(mov r8, r8\)
+ 810e: 46c0 nop @ \(mov r8, r8\)
+ 8110: 46c0 nop @ \(mov r8, r8\)
+ 8112: 46c0 nop @ \(mov r8, r8\)
8114: 0000000c .word 0x0000000c
- 8118: 4802 ldr r0, \[pc, #8\] ; \(8124 <bar\+0x84>\)
- 811a: 46c0 nop ; \(mov r8, r8\)
- 811c: 46c0 nop ; \(mov r8, r8\)
- 811e: 46c0 nop ; \(mov r8, r8\)
- 8120: 46c0 nop ; \(mov r8, r8\)
- 8122: 46c0 nop ; \(mov r8, r8\)
+ 8118: 4802 ldr r0, \[pc, #8\] @ \(8124 <bar\+0x84>\)
+ 811a: 46c0 nop @ \(mov r8, r8\)
+ 811c: 46c0 nop @ \(mov r8, r8\)
+ 811e: 46c0 nop @ \(mov r8, r8\)
+ 8120: 46c0 nop @ \(mov r8, r8\)
+ 8122: 46c0 nop @ \(mov r8, r8\)
8124: 0000000c .word 0x0000000c
Disassembly of section .plt:
[0-9a-f]+ <.plt>:
- [0-9a-f]+: e52de004 push {lr} ; .*
- [0-9a-f]+: e59fe004 ldr lr, \[pc, #4\] ; .*
+ [0-9a-f]+: e52de004 push {lr} @ .*
+ [0-9a-f]+: e59fe004 ldr lr, \[pc, #4\] @ .*
[0-9a-f]+: e08fe00e add lr, pc, lr
[0-9a-f]+: e5bef008 ldr pc, \[lr, #8\]!
[0-9a-f]+: 000080e4 .word 0x000080e4
[0-9a-f]+: e08e0000 add r0, lr, r0
[0-9a-f]+: e5901004 ldr r1, \[r0, #4\]
[0-9a-f]+: e12fff11 bx r1
- [0-9a-f]+: e52d2004 push {r2} ; .*
- [0-9a-f]+: e59f200c ldr r2, \[pc, #12\] ; .*
- [0-9a-f]+: e59f100c ldr r1, \[pc, #12\] ; .*
+ [0-9a-f]+: e52d2004 push {r2} @ .*
+ [0-9a-f]+: e59f200c ldr r2, \[pc, #12\] @ .*
+ [0-9a-f]+: e59f100c ldr r1, \[pc, #12\] @ .*
[0-9a-f]+: e79f2002 ldr r2, \[pc, r2\]
[0-9a-f]+: e081100f add r1, r1, pc
[0-9a-f]+: e12fff12 bx r2
Disassembly of section .text:
[0-9a-f]+ <foo>:
- [0-9a-f]+: e59f000c ldr r0, \[pc, #12\] ; .*
+ [0-9a-f]+: e59f000c ldr r0, \[pc, #12\] @ .*
[0-9a-f]+: e08f0000 add r0, pc, r0
[0-9a-f]+: e5901004 ldr r1, \[r0, #4\]
[0-9a-f]+: e12fff31 blx r1
- [0-9a-f]+: e1a00000 nop ; .*
+ [0-9a-f]+: e1a00000 nop @ .*
[0-9a-f]+: 000080b4 .word 0x000080b4
[0-9a-f]+ <bar>:
- [0-9a-f]+: 4802 ldr r0, \[pc, #8\] ; .*
+ [0-9a-f]+: 4802 ldr r0, \[pc, #8\] @ .*
[0-9a-f]+: 4478 add r0, pc
[0-9a-f]+: 6841 ldr r1, \[r0, #4\]
[0-9a-f]+: 4788 blx r1
- [0-9a-f]+: 46c0 nop ; .*
- [0-9a-f]+: 46c0 nop ; .*
+ [0-9a-f]+: 46c0 nop @ .*
+ [0-9a-f]+: 46c0 nop @ .*
[0-9a-f]+: 000080a2 .word 0x000080a2
Disassembly of section .plt:
00008164 <.plt>:
- 8164: e52de004 push {lr} ; .*
- 8168: e59fe004 ldr lr, \[pc, #4\] ; .*
+ 8164: e52de004 push {lr} @ .*
+ 8168: e59fe004 ldr lr, \[pc, #4\] @ .*
816c: e08fe00e add lr, pc, lr
8170: e5bef008 ldr pc, \[lr, #8\]!
8174: 000080d8 .word 0x000080d8
8178: e08e0000 add r0, lr, r0
817c: e5901004 ldr r1, \[r0, #4\]
8180: e12fff11 bx r1
- 8184: e52d2004 push {r2} ; .*
- 8188: e59f200c ldr r2, \[pc, #12\] ; .*
- 818c: e59f100c ldr r1, \[pc, #12\] ; .*
+ 8184: e52d2004 push {r2} @ .*
+ 8188: e59f200c ldr r2, \[pc, #12\] @ .*
+ 818c: e59f100c ldr r1, \[pc, #12\] @ .*
8190: e79f2002 ldr r2, \[pc, r2\]
8194: e081100f add r1, r1, pc
8198: e12fff12 bx r2
Disassembly of section .text:
000081a4 <foo>:
- 81a4: e59f0000 ldr r0, \[pc\] ; .*
+ 81a4: e59f0000 ldr r0, \[pc\] @ .*
81a8: ea000000 b 81b0 <foo\+0xc>
81ac: 000080a4 .word 0x000080a4
81b0: fafffff0 blx 8178 <.plt\+0x14>
000081b4 <bar>:
- 81b4: 4800 ldr r0, \[pc, #0\] ; .*
+ 81b4: 4800 ldr r0, \[pc, #0\] @ .*
81b6: e001 b.n 81bc <bar\+0x8>
81b8: 00008097 .word 0x00008097
81bc: f7ff efdc blx 8178 <.plt\+0x14>
Disassembly of section .plt:
[0-9a-f]+ <.plt>:
- [0-9a-f]+: e52de004 push {lr} ; .*
- [0-9a-f]+: e59fe004 ldr lr, \[pc, #4\] ; .*
+ [0-9a-f]+: e52de004 push {lr} @ .*
+ [0-9a-f]+: e59fe004 ldr lr, \[pc, #4\] @ .*
[0-9a-f]+: e08fe00e add lr, pc, lr
[0-9a-f]+: e5bef008 ldr pc, \[lr, #8\]!
[0-9a-f]+: 000080e8 .word 0x000080e8
[0-9a-f]+: e08e0000 add r0, lr, r0
[0-9a-f]+: e5901004 ldr r1, \[r0, #4\]
[0-9a-f]+: e12fff11 bx r1
- [0-9a-f]+: e52d2004 push {r2} ; .*
- [0-9a-f]+: e59f200c ldr r2, \[pc, #12\] ; .*
- [0-9a-f]+: e59f100c ldr r1, \[pc, #12\] ; .*
+ [0-9a-f]+: e52d2004 push {r2} @ .*
+ [0-9a-f]+: e59f200c ldr r2, \[pc, #12\] @ .*
+ [0-9a-f]+: e59f100c ldr r1, \[pc, #12\] @ .*
[0-9a-f]+: e79f2002 ldr r2, \[pc, r2\]
[0-9a-f]+: e081100f add r1, r1, pc
[0-9a-f]+: e12fff12 bx r2
Disassembly of section .text:
[0-9a-f]+ <foo>:
- [0-9a-f]+: e59f0004 ldr r0, \[pc, #4\] ; .*
+ [0-9a-f]+: e59f0004 ldr r0, \[pc, #4\] @ .*
[0-9a-f]+: fafffff2 blx [0-9a-f]+ .*
- [0-9a-f]+: e1a00000 nop ; .*
+ [0-9a-f]+: e1a00000 nop @ .*
[0-9a-f]+: 000080c4 .word 0x000080c4
[0-9a-f]+ <bar>:
- [0-9a-f]+: 4801 ldr r0, \[pc, #4\] ; .*
+ [0-9a-f]+: 4801 ldr r0, \[pc, #4\] @ .*
[0-9a-f]+: f7ff efe0 blx [0-9a-f]+ .*
- [0-9a-f]+: 46c0 nop ; .*
+ [0-9a-f]+: 46c0 nop @ .*
[0-9a-f]+: 000080b5 .word 0x000080b5
- [0-9a-f]+: 4801 ldr r0, \[pc, #4\] ; .*
+ [0-9a-f]+: 4801 ldr r0, \[pc, #4\] @ .*
[0-9a-f]+: f7ff efda blx [0-9a-f]+ .*
- [0-9a-f]+: 46c0 nop ; .*
+ [0-9a-f]+: 46c0 nop @ .*
[0-9a-f]+: 000080a1 .word 0x000080a1
Disassembly of section .text:
[0-9a-f]+ <foo>:
- [0-9a-f]+: e59f0004 ldr r0, \[pc, #4\] ; .*
+ [0-9a-f]+: e59f0004 ldr r0, \[pc, #4\] @ .*
[0-9a-f]+: e79f0000 ldr r0, \[pc, r0\]
- [0-9a-f]+: e1a00000 nop ; .*
+ [0-9a-f]+: e1a00000 nop @ .*
[0-9a-f]+: 00008020 .word 0x00008020
[0-9a-f]+ <bar>:
- [0-9a-f]+: 4801 ldr r0, \[pc, #4\] ; .*
+ [0-9a-f]+: 4801 ldr r0, \[pc, #4\] @ .*
[0-9a-f]+: 4478 add r0, pc
[0-9a-f]+: 6800 ldr r0, \[r0, #0\]
- [0-9a-f]+: 46c0 nop ; .*
+ [0-9a-f]+: 46c0 nop @ .*
[0-9a-f]+: 00008016 .word 0x00008016
Disassembly of section .text:
[0-9a-f]+ <foo>:
- [0-9a-f]+: e1a00000 nop ; .*
- [0-9a-f]+: e59f0004 ldr r0, \[pc, #4\] ; .*
+ [0-9a-f]+: e1a00000 nop @ .*
+ [0-9a-f]+: e59f0004 ldr r0, \[pc, #4\] @ .*
[0-9a-f]+: e79f0000 ldr r0, \[pc, r0\]
- [0-9a-f]+: e1a00000 nop ; .*
+ [0-9a-f]+: e1a00000 nop @ .*
[0-9a-f]+: 000080a0 .word 0x000080a0
[0-9a-f]+: 000080a4 .word 0x000080a4
[0-9a-f]+ <bar>:
- [0-9a-f]+: 4801 ldr r0, \[pc, #4\] ; .*
+ [0-9a-f]+: 4801 ldr r0, \[pc, #4\] @ .*
[0-9a-f]+: 4478 add r0, pc
[0-9a-f]+: 6800 ldr r0, \[r0, #0\]
- [0-9a-f]+: 46c0 nop ; .*
+ [0-9a-f]+: 46c0 nop @ .*
[0-9a-f]+: 00008092 .word 0x00008092
[0-9a-f]+: 00008094 .word 0x00008094
Disassembly of section .text:
[0-9a-f]+ <foo>:
- [0-9a-f]+: e1a00000 nop ; .*
- [0-9a-f]+: e1a00000 nop ; .*
+ [0-9a-f]+: e1a00000 nop @ .*
+ [0-9a-f]+: e1a00000 nop @ .*
[0-9a-f]+: e1a0f00e mov pc, lr
[0-9a-f]+: 00000008 .word 0x00000008
Disassembly of section .plt:
[0-9a-f]+ <.plt>:
- [0-9a-f]+: e52de004 push {lr} ; .*
- [0-9a-f]+: e59fe004 ldr lr, \[pc, #4\] ; 8128 .*
+ [0-9a-f]+: e52de004 push {lr} @ .*
+ [0-9a-f]+: e59fe004 ldr lr, \[pc, #4\] @ 8128 .*
[0-9a-f]+: e08fe00e add lr, pc, lr
[0-9a-f]+: e5bef008 ldr pc, \[lr, #8\]!
8128: 000080cc .word 0x000080cc
812c: e08e0000 add r0, lr, r0
[0-9a-f]+: e5901004 ldr r1, \[r0, #4\]
[0-9a-f]+: e12fff11 bx r1
- [0-9a-f]+: e52d2004 push {r2} ; .*
- 813c: e59f200c ldr r2, \[pc, #12\] ; 8150 .*
- [0-9a-f]+: e59f100c ldr r1, \[pc, #12\] ; 8154 .*
+ [0-9a-f]+: e52d2004 push {r2} @ .*
+ 813c: e59f200c ldr r2, \[pc, #12\] @ 8150 .*
+ [0-9a-f]+: e59f100c ldr r1, \[pc, #12\] @ 8154 .*
[0-9a-f]+: e79f2002 ldr r2, \[pc, r2\]
[0-9a-f]+: e081100f add r1, r1, pc
[0-9a-f]+: e12fff12 bx r2
Disassembly of section .text:
[0-9a-f]+ <foo>:
- [0-9a-f]+: e59f0004 ldr r0, \[pc, #4\] ; 8164 .*
+ [0-9a-f]+: e59f0004 ldr r0, \[pc, #4\] @ 8164 .*
[0-9a-f]+: fafffff2 blx 812c <.*>
- [0-9a-f]+: e1a00000 nop ; .*
+ [0-9a-f]+: e1a00000 nop @ .*
8164: 000080a0 .word 0x000080a0
Disassembly of section .text:
.* <foo>:
- .*: e1a00000 nop ; \(mov r0, r0\)
- .*: e1a00000 nop ; \(mov r0, r0\)
+ .*: e1a00000 nop @ \(mov r0, r0\)
+ .*: e1a00000 nop @ \(mov r0, r0\)
.*: e1a0f00e mov pc, lr
.*: 00010098 .word 0x00010098
.*: 0001008c .word 0x0001008c
Disassembly of section .plt:
00008170 <.plt>:
-.*: e52de004 push {lr} ; .*
-.*: e59fe004 ldr lr, \[pc, #4\] ; .*
+.*: e52de004 push {lr} @ .*
+.*: e59fe004 ldr lr, \[pc, #4\] @ .*
.*: e08fe00e add lr, pc, lr
.*: e5bef008 ldr pc, \[lr, #8\]!
.*: 000080e0 .word 0x000080e0
.*: e08e0000 add r0, lr, r0
.*: e5901004 ldr r1, \[r0, #4\]
.*: e12fff11 bx r1
-.*: e52d2004 push {r2} ; .*
-.*: e59f200c ldr r2, \[pc, #12\] ; .*
-.*: e59f100c ldr r1, \[pc, #12\] ; .*
+.*: e52d2004 push {r2} @ .*
+.*: e59f200c ldr r2, \[pc, #12\] @ .*
+.*: e59f100c ldr r1, \[pc, #12\] @ .*
.*: e79f2002 ldr r2, \[pc, r2\]
.*: e081100f add r1, r1, pc
.*: e12fff12 bx r2
Disassembly of section .text:
000081b0 <text>:
-.*: e59f0004 ldr r0, \[pc, #4\] ; .*
+.*: e59f0004 ldr r0, \[pc, #4\] @ .*
.*: fafffff2 blx .* <\.plt\+0x14>
-.*: e1a00000 nop ; .*
+.*: e1a00000 nop @ .*
.*: 000080b4 .word 0x000080b4
-.*: 4801 ldr r0, \[pc, #4\] ; .*
+.*: 4801 ldr r0, \[pc, #4\] @ .*
.*: f7ff efe0 blx .* <\.plt\+0x14>
.*: bf00 nop
.*: 000080a5 .word 0x000080a5
Disassembly of section .foo:
04001000 <foo>:
-.*: e59f0004 ldr r0, \[pc, #4\] ; .*
+.*: e59f0004 ldr r0, \[pc, #4\] @ .*
.*: fa000009 blx 4001030 .*
-.*: e1a00000 nop ; .*
+.*: e1a00000 nop @ .*
.*: fc00f264 .word 0xfc00f264
-.*: e59f0004 ldr r0, \[pc, #4\] ; .*
+.*: e59f0004 ldr r0, \[pc, #4\] @ .*
.*: fa000005 blx 4001030 .*
-.*: e1a00000 nop ; .*
+.*: e1a00000 nop @ .*
.*: fc00f25c .word 0xfc00f25c
-.*: 4801 ldr r0, \[pc, #4\] ; .*
+.*: 4801 ldr r0, \[pc, #4\] @ .*
.*: f000 e806 blx 4001030 .*
.*: bf00 nop
.*: fc00f245 .word 0xfc00f245
.*: 00000000 .word 0x00000000
04001030 <__unnamed_veneer>:
-.*: e59f1000 ldr r1, \[pc\] ; .*
+.*: e59f1000 ldr r1, \[pc\] @ .*
.*: e08ff001 add pc, pc, r1
.*: fc007148 .word 0xfc007148
.*: 00000000 .word 0x00000000
Disassembly of section .plt:
0000819c <.plt>:
- 819c: e52de004 push {lr} ; .*
- 81a0: e59fe004 ldr lr, \[pc, #4\] ; .*
+ 819c: e52de004 push {lr} @ .*
+ 81a0: e59fe004 ldr lr, \[pc, #4\] @ .*
81a4: e08fe00e add lr, pc, lr
81a8: e5bef008 ldr pc, \[lr, #8\]!
81ac: 00008100 .word 0x00008100
81b0: e08e0000 add r0, lr, r0
81b4: e5901004 ldr r1, \[r0, #4]
81b8: e12fff11 bx r1
- 81bc: e52d2004 push {r2} ; .*
- 81c0: e59f200c ldr r2, \[pc, #12\] ; .*
- 81c4: e59f100c ldr r1, \[pc, #12\] ; .*
+ 81bc: e52d2004 push {r2} @ .*
+ 81c0: e59f200c ldr r2, \[pc, #12\] @ .*
+ 81c4: e59f100c ldr r1, \[pc, #12\] @ .*
81c8: e79f2002 ldr r2, \[pc, r2\]
81cc: e081100f add r1, r1, pc
81d0: e12fff12 bx r2
Disassembly of section .text:
000081dc <text>:
- 81dc: e59f0004 ldr r0, \[pc, #4\] ; .*
+ 81dc: e59f0004 ldr r0, \[pc, #4\] @ .*
81e0: fafffff2 blx 81b0 .*
- 81e4: e1a00000 nop ; .*
+ 81e4: e1a00000 nop @ .*
81e8: 000080d4 .word 0x000080d4
- 81ec: 4801 ldr r0, \[pc, #4\] ; .*
+ 81ec: 4801 ldr r0, \[pc, #4\] @ .*
81ee: f7ff efe0 blx 81b0 .*
81f2: bf00 nop
81f4: 000080c5 .word 0x000080c5
Disassembly of section .foo:
04001000 <foo>:
- 4001000: e59f0004 ldr r0, \[pc, #4\] ; .*
+ 4001000: e59f0004 ldr r0, \[pc, #4\] @ .*
4001004: e79f0000 ldr r0, \[pc, r0\]
- 4001008: e1a00000 nop ; .*
+ 4001008: e1a00000 nop @ .*
400100c: fc00f2b4 .word 0xfc00f2b4
- 4001010: e59f0004 ldr r0, \[pc, #4\] ; .*
+ 4001010: e59f0004 ldr r0, \[pc, #4\] @ .*
4001014: fa000005 blx 4001030 .*
- 4001018: e1a00000 nop ; .*
+ 4001018: e1a00000 nop @ .*
400101c: fc00f2a0 .word 0xfc00f2a0
- 4001020: 4801 ldr r0, \[pc, #4\] ; .*
+ 4001020: 4801 ldr r0, \[pc, #4\] @ .*
4001022: f000 f809 bl 4001038 .*
4001026: bf00 nop
4001028: fc00f291 .word 0xfc00f291
400102c: 00000000 .word 0x00000000
04001030 <__unnamed_veneer>:
- 4001030: e51ff004 ldr pc, \[pc, #-4\] ; .*
+ 4001030: e51ff004 ldr pc, \[pc, #-4\] @ .*
4001034: 000081b0 .word 0x000081b0
04001038 <__unnamed_veneer>:
4001038: 4778 bx pc
400103a: e7fd b.n .+ <.+>
- 400103c: e51ff004 ldr pc, \[pc, #-4\] ; .*
+ 400103c: e51ff004 ldr pc, \[pc, #-4\] @ .*
4001040: 000081b0 .word 0x000081b0
4001044: 00000000 .word 0x00000000
Disassembly of section .plt:
0000813c <.plt>:
-.*: e52de004 push {lr} ; .*
-.*: e59fe004 ldr lr, \[pc, #4\] ; .*
+.*: e52de004 push {lr} @ .*
+.*: e59fe004 ldr lr, \[pc, #4\] @ .*
.*: e08fe00e add lr, pc, lr
.*: e5bef008 ldr pc, \[lr, #8\]!
.*: 000080f0 .word 0x000080f0
.*: e08e0000 add r0, lr, r0
.*: e5901004 ldr r1, \[r0, #4\]
.*: e12fff11 bx r1
-.*: e52d2004 push {r2} ; .*
-.*: e59f200c ldr r2, \[pc, #12\] ; .*
-.*: e59f100c ldr r1, \[pc, #12\] ; .*
+.*: e52d2004 push {r2} @ .*
+.*: e59f200c ldr r2, \[pc, #12\] @ .*
+.*: e59f100c ldr r1, \[pc, #12\] @ .*
.*: e79f2002 ldr r2, \[pc, r2\]
.*: e081100f add r1, r1, pc
.*: e12fff12 bx r2
Disassembly of section .text:
00008180 <text>:
-.*: e59f0004 ldr r0, \[pc, #4\] ; .*
+.*: e59f0004 ldr r0, \[pc, #4\] @ .*
.*: ebfffff1 bl .* <\.plt\+0x14>
-.*: e1a00000 nop ; .*
+.*: e1a00000 nop @ .*
.*: 000080c0 .word 0x000080c0
-.*: 4801 ldr r0, \[pc, #4\] ; .*
+.*: 4801 ldr r0, \[pc, #4\] @ .*
.*: f000 f805 bl .* <__unnamed_veneer>
-.*: 46c0 nop ; .*
+.*: 46c0 nop @ .*
.*: 000080b1 .word 0x000080b1
.*: 00000000 .word 0x00000000
000081a0 <__unnamed_veneer>:
.*: 4778 bx pc
.*: e7fd b.n .+ <.+>
-.*: e59f1000 ldr r1, \[pc\] ; .*
+.*: e59f1000 ldr r1, \[pc\] @ .*
.*: e081f00f add pc, r1, pc
.*: ffffffa0 .word 0xffffffa0
Disassembly of section .foo:
04001000 <foo>:
-.*: e59f0004 ldr r0, \[pc, #4\] ; .*
+.*: e59f0004 ldr r0, \[pc, #4\] @ .*
.*: eb000009 bl 4001030 .*
-.*: e1a00000 nop ; .*
+.*: e1a00000 nop @ .*
.*: fc00f240 .word 0xfc00f240
-.*: e59f0004 ldr r0, \[pc, #4\] ; .*
+.*: e59f0004 ldr r0, \[pc, #4\] @ .*
.*: eb000005 bl 4001030 .*
-.*: e1a00000 nop ; .*
+.*: e1a00000 nop @ .*
.*: fc00f238 .word 0xfc00f238
-.*: 4801 ldr r0, \[pc, #4\] ; .*
+.*: 4801 ldr r0, \[pc, #4\] @ .*
.*: f000 f80b bl 400103c .*
-.*: 46c0 nop ; .*
+.*: 46c0 nop @ .*
.*: fc00f221 .word 0xfc00f221
.*: 00000000 .word 0x00000000
04001030 <__unnamed_veneer>:
-.*: e59f1000 ldr r1, \[pc\] ; .*
+.*: e59f1000 ldr r1, \[pc\] @ .*
.*: e08ff001 add pc, pc, r1
.*: fc007114 .word 0xfc007114
0400103c <__unnamed_veneer>:
.*: 4778 bx pc
.*: e7fd b.n .+ <.+>
-.*: e59f1000 ldr r1, \[pc\] ; .*
+.*: e59f1000 ldr r1, \[pc\] @ .*
.*: e081f00f add pc, r1, pc
.*: fc007104 .word 0xfc007104
.*: 00000000 .word 0x00000000
Disassembly of section \.plt:
00080800 <_PROCEDURE_LINKAGE_TABLE_>:
- 80800: e59fc000 ldr ip, \[pc] ; 80808 <.*>
+ 80800: e59fc000 ldr ip, \[pc] @ 80808 <.*>
80804: e79cf009 ldr pc, \[ip, r9\]
80808: 0000000c .word 0x0000000c
- 8080c: e59fc000 ldr ip, \[pc] ; 80814 <.*>
+ 8080c: e59fc000 ldr ip, \[pc] @ 80814 <.*>
80810: e599f008 ldr pc, \[r9, #8\]
80814: 00000000 .word 0x00000000
- 80818: e59fc000 ldr ip, \[pc] ; 80820 <.*>
+ 80818: e59fc000 ldr ip, \[pc] @ 80820 <.*>
8081c: e79cf009 ldr pc, \[ip, r9\]
80820: 00000010 .word 0x00000010
- 80824: e59fc000 ldr ip, \[pc] ; 8082c <.*>
+ 80824: e59fc000 ldr ip, \[pc] @ 8082c <.*>
80828: e599f008 ldr pc, \[r9, #8\]
8082c: 0000000c .word 0x0000000c
Disassembly of section \.text:
00080c00 <foo>:
80c00: e92dc200 push {r9, lr, pc}
- 80c04: e59f9024 ldr r9, \[pc, #36\] ; 80c30 <.*>
+ 80c04: e59f9024 ldr r9, \[pc, #36\] @ 80c30 <.*>
80c08: e5999000 ldr r9, \[r9\]
80c0c: e5999000 ldr r9, \[r9\]
- 80c10: e59f001c ldr r0, \[pc, #28\] ; 80c34 <.*>
+ 80c10: e59f001c ldr r0, \[pc, #28\] @ 80c34 <.*>
80c14: e7991000 ldr r1, \[r9, r0\]
80c18: e2811001 add r1, r1, #1
80c1c: e7891000 str r1, \[r9, r0\]
00080800 <_PROCEDURE_LINKAGE_TABLE_>:
80800: e52dc008 str ip, \[sp, #-8\]!
- 80804: e59fc000 ldr ip, \[pc] ; 8080c <.*>
+ 80804: e59fc000 ldr ip, \[pc] @ 8080c <.*>
80808: e59cf008 ldr pc, \[ip, #8\]
8080c: 00081400 .word 0x00081400
8080c: R_ARM_ABS32 _GLOBAL_OFFSET_TABLE_
- 80810: e59fc000 ldr ip, \[pc] ; 80818 <.*>
+ 80810: e59fc000 ldr ip, \[pc] @ 80818 <.*>
80814: e59cf000 ldr pc, \[ip\]
80818: 0008140c .word 0x0008140c
80818: R_ARM_ABS32 _GLOBAL_OFFSET_TABLE_\+0xc
- 8081c: e59fc000 ldr ip, \[pc] ; 80824 <.*>
+ 8081c: e59fc000 ldr ip, \[pc] @ 80824 <.*>
80820: eafffff6 b 80800 <.*>
80824: 00000000 .word 0x00000000
- 80828: e59fc000 ldr ip, \[pc] ; 80830 <.*>
+ 80828: e59fc000 ldr ip, \[pc] @ 80830 <.*>
8082c: e59cf000 ldr pc, \[ip\]
80830: 00081410 .word 0x00081410
80830: R_ARM_ABS32 _GLOBAL_OFFSET_TABLE_\+0x10
- 80834: e59fc000 ldr ip, \[pc] ; 8083c <.*>
+ 80834: e59fc000 ldr ip, \[pc] @ 8083c <.*>
80838: eafffff0 b 80800 <.*>
8083c: 0000000c .word 0x0000000c
Disassembly of section \.text:
SENTINEL_GENERIC_START
} opcode_sentinels;
-#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
-#define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
-#define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
-#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
+#define UNDEFINED_INSTRUCTION "\t\t@ <UNDEFINED> instruction: %0-31x"
+#define UNKNOWN_INSTRUCTION_32BIT "\t\t@ <UNDEFINED> instruction: %08x"
+#define UNKNOWN_INSTRUCTION_16BIT "\t\t@ <UNDEFINED> instruction: %04x"
+#define UNPREDICTABLE_INSTRUCTION "\t@ <UNPREDICTABLE>"
/* Common coprocessor opcodes shared between Arm and Thumb-2. */
0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
+ 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t@ Deprecated"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
+ 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t@ Deprecated"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
+ 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t@ Deprecated"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
+ 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t@ Deprecated"},
/* Data transfer between ARM and NEON registers. */
{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
{
/* ARM instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
- 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
+ 0xe1a00000, 0xffffffff, "nop\t\t\t@ (mov r0, r0)"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
0xe7f000f0, 0xfff000f0, "udf\t#%e"},
/* ARM Instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
- 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
+ 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t@ (str%c %12-15r, %a)"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
- 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
+ 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t@ (ldr%c %12-15r, %a)"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
%c print the condition code
%C print the condition code, or "s" if not conditional
%x print warning if conditional an not at end of IT block"
- %X print "\t; unpredictable <IT:code>" if conditional
+ %X print "\t@ unpredictable <IT:code>" if conditional
%I print IT instruction suffix and operands
%W print Thumb Writeback indicator for LDMIA
%<bitfield>r print bitfield as an ARM register
0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
/* ARM V4T ISA (Thumb v1). */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
- 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
+ 0x46C0, 0xFFFF, "nop%c\t\t\t@ (mov r8, r8)"},
/* Format 4. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
/* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
0x4800, 0xF800,
- "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
+ "ldr%c\t%8-10r, [pc, #%0-7W]\t@ (%0-7a)"},
/* format 9 */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
/* format 12 */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
- 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
+ 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t@ (adr %8-10r, %0-7a)"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
/* format 15 */
%P print address for pli instruction.
%c print the condition code
%x print warning if conditional an not at end of IT block"
- %X print "\t; unpredictable <IT:code>" if conditional
+ %X print "\t@ unpredictable <IT:code>" if conditional
%<bitfield>d print bitfield in decimal
%<bitfield>D print bitfield plus one in decimal
func (stream, ", #%d", amount);
}
else if ((given & 0x80) == 0x80)
- func (stream, "\t; <illegal shifter operand>");
+ func (stream, "\t@ <illegal shifter operand>");
else if (print_shift)
func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
arm_regnames[(given & 0xf00) >> 8]);
switch (size)
{
case 8:
- func (stream, "#%ld\t; 0x%.2lx", value, value);
+ func (stream, "#%ld\t@ 0x%.2lx", value, value);
break;
case 16:
func (stream,
printU
- ? "#%lu\t; 0x%.4lx"
- : "#%ld\t; 0x%.4lx", value, value);
+ ? "#%lu\t@ 0x%.4lx"
+ : "#%ld\t@ 0x%.4lx", value, value);
break;
case 32:
(& floatformat_ieee_single_little, valbytes,
& fvalue);
- func (stream, "#%.7g\t; 0x%.8lx", fvalue,
+ func (stream, "#%.7g\t@ 0x%.8lx", fvalue,
value);
}
else
func (stream,
printU
- ? "#%lu\t; 0x%.8lx"
- : "#%ld\t; 0x%.8lx",
+ ? "#%lu\t@ 0x%.8lx"
+ : "#%ld\t@ 0x%.8lx",
(long) (((value & 0x80000000L) != 0)
&& !printU
? value | ~0xffffffffL : value),
}
if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
{
- func (stream, "\t; ");
+ func (stream, "\t@ ");
/* For unaligned PCs, apply off-by-alignment
correction. */
info->print_address_func (offset + pc
(16 + (value & 0xF));
if (!(decVal % 1000000))
- func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
+ func (stream, "%ld\t@ 0x%08x %c%u.%01u", value,
floatVal, value & 0x80 ? '-' : ' ',
decVal / 10000000,
decVal % 10000000 / 1000000);
else if (!(decVal % 10000))
- func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
+ func (stream, "%ld\t@ 0x%08x %c%u.%03u", value,
floatVal, value & 0x80 ? '-' : ' ',
decVal / 10000000,
decVal % 10000000 / 10000);
else
- func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
+ func (stream, "%ld\t@ 0x%08x %c%u.%07u", value,
floatVal, value & 0x80 ? '-' : ' ',
decVal / 10000000, decVal % 10000000);
break;
}
if (value_in_comment > 32 || value_in_comment < -16)
- func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
+ func (stream, "\t@ 0x%lx", (value_in_comment & 0xffffffffUL));
if (is_unpredictable)
func (stream, UNPREDICTABLE_INSTRUCTION);
offset = pc + 8;
}
- func (stream, "\t; ");
+ func (stream, "\t@ ");
info->print_address_func (offset, info);
offset = 0;
}
switch (size)
{
case 8:
- func (stream, "#%ld\t; 0x%.2lx", value, value);
+ func (stream, "#%ld\t@ 0x%.2lx", value, value);
break;
case 16:
- func (stream, "#%ld\t; 0x%.4lx", value, value);
+ func (stream, "#%ld\t@ 0x%.4lx", value, value);
break;
case 32:
(& floatformat_ieee_single_little, valbytes,
& fvalue);
- func (stream, "#%.7g\t; 0x%.8lx", fvalue,
+ func (stream, "#%.7g\t@ 0x%.8lx", fvalue,
value);
}
else
- func (stream, "#%ld\t; 0x%.8lx",
+ func (stream, "#%ld\t@ 0x%.8lx",
(long) (((value & 0x80000000L) != 0)
? value | ~0xffffffffL : value),
value);
}
if (value_in_comment > 32 || value_in_comment < -16)
- func (stream, "\t; 0x%lx", value_in_comment);
+ func (stream, "\t@ 0x%lx", value_in_comment);
if (is_unpredictable)
func (stream, UNPREDICTABLE_INSTRUCTION);
}
if (value_in_comment > 32 || value_in_comment < -16)
- func (stream, "\t; 0x%lx", value_in_comment);
+ func (stream, "\t@ 0x%lx", value_in_comment);
if (is_unpredictable)
print_mve_unpredictable (info, unpredictable_cond);
{
/* Elide positive zero offset. */
if (offset || NEGATIVE_BIT_SET)
- func (stream, "[pc, #%s%d]\t; ",
+ func (stream, "[pc, #%s%d]\t@ ",
NEGATIVE_BIT_SET ? "-" : "", (int) offset);
else
- func (stream, "[pc]\t; ");
+ func (stream, "[pc]\t@ ");
if (NEGATIVE_BIT_SET)
offset = -offset;
info->print_address_func (offset + pc + 8, info);
/* Some SWI instructions have special
meanings. */
if ((given & 0x0fffffff) == 0x0FF00000)
- func (stream, "\t; IMB");
+ func (stream, "\t@ IMB");
else if ((given & 0x0fffffff) == 0x0FF00001)
- func (stream, "\t; IMBRange");
+ func (stream, "\t@ IMBRange");
break;
case 'X':
func (stream, "%01lx", value & 0xf);
}
if (value_in_comment > 32 || value_in_comment < -16)
- func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
+ func (stream, "\t@ 0x%lx", (value_in_comment & 0xffffffffUL));
if (is_unpredictable)
func (stream, UNPREDICTABLE_INSTRUCTION);
case 'x':
if (ifthen_next_state)
- func (stream, "\t; unpredictable branch in IT block\n");
+ func (stream, "\t@ unpredictable branch in IT block\n");
break;
case 'X':
if (ifthen_state)
- func (stream, "\t; unpredictable <IT:%s>",
+ func (stream, "\t@ unpredictable <IT:%s>",
arm_conditional[IFTHEN_COND]);
break;
}
if (value_in_comment > 32 || value_in_comment < -16)
- func (stream, "\t; 0x%lx", value_in_comment);
+ func (stream, "\t@ 0x%lx", value_in_comment);
return;
}
case 'x':
if (ifthen_next_state)
- func (stream, "\t; unpredictable branch in IT block\n");
+ func (stream, "\t@ unpredictable branch in IT block\n");
break;
case 'X':
if (ifthen_state)
- func (stream, "\t; unpredictable <IT:%s>",
+ func (stream, "\t@ unpredictable <IT:%s>",
arm_conditional[IFTHEN_COND]);
break;
if (Rn == 15)
{
- func (stream, "\t; ");
+ func (stream, "\t@ ");
info->print_address_func (((pc + 4) & ~3) + offset, info);
}
}
if ((given & (1 << 23)) == 0)
offset = - offset;
- func (stream, "\t; ");
+ func (stream, "\t@ ");
info->print_address_func ((pc & ~3) + 4 + offset, info);
}
break;
}
if (value_in_comment > 32 || value_in_comment < -16)
- func (stream, "\t; 0x%lx", value_in_comment);
+ func (stream, "\t@ 0x%lx", value_in_comment);
if (is_unpredictable)
func (stream, UNPREDICTABLE_INSTRUCTION);
projects / binutils-gdb.git / commitdiff