ac: add radeon_info::tcc_harvested
authorMarek Olšák <marek.olsak@amd.com>
Tue, 24 Sep 2019 20:56:21 +0000 (16:56 -0400)
committerMarek Olšák <marek.olsak@amd.com>
Mon, 30 Sep 2019 17:36:20 +0000 (13:36 -0400)
Cc: 19.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
src/amd/common/ac_gpu_info.c
src/amd/common/ac_gpu_info.h

index 41713b5348e62372b9df1980a1c487cfcfd20c5e..b5e0b8415d29ac25522902f861f4f5a67b14d0fc 100644 (file)
@@ -470,6 +470,9 @@ bool ac_query_gpu_info(int fd, void *dev_p,
        }
        if (info->chip_class >= GFX10) {
                info->tcc_cache_line_size = 128;
+               /* This is a hack, but it's all we can do without a kernel upgrade. */
+               info->tcc_harvested =
+                       (info->vram_size / info->num_tcc_blocks) != 512*1024*1024;
        } else {
                info->tcc_cache_line_size = 64;
        }
@@ -694,6 +697,7 @@ void ac_print_gpu_info(struct radeon_info *info)
        printf("    num_sdma_rings = %i\n", info->num_sdma_rings);
        printf("    clock_crystal_freq = %i\n", info->clock_crystal_freq);
        printf("    tcc_cache_line_size = %u\n", info->tcc_cache_line_size);
+       printf("    tcc_harvested = %u\n", info->tcc_harvested);
 
        printf("    use_display_dcc_unaligned = %u\n", info->use_display_dcc_unaligned);
        printf("    use_display_dcc_with_retile_blit = %u\n", info->use_display_dcc_with_retile_blit);
index a21bd51e29d28a5cab29908fef46d40c344146e3..a2adab88ec4dafd05741e0dd045937dc240453ba 100644 (file)
@@ -58,6 +58,7 @@ struct radeon_info {
        uint32_t                    num_sdma_rings;
        uint32_t                    clock_crystal_freq;
        uint32_t                    tcc_cache_line_size;
+       bool                        tcc_harvested;
        bool                        has_clear_state;
        bool                        has_distributed_tess;
        bool                        has_dcc_constant_encode;