i965: Support multisampling in surface_state for textures

The surface_state setup for renderbuffers already worked; only the
texturing side needed work. BLORP does something similar, but does its
own surface_state setup.

On Gen6, we just need to set the correct sample count.

On Gen7: - set the correct sample count
         - set the correct layout mode
         - set GEN7_SURFACE_ARYSPC_LOD0 if it's set in the miptree.

V2: - Clarify commit message
    - Rebased onto Paul's physical/logical dims cleanup
    - Added Gen7 support

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Paul Berry <stereotype441@gmail.com>

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 267d00b60eee7203c0eb0acc911246ff529d39c7..5eee364eb7265f1177b2fb037cd661e2ebaed28b 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -885,7 +885,7 @@ brw_update_texture_surface(struct gl_context *ctx,
              (intelObj->mt->region->pitch - 1) <<
              BRW_SURFACE_PITCH_SHIFT);
 
-   surf[4] = 0;
+   surf[4] = brw_get_surface_num_multisamples(intelObj->mt->num_samples);
 
    intel_miptree_get_tile_offsets(intelObj->mt, firstImage->Level, 0,
                                   &tile_x, &tile_y);

diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index d53df20d63cca689d18001fe9f8bc67397e2876a..ef062d2fba4cd8d7d0808d6ab543d46ca7499d71 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -299,10 +299,6 @@ gen7_update_texture_surface(struct gl_context *ctx,
       return;
    }
 
-   /* We don't support MSAA for textures. */
-   assert(!mt->array_spacing_lod0);
-   assert(mt->num_samples <= 1);
-
    intel_miptree_get_dimensions_for_image(firstImage, &width, &height, &depth);
 
    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
@@ -328,6 +324,9 @@ gen7_update_texture_surface(struct gl_context *ctx,
    if (depth > 1 && tObj->Target != GL_TEXTURE_3D)
       surf[0] |= GEN7_SURFACE_IS_ARRAY;
 
+   if (mt->array_spacing_lod0)
+      surf[0] |= GEN7_SURFACE_ARYSPC_LOD0;
+
    surf[1] = mt->region->bo->offset + mt->offset; /* reloc */
 
    surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
@@ -335,6 +334,8 @@ gen7_update_texture_surface(struct gl_context *ctx,
    surf[3] = SET_FIELD(depth - 1, BRW_SURFACE_DEPTH) |
              ((intelObj->mt->region->pitch) - 1);
 
+   surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout);
+
    intel_miptree_get_tile_offsets(intelObj->mt, firstImage->Level, 0,
                                   &tile_x, &tile_y);
    assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));