PR target/93995 ICE in patch_jump_insn, at cfgrtl.c:1290 on riscv64-linux-gnu

Last code gen change of LTGT didn't consider the situation of cbranch with LTGT,
branch only support few compare codes.

gcc/ChangeLog

	* config/riscv/riscv.c (riscv_emit_float_compare): Using NE to compare
	the result of IOR.

gcc/testsuite/ChangeLog

	* gcc.dg/pr93995.c: New.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 862dffee119b41b9cce4a3bb7bb50716288f6703..42f417abb27c5b6ee05a20207fed6281cc08223a 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2020-03-04  Kito Cheng  <kito.cheng@sifive.com>
+
+       PR target/93995
+       * config/riscv/riscv.c (riscv_emit_float_compare): Using NE to compare
+       the result of IOR.
+
 2020-03-03  Dennis Zhang  <dennis.zhang@arm.com>
 
        * config/arm/arm_bf16.h (vcvtah_f32_bf16, vcvth_bf16_f32): New.

diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index d45b19d861b23ee8a4119075e9211ccee8dbe9c4..94b5ac0176271ad62785f9f6f3f9f6841e407af6 100644 (file)
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -2299,9 +2299,10 @@ riscv_emit_float_compare (enum rtx_code *code, rtx *op0, rtx *op1)
 
     case LTGT:
       /* (a < b) | (a > b) */
-      *code = IOR;
-      *op0 = riscv_force_binary (word_mode, LT, cmp_op0, cmp_op1);
-      *op1 = riscv_force_binary (word_mode, GT, cmp_op0, cmp_op1);
+      tmp0 = riscv_force_binary (word_mode, LT, cmp_op0, cmp_op1);
+      tmp1 = riscv_force_binary (word_mode, GT, cmp_op0, cmp_op1);
+      *op0 = riscv_force_binary (word_mode, IOR, tmp0, tmp1);
+      *op1 = const0_rtx;
       break;
 
     default:

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 5e8a8356a4237f6e4495b492abccfafd6ddbf9fe..cd519f4116b42585c4897aa7995c1f524d87208d 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2020-03-04  Kito Cheng  <kito.cheng@sifive.com>
+
+       PR target/93995
+       * gcc.dg/pr93995.c: New.
+
 2020-03-03  Marek Polacek  <polacek@redhat.com>
 
        PR c++/90505 - mismatch in template argument deduction.

diff --git a/gcc/testsuite/gcc.dg/pr93995.c b/gcc/testsuite/gcc.dg/pr93995.c
new file mode 100644 (file)
index 0000000..b89c85d
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr93995.c
@@ -0,0 +1,46 @@
+/* PR target/93995 */
+/* { dg-do run } */
+/* { dg-options "-O2 -fno-trapping-math" } */
+
+double s1[4], s2[4], s3[64];
+
+int
+main (void)
+{
+  int i;
+  asm volatile ("" : : : "memory");
+  for (i = 0; i < 4; i++)
+    s3[0 * 4 + i] = __builtin_isgreater (s1[i], s2[i]) ? -1.0 : 0.0;
+  for (i = 0; i < 4; i++)
+    s3[1 * 4 + i] = (!__builtin_isgreater (s1[i], s2[i])) ? -1.0 : 0.0;
+  for (i = 0; i < 4; i++)
+    s3[2 * 4 + i] = __builtin_isgreaterequal (s1[i], s2[i]) ? -1.0 : 0.0;
+  for (i = 0; i < 4; i++)
+    s3[3 * 4 + i] = (!__builtin_isgreaterequal (s1[i], s2[i])) ? -1.0 : 0.0;
+  for (i = 0; i < 4; i++)
+    s3[4 * 4 + i] = __builtin_isless (s1[i], s2[i]) ? -1.0 : 0.0;
+  for (i = 0; i < 4; i++)
+    s3[5 * 4 + i] = (!__builtin_isless (s1[i], s2[i])) ? -1.0 : 0.0;
+  for (i = 0; i < 4; i++)
+    s3[6 * 4 + i] = __builtin_islessequal (s1[i], s2[i]) ? -1.0 : 0.0;
+  for (i = 0; i < 4; i++)
+    s3[7 * 4 + i] = (!__builtin_islessequal (s1[i], s2[i])) ? -1.0 : 0.0;
+  for (i = 0; i < 4; i++)
+    s3[8 * 4 + i] = __builtin_islessgreater (s1[i], s2[i]) ? -1.0 : 0.0;
+  for (i = 0; i < 4; i++)
+    s3[9 * 4 + i] = (!__builtin_islessgreater (s1[i], s2[i])) ? -1.0 : 0.0;
+  for (i = 0; i < 4; i++)
+    s3[10 * 4 + i] = __builtin_isunordered (s1[i], s2[i]) ? -1.0 : 0.0;
+  for (i = 0; i < 4; i++)
+    s3[11 * 4 + i] = (!__builtin_isunordered (s1[i], s2[i])) ? -1.0 : 0.0;
+  for (i = 0; i < 4; i++)
+    s3[12 * 4 + i] = s1[i] > s2[i] ? -1.0 : 0.0;
+  for (i = 0; i < 4; i++)
+    s3[13 * 4 + i] = s1[i] >= s2[i] ? -1.0 : 0.0;
+  for (i = 0; i < 4; i++)
+    s3[14 * 4 + i] = s1[i] < s2[i] ? -1.0 : 0.0;
+  for (i = 0; i < 4; i++)
+    s3[15 * 4 + i] = s1[i] <= s2[i] ? -1.0 : 0.0;
+  asm volatile ("" : : : "memory");
+  return 0;
+}