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Merge pull request #316 from antonblanchard/verilator-fix
authorPaul Mackerras <paulus@ozlabs.org>
Sat, 14 Aug 2021 00:18:42 +0000 (10:18 +1000)
committerGitHub <noreply@github.com>
Sat, 14 Aug 2021 00:18:42 +0000 (10:18 +1000)
Rename 'do' signal to avoid verilator System Verilog warning


Trivial merge