ARM: Make an SRS instruction with a bad mode cause an undefined instruction fault.

diff --git a/src/arch/arm/isa/formats/mem.isa b/src/arch/arm/isa/formats/mem.isa
index 59a6f126a808663ad91587612dc88c423b25a092..f7830eff34f68dfca2db820d750167c2c65a50e6 100644 (file)
--- a/src/arch/arm/isa/formats/mem.isa
+++ b/src/arch/arm/isa/formats/mem.isa
@@ -282,6 +282,8 @@ def format Thumb32SrsRfe() {{
             }
         } else {
             const uint32_t mode = bits(machInst, 4, 0);
+            if (badMode((OperatingMode)mode))
+                return new Unknown(machInst);
             if (!add && !wb) {
                 return new %(srs)s(machInst, mode,
                         SrsOp::DecrementBefore, wb);

diff --git a/src/arch/arm/isa/formats/uncond.isa b/src/arch/arm/isa/formats/uncond.isa
index f4cc16262a8ac43d84dfa8c2ca1f7b9f93e8f542..4fa707b2bee3bc83ae4016cce9f9d12cabb5d960 100644 (file)
--- a/src/arch/arm/isa/formats/uncond.isa
+++ b/src/arch/arm/isa/formats/uncond.isa
@@ -166,6 +166,8 @@ def format ArmUnconditional() {{
                     const uint32_t val = ((machInst >> 20) & 0x5);
                     if (val == 0x4) {
                         const uint32_t mode = bits(machInst, 4, 0);
+                        if (badMode((OperatingMode)mode))
+                            return new Unknown(machInst);
                         switch (bits(machInst, 24, 21)) {
                           case 0x2:
                             return new %(srs)s(machInst, mode,