build.plat,vendor: allow clock constraints on arbitrary signals.

Currently only done for Synopsys based toolchains (i.e. not nextpnr).

Refs #88.

diff --git a/nmigen/build/plat.py b/nmigen/build/plat.py
index f6aac5482f1ce318890ef1939a1d771fcbf5d65c..c8e50584fb394b005ff2aa931b9d89b9e8a85169 100644 (file)
--- a/nmigen/build/plat.py
+++ b/nmigen/build/plat.py
@@ -296,6 +296,9 @@ class TemplatedPlatform(Platform):
             else:
                 return " ".join(opts)
 
+        def hierarchy(signal, separator):
+            return separator.join(name_map[signal][1:])
+
         def verbose(arg):
             if "NMIGEN_verbose" in os.environ:
                 return arg
@@ -313,6 +316,7 @@ class TemplatedPlatform(Platform):
                 source   = textwrap.dedent(source).strip()
                 compiled = jinja2.Template(source, trim_blocks=True, lstrip_blocks=True)
                 compiled.environment.filters["options"] = options
+                compiled.environment.filters["hierarchy"] = hierarchy
             except jinja2.TemplateSyntaxError as e:
                 e.args = ("{} (at {}:{})".format(e.message, origin, e.lineno),)
                 raise

diff --git a/nmigen/vendor/lattice_ecp5.py b/nmigen/vendor/lattice_ecp5.py
index a2231a1e2d18304c29fbeaa9ef5b8265c34f0408..db4ac0669327f98108d50f650953390060e215d4 100644 (file)
--- a/nmigen/vendor/lattice_ecp5.py
+++ b/nmigen/vendor/lattice_ecp5.py
@@ -209,7 +209,7 @@ class LatticeECP5Platform(TemplatedPlatform):
         """,
         "{{name}}.sdc": r"""
             {% for signal, frequency in platform.iter_clock_constraints() -%}
-                create_clock -period {{1000000000/frequency}} [get_ports {{signal.name}}]
+                create_clock -period {{1000000000/frequency}} [get_nets {{signal|hierarchy("/")}}]
             {% endfor %}
             {{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
         """,

diff --git a/nmigen/vendor/xilinx_7series.py b/nmigen/vendor/xilinx_7series.py
index 9529597e51c93ee2218787472dcaf24728e50033..61733c8c56df0ed1fb1e5b310cea0e9657cbd095 100644 (file)
--- a/nmigen/vendor/xilinx_7series.py
+++ b/nmigen/vendor/xilinx_7series.py
@@ -106,7 +106,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
                 {% endfor %}
             {% endfor %}
             {% for signal, frequency in platform.iter_clock_constraints() -%}
-                create_clock -name {{signal.name}} -period {{1000000000/frequency}} [get_ports {{signal.name}}]
+                create_clock -name {{signal.name}} -period {{1000000000/frequency}} [get_nets {{signal|hierarchy("/")}}]
             {% endfor %}
             {{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
         """

diff --git a/nmigen/vendor/xilinx_spartan_3_6.py b/nmigen/vendor/xilinx_spartan_3_6.py
index 9f152dca7788d7ea92eab6941e4dd648c0218b0e..c4c18ceffafaa2f1a2ea6d8fdde40fbc1a590271 100644 (file)
--- a/nmigen/vendor/xilinx_spartan_3_6.py
+++ b/nmigen/vendor/xilinx_spartan_3_6.py
@@ -127,8 +127,8 @@ class XilinxSpartan3Or6Platform(TemplatedPlatform):
                 {% endfor %}
             {% endfor %}
             {% for signal, frequency in platform.iter_clock_constraints() -%}
-                NET "{{signal.name}}" TNM_NET="PRD{{signal.name}}";
-                TIMESPEC "TS{{signal.name}}"=PERIOD "PRD{{signal.name}}" {{1000000000/frequency}} ns HIGH 50%;
+                NET "{{signal|hierarchy("/")}}" TNM_NET="PRD{{signal|hierarchy("/")}}";
+                TIMESPEC "TS{{signal|hierarchy("/")}}"=PERIOD "PRD{{signal|hierarchy("/")}}" {{1000000000/frequency}} ns HIGH 50%;
             {% endfor %}
             {{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
         """