crg: use new platform.request

diff --git a/mibuild/crg.py b/mibuild/crg.py
index 5d8510dd71b7bb823a74418636660465950c7f2c..7d967742a40f0259d5b469cf5247b2aafde57e1e 100644 (file)
--- a/mibuild/crg.py
+++ b/mibuild/crg.py
@@ -4,9 +4,8 @@ from migen.fhdl.module import Module
 class SimpleCRG(Module):
        def __init__(self, platform, clk_name, rst_name, rst_invert=False):
                        self.clock_domains.cd_sys = ClockDomain()
-                       platform.request(clk_name, None, self.cd_sys.clk)
+                       self.comb += self.cd_sys.clk.eq(platform.request(clk_name))
                        if rst_invert:
-                               rst_n = platform.request(rst_name)
-                               self.comb += self.cd_sys.rst.eq(~rst_n)
+                               self.comb += self.cd_sys.rst.eq(~platform.request(rst_name))
                        else:
-                               platform.request(rst_name, None, self.cd_sys.rst)
+                               self.comb += self.cd_sys.rst.eq(platform.request(rst_name))

diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py
index cddbbb81e4fbf21610b19202454e228f6bfb2a1b..6a1e9d7ed707f52e51b4bebfe653c7d63ea90af4 100644 (file)
--- a/mibuild/xilinx_ise.py
+++ b/mibuild/xilinx_ise.py
@@ -24,10 +24,9 @@ class CRG_DS(Module):
                self.clock_domains.cd_sys = ClockDomain()
                self._clk = platform.request(clk_name)
                if rst_invert:
-                       rst_n = platform.request(rst_name)
-                       self.comb += self.cd_sys.rst.eq(~rst_n)
+                       self.comb += self.cd_sys.rst.eq(~platform.request(rst_name))
                else:
-                       platform.request(rst_name, None, self.cd_sys.rst)
+                       self.comb += self.cd_sys.rst.eq(platform.request(rst_name))
                _add_period_constraint(platform, self._clk.p, period)
                self.specials += Instance("IBUFGDS",
                        Instance.Input("I", self._clk.p),