radeonsi: remove the shader parameter from si_set_ring_buffer

not used anymore

this is a follow-up to the RW buffer cleanup.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index e44201b1962b6f27218ec1aff700da63b4bc95c0..6926c6b701d1363252e19df8d30d85b7bafc190d 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -907,7 +907,7 @@ static void si_set_shader_buffers(struct pipe_context *ctx, unsigned shader,
 
 /* RING BUFFERS */
 
-void si_set_ring_buffer(struct pipe_context *ctx, uint shader, uint slot,
+void si_set_ring_buffer(struct pipe_context *ctx, uint slot,
                        struct pipe_resource *buffer,
                        unsigned stride, unsigned num_records,
                        bool add_tid, bool swizzle,
@@ -916,9 +916,6 @@ void si_set_ring_buffer(struct pipe_context *ctx, uint shader, uint slot,
        struct si_context *sctx = (struct si_context *)ctx;
        struct si_buffer_resources *buffers = &sctx->rw_buffers;
 
-       if (shader >= SI_NUM_SHADERS)
-               return;
-
        /* The stride field in the resource descriptor has 14 bits */
        assert(stride < (1 << 14));
 

diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h
index ef9f86449e60f2e159f7dc7814f3cae4081205da..ed3a1fe18ada1248a1119dfb0a3ab179f0e67712 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -248,7 +248,7 @@ struct si_buffer_resources {
 
 /* si_descriptors.c */
 void si_ce_enable_loads(struct radeon_winsys_cs *ib);
-void si_set_ring_buffer(struct pipe_context *ctx, uint shader, uint slot,
+void si_set_ring_buffer(struct pipe_context *ctx, uint slot,
                        struct pipe_resource *buffer,
                        unsigned stride, unsigned num_records,
                        bool add_tid, bool swizzle,

diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index d02ce8f74dd5b13871a09943def4c21a66462391..4fc079716a7a3ce0a835c960089f92cc007e2bc7 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -1565,15 +1565,15 @@ static bool si_update_gs_ring_buffers(struct si_context *sctx)
 
        /* Set ring bindings. */
        if (sctx->esgs_ring) {
-               si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_ES_RING_ESGS,
+               si_set_ring_buffer(&sctx->b.b, SI_ES_RING_ESGS,
                                   sctx->esgs_ring, 0, sctx->esgs_ring->width0,
                                   true, true, 4, 64, 0);
-               si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_GS_RING_ESGS,
+               si_set_ring_buffer(&sctx->b.b, SI_GS_RING_ESGS,
                                   sctx->esgs_ring, 0, sctx->esgs_ring->width0,
                                   false, false, 0, 0, 0);
        }
        if (sctx->gsvs_ring)
-               si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_VS_RING_GSVS,
+               si_set_ring_buffer(&sctx->b.b, SI_VS_RING_GSVS,
                                   sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
                                   false, false, 0, 0, 0);
        return true;
@@ -1589,22 +1589,22 @@ static void si_update_gsvs_ring_bindings(struct si_context *sctx)
 
        sctx->last_gsvs_itemsize = gsvs_itemsize;
 
-       si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_GS_RING_GSVS0,
+       si_set_ring_buffer(&sctx->b.b, SI_GS_RING_GSVS0,
                           sctx->gsvs_ring, gsvs_itemsize,
                           64, true, true, 4, 16, 0);
 
        offset = gsvs_itemsize * 64;
-       si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_GS_RING_GSVS1,
+       si_set_ring_buffer(&sctx->b.b, SI_GS_RING_GSVS1,
                           sctx->gsvs_ring, gsvs_itemsize,
                           64, true, true, 4, 16, offset);
 
        offset = (gsvs_itemsize * 2) * 64;
-       si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_GS_RING_GSVS2,
+       si_set_ring_buffer(&sctx->b.b, SI_GS_RING_GSVS2,
                           sctx->gsvs_ring, gsvs_itemsize,
                           64, true, true, 4, 16, offset);
 
        offset = (gsvs_itemsize * 3) * 64;
-       si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_GS_RING_GSVS3,
+       si_set_ring_buffer(&sctx->b.b, SI_GS_RING_GSVS3,
                           sctx->gsvs_ring, gsvs_itemsize,
                           64, true, true, 4, 16, offset);
 }
@@ -1792,9 +1792,8 @@ static void si_init_tess_factor_ring(struct si_context *sctx)
        sctx->b.initial_gfx_cs_size = 0; /* force flush */
        si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
 
-       si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_TESS_CTRL,
-                          SI_HS_RING_TESS_FACTOR, sctx->tf_ring, 0,
-                          sctx->tf_ring->width0, false, false, 0, 0, 0);
+       si_set_ring_buffer(&sctx->b.b, SI_HS_RING_TESS_FACTOR, sctx->tf_ring,
+                          0, sctx->tf_ring->width0, false, false, 0, 0, 0);
 }
 
 /**