Changed BaseCPU::ProfileEvent's interval member to be of type Tick. This was done...

python type of a latency.  In addition, the multiple definitions of profile in the different cpu models caused
problems for intialization of the interval value. If a child class's profile value was defined, the parent
BaseCPU::ProfileEvent interval field would be initialized with a garbage value. The fix was to remove the
multiple redifitions of profile in the child CPU classes.

diff --git a/src/cpu/CheckerCPU.py b/src/cpu/CheckerCPU.py
index 06df9c1b1b6b38883ede4e23b2a048ae34b6397c..bff9af62d280754b6f8f6cf2eb4eddafd19898c0 100644 (file)
--- a/src/cpu/CheckerCPU.py
+++ b/src/cpu/CheckerCPU.py
@@ -40,5 +40,3 @@ class CheckerCPU(BaseCPU):
         "If a load result is incorrect, only print a warning and do not exit")
     function_trace = Param.Bool(False, "Enable function trace")
     function_trace_start = Param.Tick(0, "Cycle to start function trace")
-    if build_env['FULL_SYSTEM']:
-        profile = Param.Latency('0ns', "trace the kernel stack")

diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index f79b79350ab5f143ef52ff571daca3c2e50ec7be..7b64044196f1517dd76099ff51cc8c1960fb7938 100644 (file)
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -357,7 +357,7 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU, Port *ic, Port *dc)
 
 
 #if FULL_SYSTEM
-BaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, int _interval)
+BaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval)
     : Event(&mainEventQueue), cpu(_cpu), interval(_interval)
 { }
 

diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 6e9e1dc39acefff096850406c285830f87721321..251adc1b72aa3a33e74b35a087ff40f3003a1b83 100644 (file)
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -122,10 +122,10 @@ class BaseCPU : public MemObject
     {
       private:
         BaseCPU *cpu;
-        int interval;
+        Tick interval;
 
       public:
-        ProfileEvent(BaseCPU *cpu, int interval);
+        ProfileEvent(BaseCPU *cpu, Tick interval);
         void process();
     };
     ProfileEvent *profileEvent;

diff --git a/src/cpu/o3/O3Checker.py b/src/cpu/o3/O3Checker.py
index 43a71d67b60082b3d92da25cfa4a336c4b45c337..edc6dc9b6fdc78d61bf049075c92fa591b26d47f 100644 (file)
--- a/src/cpu/o3/O3Checker.py
+++ b/src/cpu/o3/O3Checker.py
@@ -39,5 +39,3 @@ class O3Checker(BaseCPU):
         "If a load result is incorrect, only print a warning and do not exit")
     function_trace = Param.Bool(False, "Enable function trace")
     function_trace_start = Param.Tick(0, "Cycle to start function trace")
-    if build_env['FULL_SYSTEM']:
-        profile = Param.Latency('0ns', "trace the kernel stack")

diff --git a/src/cpu/ozone/OzoneCPU.py b/src/cpu/ozone/OzoneCPU.py
index b9cfb448f88a3e653a7c5051f826d5dbab8c01da..37386898d1682c78636630197b2bf5c7cda964c9 100644 (file)
--- a/src/cpu/ozone/OzoneCPU.py
+++ b/src/cpu/ozone/OzoneCPU.py
@@ -40,8 +40,6 @@ class DerivOzoneCPU(BaseCPU):
 
     if build_env['USE_CHECKER']:
         checker = Param.BaseCPU("Checker CPU")
-    if build_env['FULL_SYSTEM']:
-        profile = Param.Latency('0ns', "trace the kernel stack")
 
     icache_port = Port("Instruction Port")
     dcache_port = Port("Data Port")

diff --git a/src/cpu/ozone/OzoneChecker.py b/src/cpu/ozone/OzoneChecker.py
index f20b8770e026a22c8cab3fd634232fc40e08045c..bfa39ead90f697ed3d9fc3c0f1d58c82c2fbc6c8 100644 (file)
--- a/src/cpu/ozone/OzoneChecker.py
+++ b/src/cpu/ozone/OzoneChecker.py
@@ -39,5 +39,3 @@ class OzoneChecker(BaseCPU):
         "If a load result is incorrect, only print a warning and do not exit")
     function_trace = Param.Bool(False, "Enable function trace")
     function_trace_start = Param.Tick(0, "Cycle to start function trace")
-    if build_env['FULL_SYSTEM']:
-        profile = Param.Latency('0ns', "trace the kernel stack")

diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py
index e1c1e4cd1e46889896b3665b324720e018bffd11..87e8b5509fba33259881c8e5c7fbe3e182b4bee2 100644 (file)
--- a/src/cpu/simple/AtomicSimpleCPU.py
+++ b/src/cpu/simple/AtomicSimpleCPU.py
@@ -37,8 +37,6 @@ class AtomicSimpleCPU(BaseSimpleCPU):
     simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles")
     function_trace = Param.Bool(False, "Enable function trace")
     function_trace_start = Param.Tick(0, "Cycle to start function trace")
-    if build_env['FULL_SYSTEM']:
-        profile = Param.Latency('0ns', "trace the kernel stack")
     icache_port = Port("Instruction Port")
     dcache_port = Port("Data Port")
     physmem_port = Port("Physical Memory Port")

diff --git a/src/cpu/simple/TimingSimpleCPU.py b/src/cpu/simple/TimingSimpleCPU.py
index f2b14a175a0ddad963492d42cc8ce1e8179fee57..b7f044bfa476eabae8c53fe6a63fc64dcad43af3 100644 (file)
--- a/src/cpu/simple/TimingSimpleCPU.py
+++ b/src/cpu/simple/TimingSimpleCPU.py
@@ -34,8 +34,6 @@ class TimingSimpleCPU(BaseSimpleCPU):
     type = 'TimingSimpleCPU'
     function_trace = Param.Bool(False, "Enable function trace")
     function_trace_start = Param.Tick(0, "Cycle to start function trace")
-    if build_env['FULL_SYSTEM']:
-        profile = Param.Latency('0ns', "trace the kernel stack")
     icache_port = Port("Instruction Port")
     dcache_port = Port("Data Port")
     _mem_ports = BaseSimpleCPU._mem_ports + ['icache_port', 'dcache_port']