add binary interoperability section to rfc ls001

diff --git a/openpower/sv/rfc/Makefile b/openpower/sv/rfc/Makefile
index 0f091e0137e4a8a781bd185fd74a04da7e563acc..24b4e0960280bd691b1a837d522850b70a176d04 100644 (file)
--- a/openpower/sv/rfc/Makefile
+++ b/openpower/sv/rfc/Makefile
@@ -3,4 +3,5 @@ all: ls001.pdf
 ls001.pdf: ls001.mdwn
        pandoc -V geometry:margin=0.25in \
               -V fontsize=9pt \
+              -V papersize=a4 \
             -f markdown ls001.mdwn -s -o ls001.pdf

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index 60e27cd9912a1e6f8edae7b4dec4b619482ed49e..101ce3467443ee6e0f13447c3c73723f38563fa5 100644 (file)
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -61,6 +61,20 @@ the two types of Compliancy Levels*. The resources below therefore are
 not all required for all SV Compliancy Levels but they are all required
 to be reserved.
 
+# Binary Interoperability
+
+Power ISA is long-term stable. A catastrophic mistake has been made in
+ARM SVE/2 and RISC-V RVV: "Silicon-Partner" Scalability, marketed as
+a feature, allows the same instructions to mean different things on
+different implementations (a different Vector bitwidth).  This means
+that binary interoperability is not only impossible to achieve but
+Illegal Instruction trap-and-emulate is also out of the question.
+
+**Simple-V guarantees binary interoperability** by defining fixed
+register file bitwidths and size for all instructions.  This does
+mean that **reserved** space is important to have in SVP64, in order
+to provide future expanded register file bitwidths and sizes.
+
 # Hardware Implementations
 
 The fundamental principle of Simple-V is that it sits between Issue and