Add defaultvalue attribute

Signed-off-by: Clifford Wolf <clifford@clifford.at>

diff --git a/README.md b/README.md
index 94ea9538ff4bd05bf6b40f2e0140db307fe7bfec..637703a7f2faf766d38b726d5e1dc43d18955f5a 100644 (file)
--- a/README.md
+++ b/README.md
@@ -350,6 +350,10 @@ Verilog Attributes and non-standard features
   through the synthesis. When entities are combined, a new |-separated
   string is created that contains all the string from the original entities.
 
+- The ``defaultvalue`` attribute is used to store default values for
+  module inputs. The attribute is attached to the input wire by the HDL
+  front-end when the input is declared with a default value.
+
 - In addition to the ``(* ... *)`` attribute syntax, Yosys supports
   the non-standard ``{* ... *}`` attribute syntax to set default attributes
   for everything that comes after the ``{* ... *}`` statement. (Reset

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 5f3d713d3a546404712327c894ca2db0e87247a1..ebb4369c37f482a717f617171328426cc00ae8b4 100644 (file)
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -345,6 +345,12 @@ module_arg_opt_assignment:
                if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) {
                        AstNode *wire = new AstNode(AST_IDENTIFIER);
                        wire->str = ast_stack.back()->children.back()->str;
+                       if (ast_stack.back()->children.back()->is_input) {
+                               AstNode *n = ast_stack.back()->children.back();
+                               if (n->attributes.count("\\defaultvalue"))
+                                       delete n->attributes.at("\\defaultvalue");
+                               n->attributes["\\defaultvalue"] = $2;
+                       } else
                        if (ast_stack.back()->children.back()->is_reg || ast_stack.back()->children.back()->is_logic)
                                ast_stack.back()->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, wire, $2))));
                        else
@@ -1360,6 +1366,11 @@ wire_name_and_opt_assign:
        wire_name '=' expr {
                AstNode *wire = new AstNode(AST_IDENTIFIER);
                wire->str = ast_stack.back()->children.back()->str;
+               if (astbuf1->is_input) {
+                       if (astbuf1->attributes.count("\\defaultvalue"))
+                               delete astbuf1->attributes.at("\\defaultvalue");
+                       astbuf1->attributes["\\defaultvalue"] = $3;
+               } else
                if (astbuf1->is_reg || astbuf1->is_logic)
                        ast_stack.back()->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, wire, $3))));
                else