Merge branch 'master' into xaig

diff --cc CHANGELOG
index 192fc5a8dfccdfeb1e7cf844deb2a8d33078f9c7,128f6c6ff546ff50c3345fec35fef37796fbb48a..0636e6bad465540a3dbc50036980fd8ff15d0687
--- 1/CHANGELOG
--- 2/CHANGELOG
+++ b/CHANGELOG
@@@ -16,14 -16,11 +16,16 @@@ Yosys 0.8 .. Yosys 0.8-de
      - Added "gate2lut.v" techmap rule
      - Added "rename -src"
      - Added "equiv_opt" pass
 +    - Added "shregmap -tech xilinx"
      - Added "read_aiger" frontend
 -    - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"
+     - Added "muxcover -mux{4,8,16}=<cost>"
+     - Added "muxcover -dmux=<cost>"
+     - Added "muxcover -nopartial"
-     - Extended "muxcover -mux{4,8,16}=<cost>"
 +    - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
 +    - Added "synth_xilinx -abc9" (experimental)
 +    - Added "synth_ice40 -abc9" (experimental)
 +    - Added "synth -abc9" (experimental)
 +    - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
      - Fixed sign extension of unsized constants with 'bx and 'bz MSB