add PLL reset stability time option (defaults to 18 bits)

to fpga/top-generic.vhdl

diff --git a/fpga/top-generic.vhdl b/fpga/top-generic.vhdl
index 66c65cc2cc34561f9be7c12ca1357a4aad432b1d..3aabe93540bfc3872d36549d50feb3566f1df822 100644 (file)
--- a/fpga/top-generic.vhdl
+++ b/fpga/top-generic.vhdl
@@ -10,6 +10,7 @@ entity toplevel is
        MEMORY_SIZE   : positive := (384*1024);
        RAM_INIT_FILE : string   := "firmware.hex";
        RESET_LOW     : boolean  := true;
+       PLL_RESET_BITS     : positive  := 18;
        EXTERNAL_CORE     : boolean  := false;
        SIM_MAIN_BRAM     : boolean  := false;
        SIM_BRAM_CHAINBOOT  : positive  := 0;
@@ -62,7 +63,8 @@ begin
 
     reset_controller: entity work.soc_reset
        generic map(
-           RESET_LOW => RESET_LOW
+           RESET_LOW => RESET_LOW,
+        PLL_RESET_BITS => PLL_RESET_BITS
            )
        port map(
            ext_clk => ext_clk,