Fix store to clear debug interrupt.

diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc
index b31c4a689d6dfcb559a1a9b9f405e7c055b433e0..75bb3357ea793f2bd587cb0f34900ed0ddf66fd5 100644 (file)
--- a/riscv/debug_module.cc
+++ b/riscv/debug_module.cc
@@ -35,8 +35,8 @@ bool debug_module_t::store(reg_t addr, size_t len, const uint8_t* bytes)
     memcpy(raw_page + addr - DEBUG_START, bytes, len);
     return true;
   } else if (len == 4 && addr == DEBUG_CLEARDEBINT) {
-    clear_interrupt(bytes[4] | (bytes[5] << 8) |
-        (bytes[6] << 16) | (bytes[7] << 24));
+    clear_interrupt(bytes[0] | (bytes[1] << 8) |
+        (bytes[2] << 16) | (bytes[3] << 24));
     return true;
   }
 
@@ -54,6 +54,15 @@ void debug_module_t::ram_write32(unsigned int index, uint32_t value)
   base[3] = (value >> 24) & 0xff;
 }
 
+uint32_t debug_module_t::ram_read32(unsigned int index)
+{
+  char* base = raw_page + DEBUG_RAM_START - DEBUG_START + index * 4;
+  return base[0] |
+    (base[1] << 8) |
+    (base[2] << 16) |
+    (base[3] << 24);
+}
+
 char* debug_module_t::page(reg_t paddr)
 {
   fprintf(stderr, "dm::page(0x%lx)\n", paddr);

diff --git a/riscv/debug_module.h b/riscv/debug_module.h
index 10554a8f1e0b86d992df099afc00ea343569c12a..040ad1be3943c67b2b96a614a7d0ba9c97f3e601 100644 (file)
--- a/riscv/debug_module.h
+++ b/riscv/debug_module.h
@@ -16,6 +16,7 @@ class debug_module_t : public abstract_device_t
     char* page(reg_t paddr);
 
     void ram_write32(unsigned int index, uint32_t value);
+    uint32_t ram_read32(unsigned int index);
 
     void set_interrupt(uint32_t hartid) {
       interrupt.insert(hartid);

diff --git a/riscv/gdbserver.cc b/riscv/gdbserver.cc
index 6840cb785e38a30df0d8233533185d22191bd135..738556c2bf7044096aa8308f58f52c083c95839a 100644 (file)
--- a/riscv/gdbserver.cc
+++ b/riscv/gdbserver.cc
@@ -167,6 +167,11 @@ void gdbserver_t::write_debug_ram(unsigned int index, uint32_t value)
   sim->debug_module.ram_write32(index, value);
 }
 
+uint32_t gdbserver_t::read_debug_ram(unsigned int index)
+{
+  return sim->debug_module.ram_read32(index);
+}
+
 void gdbserver_t::halt()
 {
   processor_t *p = sim->get_core(0);
@@ -763,6 +768,8 @@ void gdbserver_t::handle()
     if (state == STATE_HALTING && sim->debug_module.get_interrupt(p->id) == 0) {
       // gdb requested a halt and now it's done.
       send_packet("T05");
+      fprintf(stderr, "DPC: 0x%x\n", read_debug_ram(0));
+      fprintf(stderr, "DCSR: 0x%x\n", read_debug_ram(2));
       state = STATE_HALTED;
     }
 

diff --git a/riscv/gdbserver.h b/riscv/gdbserver.h
index 7ac8823e739980a64939fd5aa2716358e283c626..5a7a102797e85270f72ed8fc5506928ae0317c41 100644 (file)
--- a/riscv/gdbserver.h
+++ b/riscv/gdbserver.h
@@ -126,6 +126,7 @@ private:
 
   // Write value to the index'th word in Debug RAM.
   void write_debug_ram(unsigned int index, uint32_t value);
+  uint32_t read_debug_ram(unsigned int index);
 };
 
 #endif